Effects of post-deposition anneal on the electrical properties ofSi3N4 gate dielectric

The effects of postdeposition anneal of chemical vapor deposited silicon nitride are studied. The Si₃N₄ films were in situ annealed in either H₂(2%)/O₂ at 950°C or N₂O at 950°C in a rapid thermal oxidation system. It is found that an interfacial oxide was grown at the Si₃N₄/Si interface by both postdeposition anneal conditions. This was confirmed by thickness measurement and X-ray photoelectronic spectroscopy (XPS) analysis. The devices with H₂ (2%)/O₂ anneal exhibit a lower gate leakage current and improved reliability compared to that of N₂O anneal. This improvement is attributed to a greater efficiency of generating atomic oxygen in the presence of a small amount of hydrogen, leading to the elimination of structural defects in the as-deposited Si₃N ₄ film by the atomic oxygen. Good drivability is also demonstrated on a 0.12 μm n-MOSFET device     

Effects of Ti content and wet-N2 anneal on Ge MOS capacitors with HfTiO gate dielectric

Thin HfTiO gate dielectric is deposited by reactive co-sputtering method followed by wet or dry N₂ anneal. The effects of Ti content on the performance of HfTiO gate dielectric are investigated by using different sputtering powers for the Ti target. Experimental results indicate that as the Ti content increases, the dielectric constant (κ) can increase up to 40 for a Ti content of 28%. However, when the Ti content is too high, the interface properties and gate leakage properties are deteriorated. On the contrary, results show that owing to the hydrolyzable property of GeO_x, the wet-N₂ anneal can greatly suppress the growth of unstable low-κ GeO_x interlayer, resulting in lower interface-state density and gate leakage current, in addition to larger κ value. In this study, when the sputtering power of the Ti target is 80 W together with a 25-W power for the Hf target and a post-deposition anneal (PDA) in wet-N₂ ambient at 500 °C for 300 s, excellent device performance is achieved: equivalent oxide thickness of 0.72 nm, equivalent dielectric constant of 39, interface-state density of 6.5 × 10¹¹ eV⁻¹ cm⁻² and gate leakage current of 5.7 × 10⁻⁴ A/cm² at V_g = 1 V. Therefore, in order to obtain high-quality HfTiO gate dielectric for small-scaled Ge MOS devices, not only should the Ti content be optimized, the PDA should also be done in a wet-N₂ ambient.     

Thermally-enhanced remote plasma nitrided ultrathin (1.65 nm) gateoxide with excellent performances in reduction of leakage current andboron diffusion

Ultrathin thermally enhanced remote plasma nitrided oxides (TE-RPNO) with equivalent oxide thickness down to 1.65 nm are fabricated to investigate their leakage current reduction and boron diffusion barrier performances. A PMOSFET with TE-RPNO, compared to its conventional oxide counter-part, yields almost one order magnitude lower gate leakage current, less flatband voltage changes in high boron implantation dose or activation temperature, and shows broader process windows in the tradeoff between boron penetration and dopant activation     

Improvement of gate dielectric reliability for p+poly MOS devices using remote PECVD top nitride deposition on ultra-thin (2.4–6 nm) gate oxides

Dual layer dielectrics have been formed by remote PECVD deposition of ultra-thin (0.4–1.2 nm) nitrides onto thin thermal oxides grown on n-type Si(100) substrates. Activation of boron-implanted p+ polycrystalline silicon gate electrodes was accomplished by a high temperature anneal, 1–4 min at 1000°C. Boron penetration through the dielectric film to the n-type substrate was investigated by performing a quasi-static C–V analysis and monitoring the flatband voltage shift. Boron penetration was effectively stopped by a 0.8 nm nitride film, and partially stopped by a 0.4 nm nitride film. In addition, the charge to breakdown as monitored by the Q_bd value to 50% cumulative failure was highest for the device with the 0.8 nm top nitride, and decreased significantly in the thermal oxide. However there were essentially no differences in the mid-gap interface state densities, D_it, between oxide and nitride/oxide gate dielectric structures with Al gate. It is concluded that the 0.8 nm of plasma nitride was sufficient to block boron atom out-diffusion from a heavily implanted p+ poly-silicon gate electrode under the conditions of an aggressive implant activation anneal to improve the dielectric reliability.     

Multi-objective genetic algorithms based approach to optimize the electrical performances of the gate stack double gate (GSDG) MOSFET

In this paper, a Multi-Objective Genetic Algorithm (MOGA)-based approach is proposed to study and optimize the electrical behavior of Gate Stack Double Gate (GSDG) MOSFET for deep submicron CMOS digital and analog circuit applications. The analytical models, which describe the electrical behavior, of the (GSDG) MOSFET such as OFF-current, threshold voltage roll-off, drain induced barrier lowering (DIBL), subthreshold swing and transconductance have been ascertained. The proposed compact models are used to formulate the objective functions, which are the pre-requisite of multi-objective genetic algorithms. The problem is then presented as a multi-objective optimization one where the subthreshold and saturation parameters are considered simultaneously. The proposed approach is used to find the optimal electrical and dimensional transistor parameters in order to obtain and explore the better transistor performances for analog and digital CMOS-based circuit applications.     

Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI

In this study, we integrate and compare the electrical performances of metal/high-K embedded gates in 3D multi-channel CMOSFETs (MCFETs) on SOI. The electrical characteristics of embedded gates obtained by filling cavities with TiN/HfO₂, TiN/SiO₂ or N⁺ poly-Si/SiO₂ are compared to a planar reference. In particular, we investigate electron and hole mobility behaviours (300 K down to 20 K) in embedded and planar structures, the gate leakage current and the negative bias temperature instability (NBTI). Despite a lower mobility, TiN/HfO₂ gate stack demonstrates the best I_ON/I_OFF compromise and exhibits NBTI life time higher than 10 years up to 1.3 V.     

The effect of remote plasma nitridation on the integrity of theultrathin gate dielectric films in 0.13 μm CMOS technology and beyond

The authors report the effect of the remote plasma nitridation (RPN) process on characteristics of ultrathin gate dielectric CMOSFETs with the thickness in the range of 18 Å~22 Å. In addition, the effect of RPN temperature on the nitrogen-profile within the gate dielectric films has been investigated. Experimental results show that the thinner the gate dielectric films, the more significant effect on reducing the gate current and thinning the thickness of gate dielectric films by the RPN process. Furthermore, the minimum dielectric thickness to block the penetration of B and N has been estimated based on the experimental results. The minimum RPN gate dielectric thickness is about 12 Å     

Time-dependent dielectric wearout technique with temperature effect for reliability test of ultrathin (<2.0 nm) single layer and dual layer gate oxides

Ultrathin gate oxide is essential for low supply voltage and high drive current for ULSI devices. The continuous scaling of oxide thickness has been a challenge on reliability characterization with conventional time-dependent dielectric breakdown (TDDB) technique. A new technique, the time-dependent dielectric wearout (TDDW), is proposed as a more practical and effective way to measure oxide reliability and breakdown compared to conventional TDDB methodology. The wearout of oxide is defined as the gate current reaches a critical current density with the circuit operating voltage level. It is shown that although a noisy soft breakdown always exists for ultrathin oxide, with constant-voltage stressing, a big runaway can also be observed for oxides down to 1.8 nm by monitoring the I–V characteristics at a reduced voltage. Devices are found still working after soft breakdowns, but no longer functional after the big runaway. However, by applying E-model to project dielectric lifetime, it shows that the dielectric lifetime is almost infinity for the thermal oxide at 1.8 nm range. It is also demonstrated that the dual voltage TDDW technique is also able to monitor the breakdown mechanism for nitride/oxide (N/O) dual layer dielectrics.     

Negative bias temperature instability on three oxide thicknesses (1.4/2.2/5.2 nm) with nitridation variations and deuteration

In these experiments, we explored various methods of nitridation of thermal oxide. Rapid thermal oxidation (RTO), rapid thermal oxidation with nitric oxide (RTNO), remote plasma nitridation (RPN), and decoupled plasma nitridation (DPN) processes were performed, and the result on 1.4, 2.2, and 5.2 nm oxides was measured. It is shown that the initial threshold voltage and the shift during negative bias temperature instability (NBTI) stress are proportional to the nitrogen in the oxide. Not surprisingly the threshold voltage is dependent on the interfacial nitrogen, but it was also found that the NBTI shift depends on the total nitrogen incorporated throughout the bulk of the insulator. The thinnest oxide showed boron penetration for the unnitrided split, but also very low NBTI shift. Furthermore, wafers from each of the aforementioned nitridation variants were processed with and without deuterium passivation. Although the NFET hot–carrier response is substantially improved, no significant advantage in NBTI shift is observed.     

Investigation of BTI characteristics and its behavior on 10 nm SRAM with high-k/metal gate FinFET technology having multi-VT gate stack

Bias-Temperature Instability (BTI) is one of the key device reliability concerns for both digital and analog circuit operations. Features of work-function metal (WFM) for V_T modulation in 10 nm FinFET process technology results in WFM dependent BTI characteristics. Similar levels of aging degradation to those of previous 14 nm technology were observed in both DC and AC operations. As BTI-induced V_T variability is expected to increase with 3D fin dimension scaling, such variability must be accurately characterized and considered for circuit designs. This paper reports the impact of transistor- level BTI degradation on circuits by studying Ring Oscillator (RO) and SRAM. The SRAM cell stabilities in terms of SNM (Static Noise Margin) and WRM (Write Margin) were further studied through SRAM HTOL stresses by characterizing V_min shift. Robust 10 nm SRAM and product level HTOL reliability up to 500 h were demonstrated.     

Effects of voltage stress on the single event upset (SEU) response of 65 nm flip flop

A newly integrated pulsed laser system has been utilized to investigate the effects of voltage stress on single event upset (SEU) of flip flop chain manufactured in 65 nm bulk CMOS technology. Laser mappings of the flip flop chain revealed that the SEU sensitive regions increased with laser energy. Post-processing of the data from the laser mapping facilitated the plotting of the cross-section versus laser energy curve. We found a clear shift in the cross-section curves after voltage stress of 130 h. Comparisons of data revealed at least a doubled increase in sensitive areas after voltage stress. During the voltage stress, various electrical parameters were monitored and changes were observed. It was found that the increase in SEU sensitivity is related to electrical parameter changes and SPICE simulation results concur likewise.     

Monitoring the degradation that causes the breakdown of ultrathin(<5 nm) SiO2 gate oxides

The degradation of ultrathin oxides subjected to constant-current stresses is analyzed using two independent procedures. First, the injected charge to breakdown is estimated from the stress-induced leakage current (SILC) evolution during the stress. Second, the degradation that leads to the breakdown is directly measured using a two-step stress test. The evolution of the SILC during constant-current stresses proceeds at a rate that decreases with time. Moreover, under low current density stress conditions the normalized SILC at breakdown is no longer constant. However, our two-step test methodology shows that the degradation of the oxide evolves roughly linearly until the breakdown. These apparently contradictory results can be reconciled assuming that the degradation at breakdown is independent of the stress conditions and using the initial SILC generation rate to calculate the charge-to-breakdown by linear extrapolation. The implications for the use of SILC data as a degradation monitor are discussed     

Breakdown spots of ultra-thin (EOT < 1.5 nm) HfO2/SiO2 stacks observed with enhanced—CAFM

In this work, the (gate) current versus (gate) voltage (I–V) characteristics and the dielectric breakdown (BD) of an ultra-thin HfO₂/SiO₂ stack is studied by enhanced conductive atomic force microscopy (ECAFM). The ECAFM is a CAFM with extended electrical performance. Using this new set up, different conduction modes have been observed before BD. The study of the BD spots has revealed that, as for SiO₂, the BD of the stack leads to modifications in the topography images and high conductive spots in the current images. The height of the hillocks observed in the topography images has been considered an indicator of structural damage.     

Effect of Halo structure variations on the threshold voltage of a 22 nm gate length NMOS transistor

This paper reports on the effects of the Halo structure variations on threshold voltage (V_th) in a 22 nm gate length high-k/metal gate planar NMOS transistor. Since the V_th is one of the important physical parameter for determining the functionality of complementary metal-oxide–semiconductor device, this experiment will focus on finding the best combination on process parameter to achieve the best value of V_th. The Halo structure variable process parameters are the Halo implantation dose, the Halo implantation tilting angle, the Source/Drain implantation dose and the compensation implantation dose. The design of the planar device consists of a combination of high permittivity material (high-k) and a metal gate. Titanium dioxide was used as the high-k material instead of the traditional SiO₂ dielectric and tungsten silicide was used as the metal gate. The optimization process was executed using Taguchi's L₉ array to obtain a robust design. Taguchi's Nominal-the-Best signal-to-noise ratio was used in an effort to minimize the variance of V_th. The results show that the V_th values have least variance and the mean value can be adjusted to 0.289 V±12.7% which is in line with projections made by the International Technology Roadmap for Semiconductors.     

Electrical characterization and quantum modeling of MOS capacitors with ultra-thin oxides (1.4–3 nm)

Electrical characterization of MOS capacitors with ultra-thin oxides (1.4–3 nm) has been carried out. The validity of the correction to C–V data, needed to take into account the series resistance and leakage current, is discussed. The gate current in accumulation and in depletion regions has been investigated and properly modeled based on detailed analysis of tunneling from the polygate.     

Low-leakage MIS structures with 1.5-6 nm CaF2 insulating layer on Si(1 1 1)

Thin high-quality calcium fluorite films are grown on (1 1 1) silicon in the low- and middle- temperature molecular-beam epitaxy processes followed by annealing. Metal-insulator-semiconductor structures with such films exhibit much smaller leakage currents than the casual structures with silicon dioxide. They demonstrate also satisfactory wear-out characteristics. Low leakage is achieved not due to high permittivity, but due to restricted tunnel transparency of the fluorite owing to a large effective mass of carriers. Therefore, CaF₂ is a promising candidate for gate material in advanced field-effect transistors.     

A methodology for the implementation of MOSFETs with a high-k dielectric gate material on the design of 90 nm technology circuits

Up to date, MOSFETs have been made through well established techniques that use SiO₂ as the gate dielectric and the related design issues are well established. The need to scale down device dimensions allowed researchers to seek for alternative materials, in order to replace SiO₂ as the gate dielectric. The implementation of such MOS devices in memory or logic circuits needs to take into account the effects that the use of the new gate dielectrics has on parameters such as the threshold voltage and the drain current. Hence, parameters such as the high dielectric constant values, extra oxide charges and process related defects at the physical level must be taken into account during the device design. As far as circuit applications are concerned, these changes may substantially affect the required performance. This paper presents and provides proposals about the issue of replacing commonly used parameters of the MOSFET modelling with new parameters, in which the presence of a gate dielectric with different properties from those of SiO₂ is taken into account. A stepwise procedure is described for the new device design. Moreover, a case study is presented which examines a memory circuit built up by such new technology devices. In particular, this paper presents and analyses the design of a DRAM cell made up of MOSFETs with an alternative gate dielectric. The 90 nm technology and the BSIM4 model equations are used to derive the single MOSFET behaviour and subsequently the DRAM circuit performance. The results are analysed and compared to those obtained from conventional SiO₂ devices. A cell layout is provided and the DRAM circuit characteristics are also presented.     

Characterisation and passivation of interface defects in (1 0 0)-Si/SiO2/HfO2/TiN gate stacks

The density and energy distribution of electrically active interface defects in the (1 0 0)Si/SiO₂/HfO₂ system are presented. Experimental results are analysed for HfO₂ thin films deposited by atomic layer deposition and metal-organic chemical vapour deposition on (1 0 0)Si substrates. The paper discusses the origin of the interface states, and their passivation in hydrogen over the temperature range 350–550 °C.     

Investigation of high-K gate stacks with epitaxial Gd2O3 and FUSI NiSi metal gates down to CET=0.86 nm

Novel gate stacks with epitaxial gadolinium oxide (Gd₂O₃) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10^–7 A cm^–2 are observed at a capacitance equivalent oxide thickness of CET=1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd₂O₃ thickness of 3.1 nm yield current densities down to 0.5 A cm⁻² at V_g=+1 V. The extracted dielectric constant for these gate stacks ranges from k=13 to 14. These results emphasize the potential of NiSi/Gd₂O₃ gate stacks for future material-based scaling of CMOS technology.     

Oxynitride gate dielectric grown in nitric oxide (NO): the effectof reoxidation on dielectric reliability of the active edge

Reoxidation of an oxynitride gate dielectric grown by NO anneal of thermal oxide has been studied. This process has demonstrated ~3-5X improvement of Q_BD of active edge intensive capacitors in comparison to thermal oxide, N₂O and NO oxynitride. This improvement is believed to be due to the reduction of local thinning of the gate dielectric at the field oxide edge which also reduces local build-up of positive charge near the gate electrode at the isolation edges