Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

The authors present a study on the layout dependence of the silicon-germanium source/drain (Si/sub 1-x/Ge/sub x/ S/D) technology. Experimental results on Si/sub 1-x/Ge/sub x/ S/D transistors with various active-area sizes and polylengths are combined with stress simulations. Two technologically important configurations are investigated: the nested transistor, where a polygate is surrounded by other gates, and isolated transistors, where the active area is completely surrounded by isolation oxide. The channel stress, caused by epitaxial Si/sub 1-x/Ge/sub x/ is reduced substantially when the active area is decreased from a large size towards typical values for advanced CMOS technology nodes. Nested transistors with longer gate lengths are more sensitive towards layout scaling than shorter gates. Increasing recess depth and germanium concentration gives larger channel stress, but does not change layout sensitivity. Increased lateral etching leads to higher stress, as well as to reduced layout sensitivity. In small-size transistors, there exists an optimal recess depth, beyond which the stress in the channel will not increase further. For isolated transistor structures, the interaction between Si/sub 1-x/Ge/sub x/ and the isolating oxide can even lead to stress reduction when the recess depth is increased. When technology advances, active-area dimensions will be scaled together with gate lengths and widths. For typical sizes of advanced silicon CMOS Si/sub 1-x/Ge/sub x/ S/D transistors, simulations indicate that the channel stress can be maintained in future technology nodes.     

相变材料Ge2Sb2Te5的性质及其面向新型数据存储的应用

信息时代产生的海量数据驱动着计算机存储架构的革新,高性能的非易失性存储器和存算一体的神经形态计算成为存储体系的发展方向。首先,介绍了相变材料Ge2Sb2Te5的阻变性质的机理与应用,详细阐述了相变存储器的发展以及神经形态计算的实现。然后,讨论了基于Ge2Sb2Te5铁电性质的存储器、基于Ge2Sb2Te5介电性质的光子存储单元和基于Ge2Sb2Te5应变作用的高迁移率晶体管。最后,讨论了Ge2Sb2Te5和n型硅等材料的异质结结构在器件中的应用。基于Ge2Sb2Te5材料多种特性的新型存储器件必将在未来存算一体的数据处理中扮演重要的角色。     

Emerging technologies in Si active photonics

Silicon photonics for synergistic electronic–photonic integration has achieved remarkable progress in the past two decades. Active photonic devices, including lasers, modulators, and photodetectors, are the key challenges for Si photonics to meet the requirement of high bandwidth and low power consumption in photonic datalinks. Here we review recent efforts and progress in high-performance active photonic devices on Si, focusing on emerging technologies beyond conventional foundry-ready Si photonics devices. For emerging laser sources, we will discuss recent progress towards efficient monolithic Ge lasers, mid-infrared GeSn lasers, and high-performance InAs quantum dot lasers on Si for data center applications in the near future. We will then review novel modulator materials and devices beyond the free carrier plasma dispersion effect in Si, including GeSi and graphene electro-absorption modulators and plasmonic-organic electro-optical modulators, to achieve ultralow power and high speed modulation. Finally, we discuss emerging photodetectors beyond epitaxial Ge p–i–n photodiodes, including GeSn mid-infrared photodetectors, all-Si plasmonic Schottky infrared photodetectors, and Si quanta image sensors for non-avalanche, low noise single photon detection and photon counting. These emerging technologies, though still under development, could make a significant impact on the future of large-scale electronicSilicon photonics for synergistic electronic-photonic integration has achieved remarkable progress in the past two decades. Active photonic devices, including lasers, modulators, and photodetectors, are the key challenges for Si photonics to meet the requirement of high bandwidth and low power consumption in photonic datalinks. Here we review recent efforts and progress in high-performance active photonic devices on Si, focusing on emerging technologies beyond conventional foundry-ready Si photonics devices. For emerging laser sources, we will discuss recent progress towards efficient monolithic Ge lasers, mid-infrared GeSn lasers, and high-performance InAs quantum dot lasers on Si for data center applications in the near future. We will then review novel modulator materials and devices beyond the free carrier plasma dispersion effect in Si, including GeSi and graphene electro-absorption modulators and plasmonic-organic electro–optical modulators, to achieve ultralow power and high speed modulation. Finally, we discuss emerging photodetectors beyond epitaxial Ge p–i–n photodiodes, including GeSn mid-infrared photodetectors, all-Si plasmonic Schottky infrared photodetectors, and Si quanta image sensors for non-avalanche, low noise single photon detection and photon counting. These emerging technologies, though still under development, could make a significant impact on the future of large-scale electronic–photonic integration with performance inaccessible from conventional Si photonics technologies-photonic integration with performance inaccessible from conventional Si photonics technologies.     

Crystallinity‐Controlled Germanium Nanowire Arrays: Potential Field Emitters

We report a simple method, oblique angle deposition, to directly synthesize aligned Ge nanowire arrays on a Si substrate. This process is accomplished by tilting the Si substrate and adjusting the incident angle of the evaporated Ge vapor flux with respect to the substrate normal to 87°. The resultant crystallinity of the Ge nanostructures can be tuned to either amorphous or poly‐ and single‐crystalline, depending on the substrate temperature and evaporation rate. The effects of thermal treatment on the morphology and structure of the Ge nanowires are discussed in detail. The field‐emission measurements show that increasing the annealing temperatures to about 550 °C results in a gradual increase in the maximum current density and a decrease in the turn‐on voltage, because of the decreased wire density originating from melting of the Ge nanowires. The field‐enhancement factor analysis shows there is an optimum range for Ge wire density and aspect ratio to obtain good emission performance. Ge nanowire arrays might find potential application in the field emitters of the future.     

Si基Ge/SiGeⅠ型量子阱结构的理论设计和实验研究

基于能带工程理论,设计了Si基Ge/SiGeⅠ型量子阱结构。采用超高真空化学气相淀积系统,制备出高质量的Si基Ge/SiGe多量子阱系列材料。当样品中Ge量子阱宽从15nm减少到12nm和11nm时,室温下荧光(PL)光谱观测到量子限制效应引起的直接带跃迁发光峰位的蓝移,峰位的实验值与理论值符合得很好;当Ge量子阱宽逐渐减小到9nm和7nm时,测试得到样品的PL谱峰位却与理论预期出现了较大的差值。进一步的实验表明,这主要是由于量子阱厚度小到一定程度时,量子阱的直接带发光受到抑制,其发光主要源于Ge虚拟衬底。     

Controllable growth of GeSi nanostructures by molecular beam epitaxy

We present an overview on the recent progress achieved on the controllable growth of diverse GeSi alloy nanostructures by molecular beam epitaxy. Prevailing theories for controlled growth of Ge nanostructures on patterned as well as inclined Si surfaces are outlined firstly, followed by reviews on the preferential growth of Ge nanoislands on patterned Si substrates, Ge nanowires and high density nanoislands grown on inclined Si surfaces, and the readily tunable Ge nanostructures on Si nanopillars. Ge nanostructures with controlled geometries, spatial distributions and densities, including two-dimensional ordered nanoislands, three-dimensional ordered quantum dot crystals, ordered nanorings, coupled quantum dot molecules, ordered nanowires and nanopillar alloys, are discussed in detail. A single Ge quantum dot-photonic crystal microcavity coupled optical emission device demonstration fabricated by using the preferentially grown Ge nanoisland technique is also introduced. Finally, we summarize the current technology status with a look at the future development trends and application challenges for controllable growth of Ge nanostructures.     

硅缓冲层提高选区外延生长硅基锗薄膜质量

研究了Si缓冲层对选区外延Si基Ge薄膜的晶体质量的影响。利用超高真空化学气相沉积系统,结合低温Ge缓冲层和选区外延技术,通过插入Si缓冲层,在Si/SiO_2图形衬底上选择性外延生长Ge薄膜。采用X射线衍射(XRD)、扫描电子显微镜(SEM)、原子力显微镜(AFM)表征了Ge薄膜的晶体质量和表面形貌。测试结果表明,选区外延Ge薄膜的晶体质量比无图形衬底外延得到薄膜的晶体质量要高;选区外延Ge薄膜前插入Si缓冲层得到Ge薄膜具有较低的XRD曲线半高宽以及表面粗糙度,位错密度低至5.9×10~5/cm^2,且薄膜经过高低温循环退火后,XRD曲线半高宽和位错密度进一步降低。通过插入Si缓冲层可提高选区外延Si基Ge薄膜的晶体质量,该技术有望应用于Si基光电集成。     

量子点红外探测器研究进展

量子点红外光电探测器(QDIP)凭借自身的优点,未来很有可能与碲镉汞(HgCdTe)红外探测器、量子阱红外光电探测器(QWIP)和非制冷微测辐射热计相竞争。目前,普遍采用自组织方法生长量子点,研究主要集中在:①隧道量子点红外探测器(T-QDIP);②量子阱中量子点(DWELL)红外探测器;③Si基QDIP;④Ge QDIP。本文阐述正在研究的几种QDIP,并对下一代传感器用QDIP进行预测。     

Electrical Analyses of Germanium MIS Structure and Spectroscopic Measurement of the Interface Trap Density in an Insulator/Germanium Interface at Room Temperature

In this paper, we present an equivalent circuit model of a germanium (Ge) MIS structure that is biased in the inversion region, which includes the effects of the high intrinsic carrier density and high diffusion-limited conductance of the Ge substrate at room temperature. The model can successfully express the gate bias and frequency dependences of the capacitance characteristics that are specific to the Ge MIS capacitor. Moreover, it will be shown that the interface trap density and its gate bias dependence in the inversion region can be spectroscopically determined from the gate bias and measurement frequency dependences of the equivalent parallel conductance of the Ge surface.     

Wide-bandgap compound semiconductors for X- or gamma-ray detectors

Although Ge and Si are currently the major semiconductor materials for nuclear-radiation detectors used in high-resolution nuclear spectroscopy, and will remain so in the foreseeable future, their limitations that hamper their use in field and industrial environments have given the impetus for research into alternative semiconductors that would be suitable for wider areas of application and would operate at room temperature. Requirements are formulated for semiconductors in which to make room-temperature detectors of X- or gamma-rays. A brief overview is given of the work in Russia on such detectors using a wide-bandgap compound semiconductor, namely, CdTe, GaAs, HgI₂, or TlBr. The standard of semiconductor-materials technology is shown to be a key factor in developing this type of detector.     

Bandgap engineering of amorphous semiconductors for solar cell applications

Different bandgap engineering approaches are discussed with respect to their application in thin-film solar cells based on hydrogenated amorphous silicon (a-Si: H) and its alloys with Ge or C. After a survey of the different approaches reported so far in the literature, the main emphasis will lie on the application of a-Si: H/a-Si_1-xC_x:H multilayers for use in the p-doped window layer, or a graded bandgap a-Si _1-xC_x:Hintrinsic layer with varying Ge content x. But also the possibility of using an a-Si: H/a-Si_1-xC_x:H multilayer as the i-layer will be addressed. Intrinsic films of both multilayers and graded bandgap material have been deposited in different series, varying electronic well and barrier widths in the first case, and the amount, form or local position of a change of the bandgap in the second case. Physical properties of both classes of materials have been investigated thoroughly. the results are discussed with respect to an application in amorphous thin-film solar cells, also taking into account results from the literature about the implementation of these heterostructures in devices. Conclusions for the future perspectives of these approaches are drawn.     

The Ge condensation technique: A solution for planar SOI/GeOI co-integration for advanced CMOS technologies?

This paper presents a general study on the germanium (Ge) condensation technique to assess its potential, issues and applications for advanced metal oxide semiconductor field effect transistor (MOSFET) technologies. The interest in such process for fabrication of ultrathin germanium on insulator (GeOI) layers for fully depleted GeOI MOSFETs application is first described. We highlight the impact of initial silicon on insulator (SOI) substrates uniformity on the process, determined as the key parameter to be improved. Next, a global procedure is described for MOSFETs integration on Ge layers grown on 75% Ge-enriched silicon germanium on insulator (SGOI) substrates obtained by the Ge condensation technique. A third section reviews the different local Ge condensation techniques for fabrication of SOI–GeOI hybrid substrates. Interests of such substrates for SOI–GeOI planar co-integration either at the microprocessor, at the cell or at the transistor level will be discussed. Finally, the fabrication of a first 50-nm-thick SOI–GeOI hybrid substrate is described.     

Research progress of Ge on insulator grown by rapid melting growth

Ge is an attractive material for Si-based microelectronics and photonics due to its high carries mobility, pseudo direct bandgap structure, and the compatibility with complementary metal oxide semiconductor (CMOS) processes. Based on Ge, Ge on insulator (GOI) not only has these advantages, but also provides strong electronic and optical confinement. Recently, a novel technique to fabricate GOI by rapid melting growth (RMG) has been described. Here, we introduce the RMG technique and review recent efforts and progress in RMG. Firstly, we will introduce process steps of RMG. We will then review the researches which focus on characterizations of the GOI including growth dimension, growth mechanism, growth orientation, concentration distribution, and strain status. Finally, GOI based applications including high performance metal–oxide–semiconductor field effect transistors (MOSFETs) and photodetectors will be discussed. These results show that RMG is a promising technique for growth of high quality GOIs with different characterizations. The GOI grown by RMG is a potential material for the next-generation of integrated circuits and optoelectronic circuits.     

Ge-Interface Engineering With Ozone Oxidation for Low Interface-State Density

Passivation of Ge has been a critical issue for Ge MOS applications in future technology nodes. In this letter, we introduce ozone oxidation to engineer Ge/insulator interface. Density of interface states (D_it) across the bandgap and close to the conduction band edge was extracted using conductance technique at low temperatures. D_it dependence on growth conditions was studied. Minimum D_it of 3 times 10¹¹ cm^-2V^-1 was demonstrated. Physical quality of the interface was investigated through Ge 3d spectra measurements. We found that the interface and D_it are strongly affected by the distribution of oxidation states and the quality of the suboxide.     

GaInP/GaAs/Ge三结太阳电池辐照损伤效应及加固技术研究进展

文章首先重点介绍了国内外开展GaInP/GaAs/Ge三结太阳电池的电子、质子及其他辐射粒子或射线辐照实验的研究进展,然后从辐照损伤效应的仿真模拟研究、抗辐射加固技术、损伤预估方法等方面综述了GaInP/GaAs/Ge三结太阳电池辐照损伤效应及加固技术的研究进展,最后梳理了当前GaInP/GaAs/Ge三结太阳电池辐照损伤效应研究中亟待解决的关键技术问题,为深入开展GaInP/GaAs/Ge三结太阳电池辐照损伤效应实验方法标准制定、损伤机理分析、在轨寿命预估及抗辐射加固技术研究提供了理论指导和实验技术支持。     

Characterization of copper germanide as contact metal for advanced MOSFETs

The material and electrical characteristics of /spl epsiv/-Cu/sub 3/Ge as a contact metal were investigated. The samples were prepared by direct copper deposition on germanium wafers, followed by rapid thermal annealing. The /spl epsiv/-Cu/sub 3/Ge formed at 400 /spl deg/C has a resistivity of 6.8 /spl mu//spl Omega//spl middot/cm, which is lower than typical silicides for silicon CMOS. Cross-sectional transmission electron microscopy showed smooth germanide/germanium interface, with a series of nanovoids aligning close to the top surface. These voids are believed to be the results of Kirkendall effect arising from the different diffusion fluxes of copper and germanium. The specific contact resistivity of Cu/sub 3/Ge, obtained from four-terminal Kelvin structures, was found to be as low as 8/spl times/10/sup -8/ /spl Omega//spl middot/cm/sup 2/ for p-type germanium substrate. This low resistivity makes Cu/sub 3/Ge a promising candidate for future contact materials.     

Fabrication of asymmetric Ge Schottky tunneling source n-channel field-effect transistor and its characterization of tunneling conduction

An asymmetric Schottky tunneling source field-effect transistor (STS FET) is a prospective device structure to suppress the short channel effect and to reduce the off-state current. An obstacle to implement a STS FET with a high mobility Ge channel was to form a metal/Ge contact with a low electron barrier height (Φ_BN). Recently, we succeeded in the fabrication of a TiN/Ge contact with an extremely low Φ_BN. In this study, a Ge-STS n-channel FET was fabricated, here PtGe/Ge and TiN/Ge contacts were used as the source and the drain. The device showed well-behaved transistor operation. From the current-voltage measurements in the wide temperature range of 160–300 K, the conduction mechanism from the source to the channel is confirmed to be field emission tunneling. This result will be the first step toward achieving a high-performance Ge-STS n-FET.     

Enhanced Sensitivity of Small-Size (With 1-$mu hbox{m}$ Gate Length) Junction-Field-Effect-Transistor-Based Germanium Photodetector Using Two-Step Germanium Epitaxy by Ultrahigh Vacuum Chemical Vapor Deposition

In this letter, we demonstrate a scalable (with gate length of 1 mum) Ge photodetector based on a junction field-effect-transistor (JFET) structure with high sensitivity and improved response time. To overcome the low-detection-efficiency issue of typical JFET photodetectors, a high-quality Ge epilayer, as the gate of JFET, was achieved using a novel epigrowth technique. By laser surface illumination of 3 mW on the Ge gate, an I _ON/I _OFF ratio up to 185 was achieved at a wavelength of 1550 nm for the first time. In addition, the device shows a temporal response time of 110 ps with a rise time of 10 ps, indicating that the scalable Ge JFET photodetector is a promising candidate to replace large-size photodiodes in future optoelectronic integrated circuits and as an image sensor integrated with a CMOS circuit for its comparable size in respect to modern MOSFETs.     

清洗工艺对锗外延片表面点状缺陷的影响

锗外延片表面的雾、水印及点状缺陷等会影响太阳电池的性能和成品率,其中点状缺陷出现的比例最高。研究了锗抛光片清洗工艺对外延片表面点状缺陷的影响,获得了无点状缺陷、低粗糙度及高表面质量的锗单晶片。采用厚度为175μm p型<100>锗单面抛光片进行清洗试验,研究了SC-1溶液的不同清洗时间、清洗温度和去离子水冲洗温度对锗抛光片外延后点状缺陷的影响,分析了表面SiO_2残留和锗片表面粗糙度对外延片表面点状缺陷的影响。结果表明点状缺陷主要是由于锗单晶抛光片表面沾污没有彻底清洗干净以及清洗过程中产生新的缺陷造成的。采用氢氟酸溶液浸泡、SC-1溶液低温短时间清洗结合低温去离子水冲洗后的锗抛光片进行外延,用其制备的太阳电池光电转换效率由原来的25%提高到31%。     

Breakeven criteria for the GaInNAs junction in GaInP/GaAs/GaInNAs/Ge four‐junction solar cells

The four‐junction GaInP/GaAs/GaInNAs/Ge solar cell structure holds the promise of efficiencies exceeding those of the GaInP/GaAs/Ge three‐junction cell, which at present is the benchmark for high‐efficiency multijunction cell performance. The performance of GaInNAs junctions demonstrated to date has been insufficient for the realization of these projected efficiency gains, owing to poor minority‐carrier properties in the GaInNAs. However, incremental improvements in the GaInNAs junctions have brought this breakeven point within sight. In this paper, we use a semiempirical approach to estimate the efficiency of the GaInP/GaAs/GaInNAs/Ge four‐junction solar cell structure as a function of the performance parameters of the GaInNAs third junction. The results provide guidance on the extent to which the current and voltage of present‐day GaInNAs junctions will need to be improved in order for the resulting four‐junction cell to realize its potential for efficiencies higher than that of GaInP/GaAs/Ge benchmark. Published in 2002 by John Wiley & Sons, Ltd.