Temperature dependent electrical and dielectric properties of a metal/Dy2O3/n-GaAs (MOS) structure

This paper describes the structural properties, electrical and dielectric characteristics of thin Dy₂O₃ layer deposited on the n-GaAs substrate by electron beam deposition under ultra vacuum. Structural and morphological characterizations are investigated by atomic force microscopy (AFM) and X-ray diffraction measurements (XRD). The XRD shows that the elaborated Dy₂O₃ oxide has a cubic structure. The electrical and dielectric properties of Co/Au/Dy₂O₃/n-GaAs structure were studied in the temperature range of 80–500 K. The conductance and capacitance measurements were performed as a function of bias voltage and frequency. The dielectric constant (ε′), dielectric loss (ε″) and dielectric loss tangent (tanδ) of the structure are obtained from capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements. These parameters are found to be strong functions of temperature and bias voltage. A strong negative capacitance (NC) phenomenon has been observed in C–V; hence ε′–V plots for each temperature value take negative values. The following behavior of the C and ε′ in the forward bias region has been explained with the minority-carrier injection and relaxation theory. From DC conductance study, electronic conduction is found to be dominated by thermally activated hopping at high temperature. Activation energy is deduced from the variation of conductance with temperature. The interface state density (N_ss) of the structure is of the order 1.13×10¹³ eV⁻¹ cm⁻².     

Temperature dependent dielectric studies of Ni/n-GaP Schottky diodes by capacitance and conductance measurements

The dielectric properties of Ni/n-GaP Schottky diode were investigated in the temperature range 140–300 K by capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements. The effect of temperature on series resistance (R_s) and interface state density (N_ss) were investigated. The dependency of dielectric constant (ε′), dielectric loss (ε′′), loss tangent (tan δ), ac conductivity (σ_ac), real (M′) and imaginary (M′′) parts of the electric modulus over temperature were evaluated and analyzed at 1 MHz frequency. The temperature dependent characteristics of ε′ and ε′′ reveal the contribution of various polarization effects, which increases with temperature. The Arrhenius plot of σ_ac shows two activation energies revealing the presence of two distinct trap states in the chosen temperature range. Moreover, the capacitance–frequency (C–f) measurement over 1 kHz to 1 MHz was carried out to study the effect of localized interface states.     

The source of negative capacitance and anomalous peak in the forward bias capacitance-voltage in Cr/p-si Schottky barrier diodes (SBDs)

The frequency and voltage dependence of capacitance–voltage (C–V) and conductance-voltage (G/ω−V) characteristics of the Cr/p-Si metal semiconductor (MS) Schottky barrier diodes (SBDs) were investigated in the frequency and applied bias voltage ranges of 10 kHz to 5 MHz and (−4 V)−(+4 V), respectively, at room temperature. The effects of series resistance (R_s) and density distribution of interface states (N_ss), both on C–V and G/ω−V characteristics were examined in detail. It was found that capacitance and conductance, both, are strong functions of frequency and applied bias voltage. In addition, both a strong negative capacitance (NC) and an anomalous peak behavior were observed in the forward bias C–V plots for each frequency. Contrary to the behavior of capacitance, conductance increased with the increasing applied bias voltage and there happened a rapid increase in conductance in the accumulation region for each frequency. The extra-large NC in SBD is a result of the existence of R_s, N_ss and interfacial layer (native or deposited). In addition, to explain the NC behavior in the forward bias region, we drew the C–I and G/ω−I plots for various frequencies at the same bias voltage. The values of C decrease with increasing frequency at forward bias voltages and this decrease in the NC corresponds to an increase in conductance. The values of N_ss were obtained using a Hill–Coleman method for each frequency and it exhibited a peak behavior at about 30 kHz. The voltage dependent profile of R_s was also obtained using a Nicollian and Brews methods.     

Frequency and voltage dependency of interface states and series resistance in Al/SiO2/p-Si MOS structure

The capacitance–voltage (C–V) and conductance–voltage (G/ω–V) characteristics of Al/SiO₂/p-Si metal-oxide-semiconductor (MOS) Schottky diodes have been measured in the voltage range from ?3 to +3 V and frequency range from 5 KHz to 1 MHz at room temperature. It is found that both C and G/ω of the MOS capacitor are very sensitive to frequency. The fairly large frequency dispersion of C–V and G/ω–V characteristics can be interpreted in terms of the particular distribution of interface states at SiO₂/Si interface and the effect of series resistance. At relatively low frequencies, the interface states can follow an alternating current (AC) signal that contributes to excess capacitance and conductance. This leads to an anomalous peak of C–V curve in the depletion and accumulation regions. In addition, a peak at approximately ?0.2 V appears in the R_s–V profiles at low frequency. The peak values of the capacitance and conductance decrease with increasing frequency. The density distribution profile of interface state density (N_ss) obtained from C_HF–C_LF capacitance measurement also shows a peak in the depletion region.     

Dielectric characteristics of gamma irradiated Au/SnO2/n-Si/Au (MOS) capacitor

The dielectric characteristics of gamma irradiated Au/SnO₂/n-Si/Au (MOS) capacitor were studied. The MOS capacitor was irradiated by a ⁶⁰Co gamma radiation source with a dose rate of 0.69 kGy/h. The dielectric parameters such as dielectric constant (ε′), dielectric loss (ε″), loss factor (tan δ) and ac electrical conductivity (σ_ac) were calculated from the capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements. It is found that the C and G/ω values decrease with the increasing total dose due to the irradiation-induced defects at the interface. Also, the calculated values of ε′, ε″ and σ_ac are found to decrease with an increased radiation dose. This result indicates that the dielectric characteristics of the MOS capacitor are sensitive to gamma-ray dose.     

The effects of thermal annealing on the electrical characteristics of Au/n–InP/In diode

An Au/n–InP/In diode has been fabricated in the laboratory conditions and the current–voltage (I–V) and capacitance–voltage (C–V) characteristics of the diode have been measured in room temperature. In order to observe the effect of the thermal annealing, this diode has been annealed at temperatures 100 and 200 °C for 3 min in N₂ atmosphere. The characteristic parameters such as leakage current, barrier height and ideality factor of this diode have been calculated from the forward bias I–V and reverse bias C–V characteristics as a function of annealing temperature. Also the rectifying ratio of the diode is evaluated for as-deposited and annealed diode.     

Investigations on electrical characteristics and reliability properties of MOS capacitors using HfAlOx on n-GaAs substrates

Radio frequency sputtering system is employed to fabricate metal oxide semiconductor (MOS) capacitors using an ultra-thin layer of HfAlO_x dielectric deposited on n-GaAs substrates with and without a Si interface control layer incorporated in between the dielectric and the semiconductor. Measurements are performed to obtain capacitance voltage (C–V) and current voltage (I–V) characteristics for GaAs/Si/HfAlO_x and GaAs/HfAlO_x capacitors under different constant voltage and constant current stress conditions. The variation of different electrical parameters such as change in interface trap density, hysteresis voltage with various values of constant voltage stress and the dependence of flat band voltage, fractional change in gate leakage current density, etc. with stress time are extracted from the C–V and I–V data for capacitors with and without a Si interlayer. Further the trap charge density and the movement of trap centroid are investigated for various injected influences. The dielectric breakdown and reliability properties of the dielectric films are studied using constant voltage stressing. A high time-dependent dielectric breakdown (TDDB, t_bd ? 1350 s) is observed for HfAlO_x gate dielectric with a silicon inter-layer under the high constant voltage stress at 8 V. Compared to capacitors without a Si interlayer, MOS capacitors with a Si interlayer exhibit improved electrical and breakdown characteristics, and excellent interface and reliability properties.     

Determination of the laterally homogeneous barrier height of palladium Schottky barrier diodes on n-Ge (1 1 1)

We have studied the experimental linear relationship between barrier heights and ideality factors for palladium (Pd) on bulk-grown (1 1 1) Sb-doped n-type germanium (Ge) metal-semiconductor structures with a doping density of about 2.5×10¹⁵ cm^?3. The Pd Schottky contacts were fabricated by vacuum resistive evaporation. The electrical analysis of the contacts was investigated by means of current–voltage (I–V) and capacitance–voltage (C–V) measurements at a temperature of 296 K. The effective barrier heights from I–V characteristics varied from 0.492 to 0.550 eV, the ideality factor n varied from 1.140 to 1.950, and from reverse bias capacitance–voltage (C^?2–V) characteristics the barrier height varied from 0.427 to 0.509 eV. The lateral homogenous barrier height value of 0.558 eV for the contacts was obtained from the linear relationship between experimental barrier heights and ideality factors. Furthermore the experimental barrier height distribution obtained from I–V and (C^?2?V) characteristics were fitted by Gaussian distribution function, and their mean values were found to be 0.529 and 0.463 eV, respectively.     

Fabrication and electrical properties of Al/aniline green/n-Si/AuSb structure

The current–voltage (I–V), capacitance–voltage (C–V) and capacitance–frequency (C–f) characteristics of Al/aniline green(AG)/n-Si/AuSb structure were investigated at room temperature. A modified Norde's function combined with conventional forward I–V method was used to extract the parameters including barrier height (BH) and the series resistance. The barrier height and series resistance obtained from Norde's function was compared with those from Cheung functions, and it was seen that there was a good agreement between the BH values and series resistances from both methods. The C–V characteristics were performed at 10 and 500 kHz frequencies, and C–f characteristics were performed 0.0, +0.4 and −0.4 V.     

Determination of contact parameters of Ni/n-GaP Schottky contacts

The electrical analysis of Ni/n-GaP structure has been investigated by means of current–voltage (I–V), capacitance–voltage (C–V) and capacitance–frequency (C–f) measurements in the temperature range of 120–320 K in dark conditions. The forward bias I–V characteristics have been analyzed on the basis of standard thermionic emission (TE) theory and the characteristic parameters of the Schottky contacts (SCs) such as Schottky barrier height (SBH), ideality factor (n) and series resistance (R_s) have been determined from the I–V measurements. The experimental values of SBH and n for the device ranged from 1.01 eV and 1.27 (at 320 K) to 0.38 eV and 5.93 (at 120 K) for Ni/n-GaP diode, respectively. The interface states in the semiconductor bandgap and their relaxation time have been determined from the C–f characteristics. The interface state density N_ss has ranged from 2.08 × 10¹⁵ (eV^?1 m^?2) at 120 K to 2.7 × 10¹⁵ (eV^?1 m^?2) at 320 K. C_ss has increased with increasing temperature. The relaxation time has ranged from 4.7 × 10^?7 s at 120 K to 5.15 × 10^?7 s at 320 K.     

Characteristics of RF reactive sputter-deposited Pt/SiO2/n-InGaN MOS Schottky diodes

All RF sputtering-deposited Pt/SiO₂/n-type indium gallium nitride (n-InGaN) metal–oxide–semiconductor (MOS) diodes were investigated before and after annealing at 400 °C. By scanning electron microscopy (SEM), the thickness of Pt, SiO_2, n-InGaN layer was measured to be ~250, 70, and 800 nm, respectively. AFM results also show that the grains become a little bigger after annealing, the surface topography of the as-deposited film was smoother with the rms roughness of 1.67 nm and had the slight increase of 1.92 nm for annealed sample. Electrical properties of MOS diodes have been determined by using the current–voltage (I–V) and capacitance–voltage (C–V) measurements. The results showed that Schottky barrier height (SBH) increased slightly to 0.69 eV (I–V) and 0.82 eV (C–V) after annealing at 400 °C for 15 min in N₂ ambient, compared to that of 0.67 eV (I–V) and 0.79 eV (C–V) for the as-deposited sample. There was the considerable improvement in the leakage current, dropped from 6.5×10⁻⁷ A for the as-deposited to 1.4×10⁻⁷ A for the 400 °C-annealed one. The annealed MOS Schottky diode had shown the higher SBH, lower leakage current, smaller ideality factor (n), and denser microstructure. In addition to the SBH, n, and series resistance (R_s) determined by Cheungs׳ and Norde methods, other parameters for MOS diodes tested at room temperature were also calculated by C–V measurement.     

Electrical characterization of inorganic-on-organic diode based InP and poly(3,4-ethylenedioxithiophene)/poly(styrenesulfonate) (PEDOT:PSS)

The electronic properties of metal–organic semiconductor-inorganic semiconductor diode between InP and poly(3,4-ethylenedioxithiophene)/poly(styrenesulfonate) (PEDOT:PSS) polymeric organic semiconductor film have been investigated via current–voltage and capacitance–voltage methods. The Al/PEDOT:PSS/p-InP contact exhibits a rectification behavior with the barrier height value of 0.98 eV and with the ideality factor value of 2.6 obtained from their forward bias current voltage (I–V) characteristics at the room temperature greater than the conventional Al/p-InP (0.83 eV, n = 1.13). This increase in barrier height and ideality factor can be attributed to PEDOT:PSS film formed at Al/p-InP interface.     

MISFET structures with barium titanate as a dielectric layer for application in memory cells

This work shows investigations of La₂O₃ containing BaTiO₃ thin films deposited on Si substrates by Radio Frequency Plasma Sputtering (RF PS) of sintered BaTiO₃ + La₂O₃ (2 wt.%) target. Round, aluminum (Al) electrodes were evaporated on top of the deposited layers. Thus, metal–insulator–semiconductor (MIS) structures were created with barium titanate thin films playing the role of an insulator. The MIS structures enabled a subsequent electrical characterization of the studied film by means of current–voltage (I–V) and capacitance–voltage (C–V) measurements. Several electronic parameters, i.e., ε_ri, ρ, V_FB, ΔV_H were extracted from the obtained characteristics. Moreover, the paper describes technology process of MISFETs fabrication and possibility of their application as memory cells. The influence of voltage stress on transfer and output I–V characteristics of the transistors are presented and discussed.     

Effect of the work function of gate electrode on hysteresis characteristics of organic thin-film transistors with Ta2O5/polymer as gate insulator

Organic thin-film transistors (OTFTs) using high dielectric constant material tantalum pentoxide (Ta₂O₅) and benzocyclobutenone (BCBO) derivatives as double-layer insulator were fabricated. Three metals with different work function, including Al (4.3 eV), Cr (4.5 eV) and Au (5.1 eV), were employed as gate electrodes to study the correlation between work function of gate metals and hysteresis characteristics of OTFTs. The devices with low work function metal Al or Cr as gate electrode exhibited high hysteresis (about 2.5 V threshold voltage shift). However, low hysteresis (about 0.7 V threshold voltage shift) OTFTs were attained based on high work function metal Au as gate electrode. The hysteresis characteristics were studied by the repetitive gate voltage sweep of OTFTs, and capacitance–voltage (C–V) and trap loss-voltage (G_p/ω?V) measurements of metal–insulator–semiconductor (MIS) devices. It is proved that the hysteresis characteristics of OTFTs are relative to the electron injection from gate metal to Ta₂O₅ insulator. The electron barrier height between gate metal and Ta₂O₅ is enhanced by using Au as gate electrode, and then the electron injection from gate metal to Ta₂O₅ is reduced. Finally, low hysteresis OTFTs were fabricated using Au as gate electrode.     

Low-voltage,high speed inkjet-printed flexible complementary polymer electronic circuits

We report the development of high-performance inkjet-printed organic field-effect transistors (OFETs) and complementary circuits using high-k polymer dielectric blends comprising poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) and poly(methyl methacrylate) (PMMA) for high-speed and low-voltage operation. Inkjet-printed p-type polymer semiconductors containing alkyl-substituted thienylenevinylene (TV) and dodecylthiophene (PC12TV12T) and n-type P(NDI2OD-T2) OFETs showed high field-effect mobilities of 0.1–0.4 cm² V^?1 s^?1 and low threshold voltages down to 5 V. These OFET properties were modified by changing the blend ratio of P(VDF-TrFE) and PMMA. The optimum blend – a 7:3 wt% mixture of P(VDF-TrFE) and PMMA – was successfully used to realize high-performance complementary inverters and ring oscillators (ROs). The complementary ROs operated at a supplied bias (V_DD) of 5 V and showed an oscillation frequency (f_osc) as high as ～80 kHz at V_DD = 30 V. Furthermore, the f_osc of the complementary ROs was significantly affected by a variety of fundamental parameters such as the electron and hole mobilities, channel width and length, capacitance of the gate dielectrics, V_DD, and the overlap capacitance in the circuit configuration.     

The effect of frequency and temperature on capacitance/conductance–voltage (C/G–V) characteristics of Au/n-GaAs Schottky barrier diodes (SBDs)

The capacitance–voltage (C–V) and conductance–voltage (G/ω–V) characteristics of the Au/n-GaAs Schottky barrier diodes (SBDs) have been investigated for 10, 100 and 500 kHz at 80 and 280 K. To evaluate the reason of non-ideal behavior in C–V and G/ω–V plots, the measured C and G/ω values were corrected by taking into accounts series resistance effect. Experimental results show that the values of C and G/ω were found to be a strong function of interface states (N_ss) at inverse and depletion regions especially at low frequencies, but R_s is effective only at the accumulation region especially at high frequencies. Such behavior of the C and G/ω values may be attributed to an increase in polarization especially at low frequencies and the existence of N_ss or dislocations between metal and semiconductor. It can be concluded that the increase in C and G/ω at low frequencies especially at weak and depletion regions results from the existence of N_ss. The values of doping concentration (N_d) and barrier height (BH) between metal and semiconductor were also obtained from the linear part of high frequency (500 kHz) C⁻² vs. V plots at 80 and 280 K, respectively.     

Evaluation of lateral barrier height of inhomogeneous photolithography-fabricated Au/n-GaAs Schottky barrier diodes from 80 K to 320 K

In order to evaluate current conduction mechanism in the Au/n-GaAs Schottky barrier diode (SBD) some electrical parameters such as the zero-bias barrier height (BH) Φ_bo(I–V) and ideality factor (n) were obtained from the forward bias current–voltage (I–V) characteristics in wide temperature range of 80–320 K by steps of 10 K. By using the thermionic emission (TE) theory, the Φ_bo(I–V) and n were found to depend strongly on temperature, and the n decreases with increasing temperature while the Φ_bo(I–V) increases. The values of Φ_bo and n ranged from 0.600 eV and 1.51(80 K) to 0.816 eV and 1.087 (320 K), respectively. Such behavior of Φ_bo and n is attributed to Schottky barrier inhomogeneities by assuming a Gaussian distribution (GD) of BHs at Au/n-GaAs interface. In the calculations, the electrical parameters of the experimental forward bias I–V characteristics of the Au/n-GaAs SBD with the homogeneity in the 80–320 K range have been explained by means of the TE, considering GD of BH with linear bias dependence.     

Transport and storage properties of CrSi2/Si junctions made using the CAPVD technique

p-CrSi₂/n-crystSi and p-CrSi₂/p-crystSi hetero junctions produced by cathodic arc physical vapor deposition were worked out by means of capacitance–voltage–temperature (C–V–T) and current–voltage–temperature (I–V–T) measurements to investigate storage and transport properties. Former measurement on p-CrSi₂/n-crystSi structure confirmed an abrupt type junction together with a building voltage at the proximity of 0.7 V. Though a fairly well rectification ratio (10³ at ±2 V) was realized by I–V measurement, it became deteriorated with the increase in ambient temperature. From temperature dependence of I–V variations, distinct conduction mechanisms were identified. In forward (reverse) direction trap assisted single-multistep tunneling recombination (generation) and space-charge limited current flow that corresponded to low and high bias voltage regions, respectively, were identified. Moreover, an activation energy (E_A) determined from the slopes of I–V–T curves as 0.22 and 0.26 eV was interpreted as the energy position of a chromium–boron (Cr–B) complex-type point defect residing in n/p doped c-Si semiconductor in CrSi₂/n–c-Si and CrSi₂/p–c-Si junctions. The retrieved E_A was in agreement with the recent DLTS measurement. Based on the experimental observations, schematic current path was built to interpret I–V/C–V behaviors. The model was successful in explaining the decrease in measured capacitance under large forward bias voltage reported for the first time by us for the present CrSi₂/Si junctions.     

Dielectric surface-polarity tuning and enhanced operation stability of solution-processed organic field-effect transistors

The electrical performance of triethylsilylethynyl anthradithiophene (TES-ADT) organic field-effect transistors (OFETs) was significantly affected by dielectric surface polarity controlled by grafting hexamethyldisilazane and dimethyl chlorosilane-terminated polystyrene (PS-Si(CH₃)₂Cl) to 300-nm-thick SiO₂ dielectrics. On the untreated and treated SiO₂ dielectrics, solvent–vapor annealed TES-ADT films contained millimeter-sized crystals with low grain boundaries (GBs). The operation and bias stability of OFETs containing similar crystalline structures of TES-ADT could be significantly increased with a decrease in dielectric surface polarity. Among dielectrics with similar capacitances (10.5–11 nF cm⁻²) and surface roughnesses (0.40–0.44 nm), the TES-ADT/PS-grafted dielectric interface contained the fewest trap sites and therefore the OFET produced using it had low-voltage operation and a charge-carrier mobility ∼1.32 cm² V⁻¹ s⁻¹, on–off current ratio >10⁶, threshold voltage ∼0 V, and long-term operation stability under negative bias stress.     

Carrier transport mechanisms and photovoltaic properties of Au/p-ZnPc/Al device

The dark current density–voltage characteristic of Au/ZnPc/Al device at room temperature has been investigated. Results showed a rectification behavior. At low forward bias, the current density was found to be ohmic, while at high voltages, space charge limited the current mechanism dominated by exponential trapping levels. Junction parameters such as rectification ratio (RR), series resistance (R_s), and shunt resistance (R_sh) were found to be 9.42, 9.72 MΩ, and 0.88 × 10³ MΩ, respectively. The current density–voltage characteristics under white light illumination (100 W/m²) gives values of 0.55 V, 3 × 10⁻³ A/m², 0.18 and 5.8 × 10⁻⁴% for the open circuit voltage, V_oc, the short circuit current density (J_sc), the fill factor (FF), and conversion efficiency (η), respectively.