Formation of high aspect ratio GaAs nanostructures with metal-assisted chemical etching

Periodic high aspect ratio GaAs nanopillars with widths in the range of 500-1000 nm are produced by metal-assisted chemical etching (MacEtch) using n-type (100) GaAs substrates and Au catalyst films patterned with soft lithography. Depending on the etchant concentration and etching temperature, GaAs nanowires with either vertical or undulating sidewalls are formed with an etch rate of 1-2 μm/min. The realization of high aspect ratio III-V nanostructure arrays by wet etching can potentially transform the fabrication of a variety of optoelectronic device structures including distributed Bragg reflector (DBR) and distributed feedback (DFB) semiconductor lasers, where the surface grating is currently fabricated by dry etching.     

Porosity control in metal-assisted chemical etching of degenerately doped silicon nanowires

We report the fabrication of degenerately doped silicon (Si) nanowires of different aspect ratios using a simple, low-cost and effective technique that involves metal-assisted chemical etching (MacEtch) combined with soft lithography or thermal dewetting metal patterning. We demonstrate sub-micron diameter Si nanowire arrays with aspect ratios as high as 180:1, and present the challenges in producing solid nanowires using MacEtch as the doping level increases in both p- and n-type Si. We report a systematic reduction in the porosity of these nanowires by adjusting the etching solution composition and temperature. We found that the porosity decreases from top to bottom along the axial direction and increases with etching time. With a MacEtch solution that has a high [HF]:[H(2)O(2)] ratio and low temperature, it is possible to form completely solid nanowires with aspect ratios of less than approximately 10:1. However, further etching to produce longer wires renders the top portion of the nanowires porous.     

Simultaneous Fabrication of Very High Aspect Ratio Positive Nano‐ to Milliscale Structures

A simple and inexpensive technique for the simultaneous fabrication of positive (i.e., protruding), very high aspect (>10) ratio nanostructures together with micro‐ or millistructures is developed. The method involves using residual patterns of thin‐film over‐etching (RPTO) to produce sub‐micro‐/nanoscale features. The residual thin‐film nanopattern is used as an etching mask for Si deep reactive ion etching. The etched Si structures are further reduced in size by Si thermal oxidation to produce amorphous SiO₂, which is subsequently etched away by HF. Two arrays of positive Si nanowalls are demonstrated with this combined RPTO‐SiO₂‐HF technique. One array has a feature size of 150 nm and an aspect ratio of 26.7 and another has a feature size of 50 nm and an aspect ratio of 15. No other parallel reduction technique can achieve such a very high aspect ratio for 50‐nm‐wide nanowalls. As a demonstration of the technique to simultaneously achieve nano‐ and milliscale features, a simple Si nanofluidic master mold with positive features with dimensions varying continuously from 1 mm to 200 nm and a highest aspect ratio of 6.75 is fabricated; the narrow 200‐nm section is 4.5 mm long. This Si master mold is then used as a mold for UV embossing. The embossed open channels are then closed by a cover with glue bonding. A high aspect ratio is necessary to produce unblocked closed channels after the cover bonding process of the nanofluidic chip. The combined method of RPTO, Si thermal oxidation, and HF etching can be used to make complex nanofluidic systems and nano‐/micro‐/millistructures for diverse applications.     

Sub-100 nm Si nanowire and nano-sheet array formation by MacEtch using a non-lithographic InAs nanowire mask

We report a non-lithographical method for the fabrication of ultra-thin silicon (Si) nanowire (NW) and nano-sheet arrays through metal-assisted-chemical-etching (MacEtch) with gold (Au). The mask used for metal patterning is a vertical InAs NW array grown on a Si substrate via catalyst-free, strain-induced, one-dimensional heteroepitaxy. Depending on the Au evaporation angle, the shape and size of the InAs NWs are transferred to Si by Au-MacEtch as is (NWs) or in its projection (nano-sheets). The Si NWs formed have diameters in the range of ～25-95 nm, and aspect ratios as high as 250 in only 5 min etch time. The formation process is entirely free of organic chemicals, ensuring pristine Au-Si interfaces, which is one of the most critical requirements for high yield and reproducible MacEtch.     

Plasma‐Induced Hetero‐Nanostructures on a Polymer with Selective Metal Co‐Deposition

Plasma‐induced pattern formation is explored on polyethylene terephthalate (PET) using an oxygen plasma glow discharge. The nanostructures on PET are formed through preferential etching directed by the co‐deposition of metallic elements, such as Cr or Fe, sputtered from a stainless‐steel cathode. The local islands formed by metal co‐deposition have significantly slower etching rates than those of the pristine regions on PET, generating anisotropic nanostructures in pillar‐ or hair‐like form during plasma etching. By covering the cathode with the appropriate material, the desired metallic or polymeric elements can be co‐deposited onto the target surfaces. When the cathode is covered by a relatively soft material composed of only carbon and hydrogen, such as polystyrene, nanostructures typically induced by preferential etching are not observed on the PET surface, and the surfaces are uniformly etched. A variety of metals, such as Ag, Cu, Pt, or Si, can be successfully co‐deposited onto the PET surfaces by simply using a cathode covered in the desired metal; high‐aspect‐ratio nanostructures coated with the co‐deposited metal are subsequently formed. Therefore this simple single‐step method for forming hetero‐nanostructures—that is, nanoscale hair‐like polymer structures decorated with metals—can be used to produce nanostructures for various applications, such as catalysts, sensors, or energy devices.     

Ru nanostructure fabrication using an anodic aluminum oxide nanotemplate and highly conformal Ru atomic layer deposition

We fabricated metallic nanostructures directly on Si substrates through a hybrid nanoprocess combining atomic layer deposition (ALD) and a self-assembled anodic aluminum oxide (AAO) nanotemplate. ALD Ru films with Ru(DMPD)(EtCp) as a precursor and O(2) as a reactant exhibited high purity and low resistivity with negligible nucleation delay and low roughness. These good growth characteristics resulted in the excellent conformality for nanometer-scale vias and trenches. Additionally, AAO nanotemplates were fabricated directly on Si and Ti/Si substrates through a multiple anodization process. AAO nanotemplates with various hole sizes (30-100?nm) and aspect ratios (2:1-20:1) were fabricated by controlling the anodizing process parameters. The barrier layers between AAO nanotemplates and Si substrates were completely removed by reactive ion etching (RIE) using BCl(3) plasma. By combining the ALD Ru and the AAO nanotemplate, Ru nanostructures with controllable sizes and shapes were prepared on Si and Ti/Si substrates. The Ru nanowire array devices as a platform for sensor devices exhibited befitting properties of good ohmic contact and high surface/volume ratio.     

Metal nanostructures fabricated by selective metal nanoscale etch method

A new method for fabricating metal nanostructures, called ‘the selective metal nanoscale etch method (SMNEM)’, was developed. The SMNEM consists of a galvanic displacement and selective etching process. The process was found to be simple and produced a uniform surface with a self-controlled etch rate of 32.2 ± 2.1 nm per cycle at a temperature and immersion time of 75°C and 3 min, respectively. Since it is a wet chemical process, SMNEM provides high throughput and low temperature etching which is compatible with conventional semiconductor processes. Various metal nanostructures, such as nanostairs, nanogratings, and nanowires were produced using SMNEM.     

Fabrication of p-type silicon nanowire arrays with a high aspect ratio using electrochemical and alkaline etching

We report on the fabrication of silicon nanostructures with a high aspect ratio that were created using a combination of electrochemical etching and alkaline etching. With this technique, we were able to fabricate nano- and/or micro-wire structures that are perfectly periodic over large areas of 3.14 cm2. After porous silicon was created by electrochemical etching, the effect of post-alkaline etching was investigated to determine how changes in the etching time, solution concentration and temperature of the etchant influenced the silicon morphology. As a result, periodic silicon wire arrays with good vertical alignment were obtained, and these arrays had a width of less than 500 nm and/or a high aspect ratio of more than 20.     

A simplified fabrication process of Fresnel zone plates with controlling proximity effect correction

Fresnel zone plates (FZPs) for soft X-ray microscopy with an energy range of 284 eV to 540 eV are designed and fabricated in a simple method. An adequate aspect ratio of the resist mold for electroplating was obtained by the proximity effect correction technology for an incident electron beam on a single thick layer resist. Without additional complicated reactive ion etching, a sufficient electro plating mold for nickel structures was fabricated. The overall fabrication procedures which involve a mix-and-match overlay technique for electron beam lithography and an optic exposure system that centers the membrane on the nanostructures, and hybrid silicon etching technology in junction with deep anisotropy and a KOH wet method in order to release the backside Si substrates of the Si3N4 membranes with no deformation of FZPs are introduced. High quality nanostructures with minimum outermost zone widths of 50 nm and diameters of 120 microm were fabricated with simplified fabrication process and with cost-effective.     

Fabrication and optical property of vertically-aligned ZnO/Si double nanostructures

We fabricated the vertically-aligned zinc oxide (ZnO)/silicon (Si) double nanostructures by simple processes using the metal-assisted chemical etching and a subsequent hydrothermal synthesis, and their optical property was investigated. For efficient antireflection characteristics, Si nanostructures were optimized by changing the size of the dewetted silver (Ag) at different etching times. The thermally dewetted Ag nanoparticles or semi-island films as metal catalysts were controlled by the Ag film thickness and dewetting temperature. To form the ZnO/Si double nanostructures, ZnO nanorods were synthesized on the chemically etched Si nanostructures using a thin sputtered ZnO seed layer. The grown ZnO nanorod arrays (NRAs) exhibited good crystallinity and further reduced the surface reflection due to their antireflective property. The ZnO/Si double nanostructures showed the increased peak intensity of X-ray diffraction as well as the significantly reduced solar weight reflectance of 6.05% compared to 11.71% in the ZnO NRAs on the flat Si substrate. Also, the enhanced antireflection property of ZnO/Si double nanostructures was theoretically analyzed by performing the rigorous coupled wave analysis simulation.     

Nanolithography using spin-coatable ZrO(2) resist and its application to sub-10 nm direct pattern transfer on compound semiconductors

A typical method for sub-micrometer compound semiconductor dry etching utilizes polymethylmethacrylate?(PMMA) to transfer patterns to SiO(2) as intermediate masks, which limits its ability to obtain etching resolutions approaching sub-10?nm. We report a new approach for direct sub-10?nm pattern transfer using sol-gel derived spin-coatable ZrO(2) resist as the mask. The optimal dose of ZrO(2) resist is ～160?mC?cm(-2). The sample InP compound semiconductor etching selectivity to ZrO(2) is over 13:1, with high aspect ratio of 35:1. The smallest etching feature is 9?nm. These results will be very useful for realizing various challenging nanoscale photonic and electronic devices and circuits.     

High‐Gain 200 ns Photodetectors from Self‐Aligned CdS–CdSe Core–Shell Nanowalls

1D core–shell heterojunction nanostructures have great potential for high‐performance, compact optoelectronic devices owing to their high interface area to volume ratio, yet their bottom‐up assembly toward scalable fabrication remains a challenge. Here the site‐controlled growth of aligned CdS–CdSe core–shell nanowalls is reported by a combination of surface‐guided vapor–liquid–solid horizontal growth and selective‐area vapor–solid epitaxial growth, and their integration into photodetectors at wafer‐scale without postgrowth transfer, alignment, or selective shell‐etching steps. The photocurrent response of these nanowalls is reduced to 200 ns with a gain of up to 3.8 × 10³ and a photoresponsivity of 1.2 × 10³ A W^?1, the fastest response at such a high gain ever reported for photodetectors based on compound semiconductor nanostructures. The simultaneous achievement of sub‐microsecond response and high‐gain photocurrent is attributed to the virtues of both the epitaxial CdS–CdSe heterojunction and the enhanced charge‐separation efficiency of the core–shell nanowall geometry. Surface‐guided nanostructures are promising templates for wafer‐scale fabrication of self‐aligned core–shell nanostructures toward scalable fabrication of high‐performance compact photodetectors from the bottom‐up.     

Fabrication and characterization of plasmonic nanorods with high aspect ratios

Metallic nanostructures with high aspect ratios are important for developing devices in photonics and integrated optics. However, fabricating well-aligned plasmonic arrays is challenging due to the difficulties of etching metals. In this work, we investigate the feasibility of constructing high aspect ratio nanorods with desired shapes and controllable geometric parameters using direct focused ion beam etching. The whole fabrication process only involves a metal-deposition step and a single milling of designed patterns. Detailed characterizations of the fabricated devices are also experimentally demonstrated.     

Ordered arrays of <100>-oriented silicon nanorods by CMOS-compatible block copolymer lithography

Dense, ordered arrays of <100>-oriented Si nanorods with uniform aspect ratios up to 5:1 and a uniform diameter of 15 nm were fabricated by block copolymer lithography based on the inverse of the traditional cylindrical hole strategy and reactive ion etching. The reported approach combines control over diameter, orientation, and position of the nanorods and compatibility with complementary metal oxide semiconductor (CMOS) technology because no nonvolatile metals generating deep levels in silicon, such as gold or iron, are involved. The Si nanorod arrays exhibit the same degree of order as the block copolymer templates.     

High ion density dry etching of compound semiconductors

The use of plasma sources that generate high ion densities (> 10¹¹ cm⁻³) enables dry etching of compound semiconductors at high rates with anisotropic sidewalls. In this paper we review the use of several types of electron cyclotron resonance (ECR) plasma sources and contrast the result with those obtained under reactive ion etching conditions. Various problems occurring in dry etching will be discussed, including aspect ratio dependent etch rates, mask erosion, sidewall roughening and damage introduction into the semiconductor. This damage may consist of point and line defect creation, non-stoichiometric surfaces, resputtering of mask materials or deposition of contaminating films. The use of low or high substrate temperatures to control the desorption kinetics of etch products is also discussed; at low temperatures problems can occur with condensation of the etch gases onto the substrate, while at elevated temperatures it is necessary to thermally bond the sample to the r.f. powered electrode to obtain reproducibility. Etch selectivity between the components of heterostructure systems such as GaAs/AlGaAs, GaAs/InGaP, InGaAs/AlInAs and GaN/AlN is usually much worse under high ion density conditions because of the high rates and large physical component.     

Robust Free‐Standing Nano‐Thin SiC Membranes Enable Direct Photolithography for MEMS Sensing Applications

This work presents fabrication of micro structures on sub–100 nm SiC membranes with a large aspect ratio up to 1:3200. Unlike conventional processes, this approach starts with Si wet etching to form suspended SiC membranes, followed by micro‐machined processes to pattern free‐standing microstructures such as cantilevers and micro bridges. This technique eliminates the sticking or the under‐etching effects on free‐standing structures, enhancing mechanical performance which is favorable for MEMS applications. In addition, post‐Si‐etching photography also enables the formation of metal electrodes on free standing SiC membranes to develop electrically‐measurable devices. To proof this concept, the authors demonstrate a SiC pressure sensor by applying lithography and plasma etching on released ultrathin SiC films. The sensors exhibit excellent linear response to the applied pressure, as well as good repeatability. The proposed method opens a pathway for the development of self‐sensing free‐standing SiC sensors.     

Scanning Nanowelding Lithography for Rewritable One‐Step Patterning of Sub‐50 nm High‐Aspect‐Ratio Metal Nanostructures

The development of a new nanolithographic strategy, named scanning nanowelding lithography (SNWL), for the one‐step fabrication of arbitrary high‐aspect‐ratio nanostructures of metal is reported in this study. Different from conventional pattern transfer and additive printing strategies which require subtraction or addition of materials, SNWL makes use of a sharp scanning tip to reshape metal thin films or existing nanostructures into desirable high‐aspect‐ratio patterns, through a cold‐welding effect of metal at the nanoscale. As a consequence, SNWL can easily fabricate, in one step and at ambient conditions, sub‐50 nm metal nanowalls with remarkable aspect ratio >5, which are found to be strong waveguide of light. More importantly, SNWL outweighs the existing strategies in terms of the unique ability to erase the as‐made nanostructures and rewrite them into other shapes and orientations on‐demand. Taking advantages of the serial and rewriting capabilities of SNWL, the smart information storage–erasure of Morse codes is demonstrated. SNWL is a promising method to construct arbitrary high‐aspect‐ratio nanostructure arrays that are highly desirable for biological, medical, optical, electronic, and information applications.     

Sub‐Micron Anisotropic InP‐based III–V Semiconductor Material Deep Etching for On‐Chip Laser Photonics Devices

Two InP‐based III–V semiconductor etching recipes are presented for fabrication of on‐chip laser photonic devices. Using inductively coupled plasma system with a methane free gas chemistry of chlorine and nitrogen at a high substrate temperature of 250 °C, high aspect ratio, anisotropic InP‐based nano‐structures are etched. Scanning electron microscopy images show vertical sidewall profile of 90° ± 3°, with aspect ratio as high as 10. Atomic Force microscopy measures a smooth sidewall roughness root‐mean‐square of 2.60 nm over a 3 × 3 μm scan area. The smallest feature size etched in this work is a nano‐ring with inner diameter of 240 nm. The etching recipe and critical factors such as chamber pressure and the carrier plate effect are discussed. The second recipe is of low temperature (?10 °C) using Cl₂ and BCl₃ chemistry. This recipe is useful for etching large areas of III–V to reveal the underlying substrate. The availability of these two recipes has created a flexible III–V etching platform for fabrication of on‐chip laser photonic devices. As an application example, anisotropic InP‐based waveguides of 3 μm width are fabricated using the Cl₂ and N₂ etch recipe and waveguide loss of 4.5 dB mm^?1 is obtained.

     

A systematic study of DRIE process for high aspect ratio microstructuring

Various MEMS devices like Accelerometers, Resonators, RF- Filters, Micropumps, Microvalves, Microdispensers and Microthrusters are produced by removing the bulk of the substrate materials. Fabrications of such Microsystems requires the ability to engineer precise three-dimensional structures in the silicon substrate. Fabrication of MEMS faces multiple technological challenges before it can become a commercially viable technology. One key fabrication process required is the deep silicon etching for forming high aspect ratio structures. There is an increasing interest in the use of dry plasma etching for this application because of its anisotropic etching behavior, high etch speed, good uniformity and profile control, high aspect ratio capabilities without having any undesired secondary effects i.e. RIE lags, Loading, microloading, loosing of anisotropic nature of etching as aspect ratio increases, micro-grass and even etch stalling. Developing a DRIE micro-machining process requires a thorough understanding of all plasma parameters, which can affect a silicon etching process and their use to suppress the secondary effects. In this paper our intention is to investigate the influence of etching gas flow, etching gas pressure, passivation gas pressure, ICP coil power, Platen power and etch and passivation time sequence on etch rate and side wall profile. Parameter ramping is a powerful technique used to achieve the requirements of high aspect ratio microstructures (HARMS) for MEMS applications by having high etch rate with good profile/CD control. The results presented here can be used to rationally vary processing parameters in order to meet the microstructural requirements for a particular application.     

Site-controlled fabrication of dimension-tunable Si nanowire arrays on patterned (001)Si substrates

In this study, we fabricated well-ordered arrays of site-controlled, vertically-aligned Si nanowires on the desired areas of pre-patterned (001)Si substrates by employing the nanosphere lithographic technique in combination with the Au-assisted selective etching process. The results of transmission electron microscopy and selected-area electron diffraction analysis show that the Si nanowires that fabricated on the patterned (001)Si substrates have a single-crystalline nature and form along the [001] direction. The length of the Si nanowires was found to increase linearly with the Au-assisted etching time. Scanning electron microscopy images clearly revealed that by adjusting the sizes of the nanosphere template and the etching temperature and time, the diameter and length of the patterned Si nanowires could be effectively tuned and accurately controlled. Furthermore, the diameters of the Si nanowires produced at various temperatures and time were found to be relatively uniform over the entire length. The combined approach presented here provides the capability to fabricate a variety of size-, length-tunable 1D Si-based nanostructures on various patterned Si-based substrates.