Impact of Sampling Clock Phase Noise on Σ∆ Frequency Discriminators

SigmaDelta frequency discriminators (SigmaDeltaFDs) convert instantaneous frequency deviations of a carrier signal to digital. They are used for decoding narrowband phase or frequency modulated signals in communication receivers, self calibration of RF frequency synthesizers and in digital phase locked loops. In this paper, the impact of reference (sampling) clock phase noise on a SigmaDeltaFD's spurious-free dynamic range (SFDR) is derived. It is shown that for SigmaDeltaFDs with jittered sampling clock, in addition to FM sidebands, a high baseband tonal content is generated degrading overall SFDR. The reference clock phase noise impact is derived mathematically, and two commonly used SigmaDeltaFDs circuits are designed and implemented to verify the results experimentally. Experimental results are shown to match the theoretical prediction of SFDR within 3 dB.     

Mismatch Insensitive Double-Sampling Quadrature Bandpass Σ∆ Modulation

In a double-sampling quadrature bandpass sigma-delta modulator, path mismatch between the double-sampling branches and between the I/Q paths occurs. In this paper, an analytical study is presented which shows that this causes quantization noise and input signals to fold from the image band into the signal band and that this also results in a self-image component. To reduce the folding from the image band, a novel resonator is presented. This resonator has a bilinear input circuit so that noise and signals exhibits first-order shaping before folding in the band of interest. Next, three different modulator architectures based on the novel resonator are introduced. Finally, the remaining problem of self-image is tackled with a simple, yet efficient offline calibration strategy. Various design examples are shown and simulated to illustrate and prove the effectiveness of the proposed architectures and methods.     

Behavioral Modeling Methods for Switched-Capacitor Σ∆ Modulators

Sigma-delta Modulators (SigmaDeltaMs) are cornerstone elements in oversampled analog-to-digital converters and digital-to-analog converters (DAC). Although transistor-level simulation is the most accurate approach known for these components, this method becomes impractical for complex systems due to its long computational time requirements. Behavioral modeling has become a viable solution to this problem. In this paper, we study styles and issues in the accurate modeling of low-power, high-speed SigmaDeltaMs and introduce two new behavioral models for switched-capacitor (SC) integrators. The first model is based on the SC integrator transient response, including the effects of the amplifier transconductance, output conductance, and the dynamic capacitive loading effect on the settling time. The second model is based on a symbolic node admittance matrix representation of the system. Nonidealities such as jitter, thermal noise, and DAC mismatch are also addressed and included in a dual-band, GSM/WCDMA, second-order, multibit SigmaDeltaM model with individual level averaging. VHDL-AMS and MATLAB Simulink were used as modeling languages. Both models are validated against experimental data, showing competitive results in the signal-to-noise-plus-distortion ratio. A comparative analysis between the proposed and a traditional model is presented, with emphasis on the degrading effects due to the integrator dynamics. Moreover, a general simulation speed analysis of the proposed models is addressed.     

Efficient Multibit Quantization in Continuous-Time Σ∆ Modulators

A drawback of continuous-time SigmaDelta modulators is their sensitivity to clock jitter. One way to counteract this is to use a multibit feedback loop which requires a (high resolution) multibit quantizer. However, every extra bit in the quantizer doubles its complexity, power consumption and capacitive load for the analog circuit that needs to drive the quantizer. In this paper a new concept for the quantization in sigma delta modulators is proposed. It allows to significantly reduce the required amount of comparators in the multibit quantizer. Three architectures that realize this new concept are presented and their implementation issues discussed. The architectures' performance has been compared with a conventional modulator through computer simulations. Compared to the conventional modulator, the proposed architectures achieve the same performance, with much less comparators in the quantizer     

A Design-for-Digital-Testability Circuit Structure for Σ- ∆ Modulators

A design-for-digital-testability (DfDT) switched-capacitor circuit structure for testing Sigma-Delta modulators with digital stimuli is presented to reduce the overall testing cost. In the test mode, the DfDT circuits are reconfigured as a one-bit digital-to-charge converter to accept a repetitively applied Sigma-Delta modulated bit-stream as its stimulus. The single-bit characteristic ensures that the generated stimulus is nonlinearity free. In addition, the proposed DfDT structure reuses most of the analog components in the test mode and keeps the same loads for the operational amplifiers as if they were in the normal mode. It thereby achieves many advantages including lower cost, higher fault coverage, higher measurement accuracy, and the capability of performing at-speed tests. A second-order Sigma-Delta modulator was designed and fabricated to demonstrate the effectiveness of the DfDT structure. Our experimental results show that the digital test is able to measure a harmonic distortion lower than -106 dBFS. Meanwhile, the dynamic range measured with the digital stimulus is as high as 84.4 dB at an over-sampling ratio of 128. The proposed DfDT scheme can be easily applied to other types of Sigma-Delta modulators, making them also digitally testable.     

∆Σ PLL Transmitter With a Loop-Bandwidth Calibration System

We developed a DeltaSigma PLL transmitter with a linear charge pump and a new loop-bandwidth calibration system that can calibrate loop bandwidth accurately in a very short time. The calibration system uses a double integration technique that integrates the transient signal at the voltage-controlled oscillator output during the response to a step wave input to the divider. In our DeltaSigma PLL transmitter for GSM phones, the calibration system keeps the loop bandwidth within 2% and the calibration time is about 25 mus. To improve the GSM spectrum, we developed a charge pump that reduces a spike noise and the asymmetry of the charge and discharge characteristics. The phase error of modulation in the DeltaSigma PLL transmitter with the charge pump and calibration system was kept within 2 degrees rms, and after calibration the 400-kHz offset noise level of the spectrum mask was -64 dBc.     

A Power Optimized Continuous-Time ∆Σ ADC for Audio Applications

We present design considerations for low-power continuous-time modulators. Circuit design details and measurement results for a 15 bit audio modulator are given. The converter, designed in a 0.18 mum CMOS technology, achieves a dynamic range of 93.5 dB in a 24 kHz bandwidth and dissipates 90 muW from a 1.8 V supply. It features a third-order active-RC loop filter, a very low-power 4-bit flash quantizer, and an efficient excess-delay compensation scheme to reduce power dissipation.     

Efficient Look-Up-Table-Based Modeling for Robust Design of Σ∆ ADCs

The sigma-delta (SigmaDelta) analog-digital converter (ADC) has been widely used in data conversion applications due to its good performance. However, oversampling and complex circuit behaviors render the transistor-level analysis of these designs prohibitively time consuming. The inefficiency of the standard simulation approach also rules out the possibility of analyzing the impacts of a multitude of environmental and process variations critical in modern VLSI technologies. We present a look-up table (LUT)-based modeling technique to facilitate much more efficient performance analysis of SigmaDelta ADCs. Various transistor-level circuit nonidealities are systematically characterized at the building block level and the whole system is simulated much more efficiently using these building block models. Our approach can provide up to four orders of magnitude runtime speedup over SPICE-like simulators, hence significantly shortening the CPU time required for evaluating system performances such as signal-to-noise-and-distortion ratio. The proposed modeling technique is further extended to enable scalable performance variation analysis of complex SigmaDelta ADC designs. Such modeling approach allows us to perform trade-off analysis of various topologies considering not only nominal performances but also their variabilities. Equally important, with our efficient parametric modeling technique, we are able to feasibly extract simulation-based statistical performance correlation models allowing low-cost alternate linearity test of ADC designs.     

A Novel ∆Σ Control System Processor and Its VLSI Implementation

This paper describes a novel control system processor architecture based on DeltaSigma modulation known as the DeltaSigma -CSP. The DeltaSigma -CSP utilizes 1-bit processing which is a new concept in digital control applications with the direct benefit of making multi-bit multiplication operations redundant. A simple conditional-negate-and-add (CNA) unit is instead used for operations in control law implementations. For this reason, the proposed processor has a very small silicon footprint and runs at very high frequencies making it ideal for high-sampling rate, real-time control applications. A number of DeltaSigma -CSP configurations have been implemented as VLSI hard macros in a high-performance 0.13-mum CMOS process and a particular configuration achieved a post-route operating frequency of 355 MHz resulting in a 2.17 MHz sampling rate for a fourth-order control law implementation. Additional results prove that the DeltaSigma -CSP compares very favorably, in terms of silicon area and sampling rates, to two other specialized digital control processing systems, including direct, hardwired implementation of control laws; at the same time, it substantially outperforms software implementations of control laws running on very wide, general-purpose VLIW architectures.     

直接数字频率合成器的优化技术研究

详细阐述了利用QuartusⅡ实现直接数字频率合成器（DDS）的方法和步骤。分析了DDS的设计原理,采用多级流水线控制技术对DDS相位累加器进行了优化,利用存储对称波形方法对波形存储表进行了优化,并在开发环境下进行了功能仿真,选用现场可编程器件FPGA作为目标器件,得到了可以重构的IP核,实现了复杂的调频功能。利用该方法实现的DDS模块具有更广泛的实际意义和更良好的实用性。     

基于Delta-Sigma技术的直接数字频率发生器的设计

直接数字频率合成技术(DDFS)具有很好的频率渐变与很高的频率分辨率,然而该技术却伴随着严重的谐波噪声,主要的谐波噪声是相位截断噪声。该文将介绍一种新型的DDFS结构,该结构采用了Delta-Sigma噪声整形技术,有效地减少由相位截断引入的噪声。经测试,信号的信噪比可以大于60dB,同时减小了硬件的复杂性。     

直接数字频率合成的DSP实现

介绍了一种实现直接数字频率合成的数字信号处理方法，其基本思想基于脉冲响应为正弦波的二阶ⅡＲ谐振器，采用这种方法可以产生出比常规的基于正弦查表的ＤＤＦＳ实现方法多的频率种为 频率谱纯度高，硬件设计，小型，可靠等优点。     

直接数字频率合成器(DDS)应用的频率规划

DDS基本知识与频率规划的意义 DDS被定义为是一种由固定频率参考时钟源产生正弦波的数字技术。需要注意的是,参考时钟源的动态性能会直接影响到DDS的输出频谱。DDS有如下优点：     

直接数字频率合成器的PFGA实现

系统采用Xilinx公司生产的型号为XC3S200的FPGA芯片和Maxim公司、生产的型号为MAX5885的专用D／A芯片,利用直接数字频率合成技术,通过Xilinx公司的ISE9．2开发软件,完成DDS核心部分即相位累加器和ROM查找表的设计。可得到相位连续、频率可变的信号。经过电路设计和模块仿真,验证了设计的正确性。由于FPGA的可编程性,使得修改和优化DDS的功能非常快捷。     

A Low-Noise 40-GS/s Continuous-Time Bandpass ∆Σ ADC Centered at 2 GHz for Direct Sampling Receivers

This paper presents a 40-GS/s continuous-time bandpass DeltaSigma analog-to-digital converter centered at 2 GHz for wireless base station applications. The ADC consists of a fourth-order loop with multiple feedback and is designed entirely in the s-domain. The circuit achieves an SNDR of 55 dB and 52 dB over bandwidths of 60 MHz and 120 MHz, respectively, and an SFDR of 61dB with a single-ended IIP3 of +4 dBm. The center frequency is tunable from 1.8 to 2 GHz. It employs a G_m-LC_VAR filter based on a MOS-HBT cascode transconductor with an NFMIN of 2.29 dB. The entire circuit is implemented in a 130-nm SiGe BiCMOS technology with 150-GHz f_T SiGe HBT and dissipates 1.6 W from a 2.5-V supply     

An IF-to-Baseband Σ∆ Modulator for AM/FM/IBOC Radio Receivers With a 118 dB Dynamic Range

A single-bit fifth-order complex continuous-time IF-to-baseband SigmaDelta modulator for AM/FM/IBOC receivers is presented. The input IF is 10.7 MHz and the sampling frequency is 41.7 MHz. The modulator achieves a dynamic range of 118dB in AM mode (3 kHz BW), 98dB in FM mode (200 kHz BW), and 86dB in IBOC mode (500 kHz BW). The modulator's high dynamic range enables the realization of an AM radio receiver without a VGA and without an AM channel-selection filter, thereby reducing system complexity and cost. The elimination of the VGA also improves the sensitivity and the overall noise figure of the receiver. The modulator's spurious free dynamic range is 88 dB in the bandwidth from 25 to 525 kHz. The IM2 distance is 92 dB, and the IM3 distance is 91 dB. The ADC was fabricated in a one-poly five-metal 0.18-mum CMOS process with an active area of 6.0mm². It consumes 210 mW from a 1.8-V supply     

FPGA实现的直接数字频率合成器

描述了直接数字频率合成器（DDS）的原理和特点，并给出了用FPGA实现DDS的方法及仿真结果。     

一种多通道直接数字频率合成器的设计

基于直接数字频率合成(DDS)的原理,设计实现了四通道的直接数字频率合成器。其内部集成四路DAC,最高工作频率达到500 MHz。分析实现相位幅度转换的CORDIC算法原理并进行算法改进,降低了整体电路的功耗。     

直接数字式频率合成器的原理与设计

本文介绍了直接数字式频率合成器(DDFS)的一般原理,提出了一个改进方案,并用改进方案设计了一个频率范围为0.01Hz～30kHz,频率间隔为0.01Hz,具有晶体振荡器频率标准稳定度的正弦/余弦信号发生器。     

一种高速直接数字频率合成器及其FPGA实现

介绍了一种用于QAM调制和解调的直接数字频率合成器,该电路同时输出10位正弦和余弦两种波形,系统时钟频率为50MHz,信号的谐波小于－72dB。输出信号的范围为DC到25MHz,信号频率步长为0．0116Hz,相应的转换速度为20ns,建立时间延迟为4个时种。直接数字合成器（DDFS）采用一种有效查找表的方式生成正弦函数,为了降低ROM的大小,采用了1／8正弦波形函数压缩算法。直接数字频率合成器的数字部分由Xilinx FPGA实现,最后通过数模转换器输出。