A 4.39–5.26 GHz LC-Tank CMOS Voltage-Controlled Oscillator With Small VCO-Gain Variation

A wide band CMOS LC-tank voltage controlled oscillator (VCO) with small VCO gain $(K_{VCO})$ variation was developed. For small $K_{VCO}$ variation, serial capacitor bank was added to the LC-tank with parallel capacitor array. Implemented in a 0.18 $mu{rm m}$ CMOS RF technology, the proposed VCO can be tuned from 4.39 GHz to 5.26 GHz with the VCO gain variation less than 9.56%. While consuming 3.5 mA from a 1.8 V supply, the VCO has $-$ 113.65 dBc/Hz phase noise at 1 MHz offset from the carrier.      

A 1.94 to 2.55 GHz, 3.6 to 4.77 GHz Tunable CMOS VCO Based on Double-Tuned, Double-Driven Coupled Resonators

This paper presents a multi-band CMOS VCO using a double-tuned, current-driven transformer load. The dual frequency range oscillator is based on enabling/disabling the driving current in the secondary port of the transformer. This approach eliminates the effect of switches connected directly to the VCO tank whose capacitance and on-resistance affect both the tuning range and the phase noise of a typical multi-band oscillator. The relation between the coupling coefficient of the transformer load, selection of frequency bands, and the resulting quality factor at each band is investigated. The concept is validated through measurement results from a prototype fabricated in 0.25 $~muhbox{m}$ CMOS technology. The VCO has a measured tuning range of 1.94 to 2.55 GHz for the low frequency range and 3.6 to 4.77 GHz for the high frequency range. It draws a current of 1 mA from 1.8 V supply with a measured phase noise of $-hbox{116~dBc/Hz}$ at 1 MHz offset from a 2.55$~$GHz carrier. For the high frequency band, the VCO draws 10.1 mA from the same supply with a phase noise of $-hbox{122.8~dBc/Hz}$ at 1$~$ MHz offset from a 4.77 GHz carrier.      

A 0.13 $mu$ m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

This paper presents a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS/EDGE applications which adopts a direct-conversion receiver, a direct-conversion transmitter and a fractional-N frequency synthesizer with a built-in DCXO. In the GSM mode, the transmitter delivers 4 dBm of output power with 1$^{circ}$ RMS phase error and the measured phase noise is ${-}$164.5 dBc/Hz at 20 MHz offset from a 914.8$~$MHz carrier. In the EDGE mode, the TX RMS EVM is 2.4% with a 0.5 $~$dB gain step for the overall 36 dB dynamic range. The RX NF and IIP3 are 2.7 dB/ ${-}$12 dBm for the low bands (850/900 MHz) and 3 dB/${-}$ 11 dBm for the high bands (1800/1900 MHz). This transceiver is implemented in 0.13 $mu$m CMOS technology and occupies 10.5 mm$^{2}$ . The device consumes 118 mA and 84 mA in TX and RX modes from 2.8 V, respectively and is housed in a 5$,times,$ 5 mm$^{2}$ 40-pin QFN package.      

A 98/196 GHz Low Phase Noise Voltage Controlled Oscillator With a Mode Selector Using a 90 nm CMOS Process

A 98/196 GHz low phase noise voltage controlled oscillator (VCO) with a fundamental/push-push mode selector using a 90 nm CMOS process is presented in this letter. An innovative concept of the VCO with the mode selector is proposed to switch the fundamental or second harmonic to the RF output. The VCO demonstrates a fundamental frequency of up to 98 GHz with an output power of greater than $-8~{rm dBm}$. The phase noise of the VCO is better than $-100.8~{rm dBc}/{rm Hz}$ at 1 MHz offset frequency, and its figure-of-merit is better than $-186~{rm dBc}/{rm Hz}$. Moreover, the output frequency of the work is up to 196 GHz with a fundamental suppression of greater than $-30~{rm dBc}$ as the VCO is operated in push-push mode.      

2 MHz AO $Q$ -switched ${rm TEM}_{00}$ Grazing Incidence Laser With 3 at.% Neodymium Doped Nd:YVO$_{4}$

We present a detailed experimental and theoretical study of the ultrahigh repetition rate AO $Q$ -switched ${rm TEM}_{00}$ grazing incidence laser. Up to 2.1 MHz $Q$-switching with ${rm TEM}_{00}$ output of 8.6 W and 2.2 MHz $Q$ -switching with multimode output of 10 W were achieved by using an acousto-optics $Q$ -switched grazing-incidence laser with optimum grazing-incidence angle and cavity configuration. The crystal was 3 at.% neodymium doped Nd:YVO$_{4}$ slab. The pulse duration at 2 MHz repetition rate was about 31 ns. The instabilities of pulse energy at 2 MHz repetition rate were less than ${pm}6.7hbox{%}$ with ${rm TEM}_{00}$ operation and ${pm}3.3hbox{%}$ with multimode operation respectively. The modeling of high repetition rate $Q$-switched operation is presented based on the rate equation, and with the solution of the modeling, higher pump power, smaller section area of laser mode, and larger stimulated emission cross section of the gain medium are beneficial to the $Q$-switched operation with ultrahigh repetition rate, which is in consistent with the experimental results.      

A Low Phase-Noise QVCO With Integrated Back-Gate Coupling and Source Resistive Degeneration Technique

A 0.18 $mu$ m CMOS quadrature voltage-controlled oscillator with an extremely-low phase noise is presented. The excellent phase noise performance is accomplished by integration of the back-gate quadrature phase coupling and source resistive degeneration techniques into a complementary oscillator topology. The measured phase noise is as low as ${-}133$ dBc/Hz at 1 MHz offset from 3.01 GHz. The output phase imbalance is less than 1$^{circ}$ . The output power is $-1.25{pm} 0.5$ dBm and harmonic suppression is greater than 30.8 dBc. The oscillator core consumes 5.38 mA from a 1.5 V power supply. This QVCO achieves the highest figure-of-merit of ${-}193.5$ dBc/Hz.      

A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios

The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for application in wireless sensor networks (WSN). After a single-point calibration, the spread of its output frequency is less than 1.1% (3$sigma $) over the temperature range from $-{hbox{22}},^{circ}{hbox{C}}$ to 85$,^{circ}{hbox{C}}$ . Fabricated in a baseline 65$~$nm CMOS technology, the frequency reference circuit occupies 0.11$ hbox{mm}^{2}$ and draws 34 $ muhbox{A}$ from a 1.2 V supply at room temperature.      

Characterization and Modeling of RF-Performance $(f_{T})$ Fluctuation in MOSFETs

The fluctuation of RF performance (particularly for $f_{T}$ : cutoff frequency) in the transistors fabricated by 90-nm CMOS technology has been investigated. The modeling for $f_{T}$ fluctuation is well fitted with the measurement data within approximately 1% error. Low-$V_{t}$ transistors (fabricated by lower doping concentration in the channel) show higher $f_{T}$ fluctuation than normal transistors. Such a higher $f_{T}$ fluctuation results from $C_{rm gg}$ (total gate capacitance) variation rather than $g_{m}$ variation. More detailed analysis shows that $C_{rm gs} + C_{rm gb}$ (charges in the channel and the bulk) are predominant factors over $C_{rm gd}$ (charges in LDD/halo region) to determine $C_{rm gg}$ fluctuation.      

Effective Modulation of Quadratic Voltage Coefficient of Capacitance in MIM Capacitors Using $hbox{Sm}_{2}hbox{O}_{3}/hbox{SiO}_{2}$ Dielectric Stack

We report the first demonstration of metal–insulator–metal (MIM) capacitors with $hbox{Sm}_{2}hbox{O}_{3}/hbox{SiO}_{2}$ stacked dielectrics for precision analog circuit applications. By using the “canceling effect” of the positive quadratic voltage coefficient of capacitance (VCC) of $hbox{Sm}_{2}hbox{O}_{3}$ and the negative quadratic VCC of $hbox{SiO}_{2}$, MIM capacitors with capacitance density exceeding 7.3 $hbox{fF}/muhbox{m}^{2}$ , quadratic VCC of around $-hbox{50} hbox{ppm/V}^{2}$ , and leakage current density of $hbox{1} times hbox{10}^{-7} hbox{A/cm}^{2}$ at $+$3.3 V are successfully demonstrated. The obtained capacitance density and quadratic VCC satisfy the technical requirements specified in the International Technology Roadmap for Semiconductors through the year 2013 for MIM capacitors to be used in precision analog circuit applications.      

A 0.55 V 60 dB-DR Fourth-Order Analog Baseband Filter

A 0.55 V supply voltage fourth-order low-pass continuous-time filter is presented. The low-voltage operating point is achieved by an improved bias circuit that uses different opamp input and output common-mode voltages. The fourth-order filter architecture is composed by two Active- ${rm G}_{rm m}{-}{rm RC}$ biquadratic cells, which use a single opamp per-cell with a unity-gain-bandwidth comparable to the filter cut-off frequency. The $-$ 3 dB filter frequency is 12 MHz and this is higher than any other low-voltage continuous-time filter cut-off frequency. The $-$3 dB frequency can be adjusted by means of a digitally-controlled capacitance array. In a standard 0.13 $mu{rm m}$ CMOS technology with ${V}_{THN}approx 0.25 {rm V}$ and ${V}_{THP}approx 0.3 {rm V}$, the filter operates with a supply voltage as low as 0.55 V. The filter $({rm total} {rm area}=0.47 {rm mm}^{2})$ consumes 3.4 mW. A 8 dBm-in-band IIP3 and a 13.3 dBm-out-of-band IIP3 demonstrate the validity of the proposal.      

A 47 GHz Cross-Coupled VCO Employing High- Island-Gate Varactor for Phase Noise Reduction

A 47 GHz $LC$ cross-coupled voltage controlled oscillator (VCO) employing the high-$Q$ island-gate varactor (IGV) based on a 0.13 $mu{rm m}$ RFCMOS technology is reported in this work. To verify the improvement in the phase noise, two otherwise identical VCOs, each with an IGV and a conventional multi-finger varactor, were fabricated and the phase noise performance was compared. With $V_{DD}$ of 1.2 V and core power consumption of 3.86 mW, the VCOs with the IGV and the multi-finger varactor have a phase noise of $-$95.4 dBc/Hz and $-$91.4 dBc/Hz respectively, at 1 MHz offset, verifying the phase noise reduction with the introduction of the high-$Q$ IGV. The VCO with IGV exhibited an output power of around $-$15 dBm, leading to a FoM of $-$182.9 dBc/Hz and a tuning range of 3.35% (45.69 to 47.22 GHz).      

A Linearization Technique for RF Receiver Front-End Using Second-Order-Intermodulation Injection

A linearization technique is proposed in which low-frequency second-order-intermodulation $({rm IM}_{2})$ is generated and injected to suppress the third-order intermodulation $({rm IM}_{3})$. The proposed linearization technique is applied to both a low-noise amplifier (LNA) and a down-conversion mixer in an RF receiver front-end (RFE) working at 900 MHz. Fabricated in a 0.18$ mu{hbox{m}}$ CMOS process and operated at 1.5 V supply with a total current of 13.1 mA, the RFE delivers 22 dB gain with 5.3 dB noise figure (NF). The linearization technique achieves around 20 dB ${rm IM}_{3}$ suppression and improves the RFE's ${rm IIP}_{3}$ from $-$ 10.4 dBm to 0.2 dBm without gain reduction and noise penalty while requiring only an extra current of 0.1 mA.      

$hbox{TiN/ZrO}_{2}$/Ti/Al Metal–Insulator–Metal Capacitors With Subnanometer CET Using ALD-Deposited $hbox{ZrO}_{2}$ for DRAM Applications

We provide the first report of the structural and electrical properties of $hbox{TiN/ZrO}_{2}$/Ti/Al metal–insulator–metal capacitor structures, where the $hbox{ZrO}_{2}$ thin film (7–8 nm) is deposited by ALD using the new zirconium precursor ZrD-04, also known as Bis(methylcyclopentadienyl) methoxymethyl. Measured capacitance–voltage ($C$– $V$) and current–voltage ( $I$–$V$) characteristics are reported for premetallization rapid thermal annealing (RTP) in $hbox{N}_{2}$ for 60 s at 400 $^{circ}hbox{C}$, 500 $^{circ}hbox{C}$, or 600 $^{ circ}hbox{C}$. For the RTP at 400 $^{circ}hbox{C}$ , we find very low leakage current densities on the order of nanoamperes per square centimeter at a gate voltage of 1 V and low capacitance equivalent thickness values of $sim$ 0.9 nm at a gate voltage of 0 V. The dielectric constant of $ hbox{ZrO}_{2}$ is 31 $pm$ 2 after RTP treatment at 400 $^{circ}hbox{C}$.      

A 5-GHz CMOS Type-II PLL With Low $K_{rm VCO}$ and Extended Fine-Tuning Range

A 5-GHz dual-path integer-$N$ Type-II phase-locked loop (PLL) uses an LC voltage-controlled oscillator and softly switched varactors in an overlapped digitally controlled integral path to allow a large fine-tuning range of approximately 160 MHz while realizing a low susceptibility to noise and spurs by using a low $K_{rm VCO}$ of 3.2 MHz/V. The reference spur level is less than $-$70 dBc with a 1-MHz reference frequency and a total loop-filter capacitance of 26 pF. The measured phase noise is $-$75 and $-$115 dBc/Hz at 10-kHz and 1-MHz offsets, respectively, using a loop bandwidth of approximately 30 kHz. This 0.25-${hbox{mm}}^{2}$ PLL is fabricated in a 90-nm digital CMOS process and consumes 11 mW from a 1.2-V supply.      

Compact $S$ -/$Ka$-Band CMOS Quadrature Hybrids With High Phase Balance Based on Multilayer Transformer Over-Coupling Technique

This paper presents compact CMOS quadrature hybrids by using the transformer over-coupling technique to eliminate significant phase error in the presence of low-$Q$ CMOS components. The technique includes the inductive and capacitive couplings, where the former is realized by employing a tightly inductive-coupled transformer and the latter by an additional capacitor across the transformer winding. Their phase balance effects are investigated and the design methodology is presented. The measurement results show that the designed 24-GHz CMOS quadrature hybrid has excellent phase balance within ${pm}{hbox{0.6}}^{circ}$ and amplitude balance less than ${pm} {hbox{0.3}}$ dB over a 16% fractional bandwidth with extremely compact size of 0.05 mm$^{2}$. For the 2.4-GHz hybrid monolithic microwave integrated circuit, it has measured phase balance of ${pm}{hbox{0.8}}^{circ}$ and amplitude balance of ${pm} {hbox{0.3}}$ dB over a 10% fractional bandwidth with a chip area of 0.1 mm$^{2}$ .      

Low Phase Noise G$ _{m}$-Boosted Differential Gate-to-Source Feedback Colpitts CMOS VCO

This paper presents a ${g} _{ m}$-boosted differential gate-to-source feedback Colpitts (GS-Colpitts) CMOS voltage-controlled oscillator (VCO) that consumes a lower oscillation start-up current. The proposed architecture allows a wider range of saturation mode operation for the switching transistors, which helps suppress AM-to-FM conversion by these transistors. In addition, the phase noise contribution of the flicker noise in the switching transistor is reduced through the capacitor feedback network of the Colpitts oscillator. As a result, the proposed topology can achieve better phase noise performance and a higher figure of merit (FOM) compared to a conventional NMOS-only cross-coupled VCO. The proposed VCO is implemented in a 0.18-$mu{hbox {m}}$ CMOS for 1.78 to 1.93 GHz operation. At 1.86 GHz, the measurements show phase noise of $-$105 and $-hbox{128~dBc/Hz}$ (corresponding to ${rm FOM}= 191.2$) at offsets of 100 kHz and 1 MHz, respectively, while dissipating 1.8 mA from a 0.9-V supply.      

An FIR-Embedded Noise Filtering Method for $Delta Sigma$ Fractional-N PLL Clock Generators

This paper describes a noise filtering method for $Delta Sigma$ fractional- $N$ PLL clock generators to reduce out-of-band phase noise and improve short-term jitter performance. Use of a low-cost ring VCO mandates a wideband PLL design and complicates filtering out high-frequency quantization noise from the $Delta Sigma$ modulator. A hybrid finite impulse response (FIR) filtering technique based on a semidigital approach enables low-OSR $Delta Sigma$ modulation with robust quantization noise reduction despite circuit mismatch and nonlinearity. A prototype 1-GHz $Delta Sigma$ fractional-$N$ PLL is implemented in 0.18 $muhbox{m}$ CMOS. Experimental results show that the proposed semidigital method effectively suppresses the out-of-band quantization noise, resulting in nearly 30% reduction in short-term jitter.      

94 GHz Voltage Controlled Oscillator With 5.8% Tuning Range in Bulk CMOS

A 94 GHz fundamental mode voltage controlled oscillator (VCO) is demonstrated using low leakage transistors in a 65 nm digital CMOS process with six metal layers. It achieves a tuning range of 5.8% and phase noise of ${-}$ 106 dBc/Hz at 10 MHz offset from a 94.9 GHz carrier. The output power varies between ${-}$ 4 and ${-}$ 8 dBm over the tuning range. The VCO draws 6 mA bias current from a 1.5 V supply and 6 mA from a 0.8 V supply.      

An Edge Missing Compensator for Fast Settling Wide Locking Range Phase-Locked Loops

An edge missing compensator (EMC) is proposed to approach the function of an ideal PD with $pm 2 ^{N-1} times 2pi $ linear range with $N$-bit EMC. A PLL implemented with a 9-bit EMC achieves 320 MHz frequency hopping within 10 $~mu{hbox {s}}$ logarithmically which is about 2.4 times faster than the conventional design. The reference spur of the PLL is ${-}{hbox {48.7~dBc}}$ and the phase noise is ${-}hbox{88.31~dBc/Hz}$ at 10 kHz offset with $K_{rm VCO}= -$ 2 GHz/V.      

A 300 nW, 15 ppm/$^{circ}$C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs

A low-power CMOS voltage reference was developed using a 0.35 $mu$m standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, which was about 745$~$mV for the MOSFETs we used. The temperature coefficient of the voltage was 7 ppm/ $^{circ}$C at best and 15 ppm/$^{circ}$C on average, in a range from ${-}$ 20 to 80$^{circ}$ C. The line sensitivity was 20 ppm/V in a supply voltage range of 1.4–3 V, and the power supply rejection ratio (PSRR) was ${-}$45 dB at 100 Hz. The power dissipation was 0.3 $mu$W at 80$^{circ}$C. The chip area was 0.05 mm$^2$ . Our device would be suitable for use in subthreshold-operated, power-aware LSIs.