TFT-LCD过孔接触电阻研究

研究了过孔接触电阻变化规律,并进行机理分析,为优化薄膜晶体管的过孔设计提供依据。首先,运用开尔文四线检测法对不同大小、形状、数量的钼/铝/钼结构的栅极和源/漏层金属与氧化铟锡连接过孔的接触电阻进行测试。然后,通过扫描电子显微镜、能量色散X射线光谱仪和聚焦离子束显微镜对过孔内部形貌进行表征。最后,对过孔接触电阻变化规律进行机理分析。实验结果表明:过孔面积越大,接触电阻越小;过孔面积相同时,长方形过孔的接触电阻小于正方形过孔的接触电阻,多小孔的接触电阻小于单大孔的接触电阻,栅极金属与氧化铟锡的过孔接触电阻小于源/漏层金属与氧化铟锡的过孔接触电阻。为了降低钼/铝/钼与氧化铟锡连接过孔的接触电阻,过孔面积尽可能最大化,采用长方形过孔优于正方形过孔,多小过孔优于单大孔设计,同时优化过孔刻蚀工艺,减少过孔内顶层钼的损失。     

高速PCB单端过孔研究

在高速数字电路设计中,过孔的寄生电容、电感的影响不能忽略,过孔在传输路径上表现为阻抗不连续的断点,会产生信号的反射、延时、衰减等信号完整性问题。文章采用矢量网络分析仪研究了过孔长度、过孔孔径、焊盘/反焊盘直径对过孔阻抗的影响。通过在信号孔旁增加接地孔,为过孔电流提供回路方法,提高过孔阻抗的连续性,并有效降低过孔损耗。此外,文章还探讨了过孔多余短柱对过孔阻抗及损耗的影响。本研究可为高速数字电路过孔设计和优化提供依据。     

一种微带线-带状线过孔互连结构的电磁特性仿真分析

选取多层微波电路中,微带线-带状线-微带线通过过孔互连的结构模型,使用电磁仿真软件HFSS对过孔进行电磁特性分析,得出过孔散射参数(S参数)。分析不同参数:过孔半径、接地板开孔半径、是否存在接地孔对过孔的传输特性的影响。所得出结论对实际应用设计具有指导作用。     

高分辨率显示用小孔设计技术

为了满足市场对显示产品高分辨率的要求,需要从产品的设计和工艺各个方面进行优化,其中过孔尺寸和线宽两个因素对阵列基板分辨率影响最大,本文通过相移掩模技术可以实现对过孔尺寸的精确控制,通过在普通过孔上增加一定厚度和透过率的相移层,并对各种参数下过孔的光透过率进行模拟分析,可以获得不同相移层参数对过孔特性的影响,最后提出一种可以获得稳定微小过孔的方法。结果表明,通过对相移层透过率和宽度的控制,可以获得对曝光光强不敏感的稳定微小过孔,曝光量增大一倍乃至数倍的过程中,过孔尺寸始终保持稳定,提高了工艺容忍度。对于模拟中过孔尺寸可以小于设备的4μm分辨极限。通过减小过孔尺寸,可以有效提升TFT显示产品的开口率,实现产品对高分辨率的要求。     

高速PCB的过孔设计

在高速设计中，过孔设计是一个重要因素，它由孔，孔周围的焊盘区和POWER层隔离区组成，通常分为盲孔，埋孔和通孔三类，在PCB设计过程中通过对过孔的寄生电容和寄生电感分析，总结出高速PCB过孔设计中的一些注意事项。     

基于以顶层ITO为像素电极设计的产品工艺优化

HADS产品通常使用有机膜材料来减小寄生电容,以实现高像素密度(PPI)显示。本文对如何改善以顶层ITO为像素电极(Pixel Top)设计的有机膜产品的公共电极ITO与数据线间短路(DCS)不良进行了工艺优化研究。首先,通过显微镜、聚焦离子束对HADS有机膜产品DCS不良发生机理进行了分析,进而提出了第一钝化绝缘层刻蚀工序省略、保留第一钝化绝缘层至公共电极与像素电极间第二钝化绝缘层刻蚀时进行"一步刻蚀"的工艺流程变更改善方案。针对新工艺流程验证中TFT栅极过孔处第一钝化绝缘层出现的底切不良,通过调整等离子增强化学气相沉积成膜参数改善第一钝化绝缘层膜质,并选取最优成膜条件进一步调整干法刻蚀参数改善刻蚀形貌,获得了优良的栅极过孔刻蚀坡度角。优化后的"一步刻蚀"工艺进行的TFT基板,其栅极过孔第一钝化绝缘层坡度角小于40°,与栅极绝缘层间无明显刻蚀台阶。量产验证有机膜缺失导致的DCS发生率降为0。通过优化工艺,在降低产品不良率的同时还减少了工艺步骤,提升了产能。     

高速信号过孔对信号影响因素研究

影响信号完整性的因素有很多,其中过孔结构对信号影响越来越明显,如何进行有效的过孔设计从而使过孔阻抗与激励源阻抗配从而达到信号完整性已经成为当今PCB设计业界中的一个热门课题。文章通过Ansys公司的HFSS仿真软件,利用仿真方法分析不同信号过孔结构对高速信号的影响,并对过孔残桩长度（stub）,反焊盘,焊盘的不同大小对信号差损影响程度做了进一步研究。     

采用轴对称二维有限元法提取过孔分布电容

采用简便的两维轴对称有限元法分析了四层印制电路板的过孔电容。将极坐标形式的拉普拉斯方程变换成直角坐标形式,避免了复杂的椭圆积分。将过孔的电容分层处理,分析了过孔的高度、半径、焊盘半径等参数对过孔电容的影响。与有限元分析软件ANSYS进行了对比,计算结果基本一致。此方法可用于任意层复杂印制电路板过孔电容的提取,所得结论有助于过孔的等效电路建模以及高速PCB的信号完整性分析。     

45°准同轴微波多层过孔TDR仿真技术

准同轴微波多层过孔是微波多层印制技术中常用的跨层互连形式,当互连结构较为复杂时,其微波性能会对系统指标构成较大影响,目前研究微波过孔的手段还主要局限于理论推导和频域仿真。首次使用TDR仿真技术,对45°准同轴微波多层过孔进行了建模、仿真和分析,并对过孔尺寸进行了优化,所得到的微波多层过孔结构具有较理想的50Ω阻抗特性,同时在很宽的频带内展现出良好的微波特性,进而验证了TDR仿真方法在分析准同轴微波多层过孔结构上的有效性。     

PCB布线中的过孔和电容效应分析和结构优化

在多层PCB布线中,过孔和电容是常见的不连续结构。信号线在不同平面间转换传输路径时,过孔与回流层之间的寄生电容与寄生电感将引起信号完整性的相关问题;而常用的传输线上的AC耦合电容等,引入了阻抗突变的结构,由此带来了反射等相关问题。通过对多层PCB上的过孔进行建模仿真,研究不同变量对过孔性能的影响趋势,以协助信号完整性问题的分析;通过对电容阻抗突变处进行不同形式的补偿,仿真和测试结果相验证,得到提高信号传输质量的解决方案。     

钝化层沉积工艺对过孔尺寸减小的研究

为了适应TFT-LCD小型化与窄边框化以及在面板布线精细化的趋势,提高工艺设计富裕量以及增加面板的实际利用率,研究了通过改变钝化层(PVX)的沉积工艺来减小液晶面板阵列工艺中连接像素电极与漏极的过孔(VIA)尺寸的方案,通过设计实验考察了影响过孔大小的钝化层的主要影响因素(黑点、倒角、顶层钝化层沉积厚度,顶层钝化层沉积压力),得出了在不改变原有刻蚀方式基础之上使过孔的尺寸降低20%～30%的优化方案,并对其进行了电学性能评价(Ion:开态电流、Ioff:关态电流、Vth:阈值电压、Mobility:迁移率),从而获得了较佳的减小过孔尺寸的方案,提高了产品品质。     

Plasma charging damage during contact hole etch in high-density plasma etcher

Plasma process induced damage from high-density plasma dielectric etcher was studied comprehensively. It was observed that PMOS devices were damaged more readily than NMOS devices. Low field gate current is the most sensitive parameter to reflect the permanent damages. Some permanent damages become hidden defects after backend of line processes. These latent damages in the form of gate oxide traps result in poor oxide integrity during Fowler–Nordheim stress or hot carrier stress. The damage shows good correlation with the total exposed contact area. The safe antenna ratio is much lower than that at the conductor etch, although no electron shading effect was observed. Thus, plasma damage during contact or via hole etch in high-density plasma system must be considered carefully.     

A novel fabrication process of a silicon field emitter array withthermal oxide as a gate insulator

We have successfully developed a fabrication process of a silicon field emitter array with a gate insulator formed by Si₃N₄ sidewall formation and subsequent thermal oxidation. This process overcomes some problems in the conventional fabrication, such as high etch rate, low breakdown field, and gate hole expansion arising from evaporation of gate oxide. Therefore, we could improve process stability and emission performance, and also reduce gate leakage current. The optimum process conditions were determined by process simulations using SUPREM-4. The turn-on voltage of the fabricated field emitters was approximately 38 V. An anode current of 0.1 μA (1 μA) per tip was measured for a 625-tip array at the gate bias of 80 V (100 V), and the gate current was less than 0.3% of the anode current at those emission levels     

Strained InGaAs/GaAs quantum well constricted-mesa lasers andapplication in a vertical-twin-guide tunable laser

Constricted-mesa semiconductor lasers containing a strained-layer InGaAs single-quantum-well-separate-confinement-heterostructure have been demonstrated. Very high etching selectivity between Al_xGa_1-xAs (x=0.9) and Al_xGa _1-xAs (x=<0.6) was achieved using diluted hydrofluoric acid to create a deeply undercut current confinement region, which enables a side contact for current injection. A process combining a self-aligned reactive ion etch and the undercut wet chemical etch has been developed for implementing a vertical twin-guide three-electrode tunable laser structure. Low-threshold currents for both single-guide devices with centered top contacts (5.2 mA) and twin-guide ones with side contacts (6.5 mA) were obtained     

0.5μm AlGaN/GaN HEMT及其应用

报道了采用I线步进光刻实现的76.2 mm SiC衬底0.5μm GaN HEMT.器件正面工艺光刻均采用了I线步进光刻来实现,背面用通孔接地.栅脚介质刻蚀采用一种优化的低损伤RIE刻蚀方法实现了60°左右的侧壁倾斜角,降低了栅脚附近峰值电场强度,提高器件性能和可靠性.研制的GaN HEMT器件fT为15 GHz,fm...     

Interplay of plasma etch, strip and wet clean in patterning La2O3/HfO2-containing high-κ/metal gate stacks

The removal process of the La₂O₃/HfO₂ dielectric and of the residues after metal gate etch are discussed. The challenges are presented and related to the specific physico-chemical properties of La-containing compounds. Solutions based on optimization of plasma etch, strip and wet clean are demonstrated for both an integrated and delayed etch-clean process. Both processes meet the stringent requirements of complete removal of the high-κ layers and metal-containing sidewall residues without inducing silicon recess or undercut.     

先进CMOS器件中poly-Si/TaN/HfSiON栅结构的干法刻蚀研究

研究了先进CMOS器件中poly-Si/TaN/HfSiON栅结构的干法刻蚀工艺。对于poly-Si/TaN/HfSiON栅结构的刻蚀,我们采用的策略是对栅叠层中的每一层都进行高选择比地、陡直地刻蚀。首先,对于栅结构中poly-Si的刻蚀,开发了一种三步的等离子体刻蚀工艺,不仅得到了陡直的poly-Si刻蚀剖面而且该刻蚀可以可靠地停止在TaN金属栅上。然后,为了得到陡直的TaN刻蚀剖面,研究了多种BCl3基刻蚀气体对TaN金属栅的刻蚀,发现BCl3/Cl2/O2/Ar等离子体是合适的选择。而且,考虑到Cl2对Si衬底几乎没有选择比,采用优化的BCl3/Cl2/O2/Ar等离子体陡直地刻蚀掉TaN金属栅以后,我们采用BCl3/Ar等离子体刻蚀HfSiON高K介质,改善对Si衬底的选择比。最后,采用这些新的刻蚀工艺,成功地实现了poly-Si/TaN/HfSiON栅结构的刻蚀,该刻蚀不仅得到了陡直的刻蚀剖面且对Si衬底几乎没有损失。     

Deep dry etching of borosilicate glass using SF6 and SF6/Ar inductively coupled plasmas

Deep reactive ion etching (DRIE) of borosilicate glass was carried out using SF₆ and SF₆/Ar plasmas in an inductively coupled plasma (ICP) reactor. Electroplated Ni on Cu (≅50 nm)/Cr (≅100 nm)/glass structure using patterned SU-8 photoresist mask with a line spacing of 12-15 μm was used as a hard-mask for plasma etching. Plasma etching of borosilicate glass was performed by varying the various process parameters such as the gas chemistry, the gas flow ratio, the top electrode power, and the dc self-bias voltage (V_dc). In the case of using SF₆ gas only, the profiles of the etched channel showed the undercut below the Ni hard-mask due to a chemical etching and the microtrenching at the bottom of the etched channel. An optimized process using the SF₆ plasmas showed the glass etch rate of ≅750 nm/min. The addition of the Ar gas to the SF₆ gas removed the undercut and microtrenching but decreased the etch rate to ≅540 nm/min. The increasing and decreasing time-dependent etch rates with the etch depth in the SF₆ (200 sccm) and SF₆(60%)/Ar(40%) plasmas, respectively, were ascribed to the different ion-to-neutral flux ratios leading to the different etch process regime.     

New Gate CD Control Technology Using CF 4 Plasma Treatment Following HBr/O 2 Plasma Treatment Step in Gate Etch Process Using Organic BARC

A new technology of resist trimming in a gate etch process using organic bottom antireflective coating (BARC) for accurate and stable gate critical dimension (CD) control of sub-0.18-mum node technology is presented in this paper. The new method uses an in situ CF₄ plasma treatment following an HBr/O₂ plasma treatment step as a part of the gate etch process to achieve a stable gate CD. The new method controls gate CD by trimming the photo resist masking gate line by reducing the effect of etch by-products, the source of CD variation, after etching organic BARC with HBr/O₂ plasma. It shows the markedly improved gate CD capability over the conventional one using just an HBr/O₂ plasma treatment for the CD control. We confirm that this new method is very useful and effective for the accurate gate CD control for sub-0.18-mum node metal-oxide semiconductor technology     

Supervisory run-to-run control of polysilicon gate etch using insitu ellipsometry

Polysilicon gate etch is a critical manufacturing step in the manufacturing of MOS devices because it determines the tolerance limits on MOS circuit performance. The etch used in the current study suffers from machine aging, which causes processing results to drift with time. Performing the etch for the same time with fixed process setpoints (recipe) for all wafers would produce unsatisfactory results. Thus, an in situ ellipsometer was employed with a new run-to-run supervisory controller, termed predictor corrector control (PCC), to eliminate the impact of machine and process drift. A novel modeling technique was used to predict uniformity from the ellipsometry data collected at a single site on the wafer. Predictive models are employed by the PCC supervisory controller to generate optimal settings (recipe) for every wafer which will achieve a target mean etch rate, while maintaining a spatially uniform etch. A 200 wafer experiment was conducted to demonstrate the benefits of process control. Implementation of PCC resulted in a 36% decrease in standard deviation from target for the mean etch rate. In addition, the data indicates that controlling etch rate may improve the control and uniformity of the line width change