TFT阵列基板过孔电阻与耐流性能研究

薄膜晶体管阵列基板过孔电阻大、耐流性差易发生过孔烧毁,引起显示异常。目前针对过孔电阻与耐流性影响因素及机理尚不明确,制约着未来高耐流性过孔的制备和应用。本文实验结果表明：氧化铟锡(Indium Tin Oxide, ITO)膜方块电阻减小、过孔坡度角减小、ITO膜与金属接触面积增大均可降低过孔电阻、提升过孔耐流性。结合过孔结构及机理分析指出,过孔电阻主要由ITO膜层自身电阻(R_ITO)及过孔接触电阻(R_contact)组成,ITO膜方块电阻及过孔坡度角减小会使R_ITO减小,ITO膜与金属接触面积增大会使R_contact减小。基板中部过孔耐流性差与中部的ITO膜方块电阻及过孔坡度角偏大有关。在满足产品光学品质标准前提下,ITO膜厚增厚、调控绝缘层膜质以及干法刻蚀参数减小坡度角、加大过孔接触面积设计是降低过孔电阻、提升过孔耐流性的有效途径。     

ITO连接过孔电阻定量计算与设计方法

TFT-LCD面板内的ITO连接过孔目前只有一些定性的设计规则,缺乏定量计算和设计过孔的方法。本文研究了此类过孔电阻的定量计算方法,同时探索了过孔电阻与击穿电流的关系,为合理设计过孔、防止过孔烧毁提供了指导依据。首先,通过分析过孔的结构,抽象出等效电阻电路图,得到多种不同结构的过孔电阻分解公式。过孔电阻主要由深孔接触电阻、浅孔接触电阻和深浅孔之间连接的ITO电阻组成。然后,通过设计不同尺寸的金属与ITO的接触过孔,使用开尔文四线检测法测量得到深孔接触电阻和浅孔接触电阻与孔尺寸之间的关系式。同时,深浅孔之间连接的ITO电阻可通过ITO方块电阻与深浅孔之间的ITO尺寸计算得到。由此,我们仅依据过孔的尺寸信息及ITO方阻数据即可计算得到各种结构的过孔电阻阻值。通过对大量过孔电阻的实测值与计算值进行相关性分析,线性相关系数达到0.96,证明了该计算方法的可靠性。最后,通过测量大量过孔的电阻阻值及其击穿电流值,发现过孔电阻阻值与击穿电流之间存在显著的幂函数关系,幂指数在-1.3附近,相关系数达到0.98。自此,建立起了一整套可定量计算和设计过孔电阻和击穿电流的方法。     

垂直线不良分析与改善

针对栅极绝缘层和栅极引线接触处形成过孔倒角造成的一种垂直线不良进行分析和改善。研究气相沉积、干法刻蚀和磁控溅射对过孔倒角的影响,通过扫描电子显微镜对过孔形貌进行表征,并用成盒检测设备检测不良发生情况。实验结果表明:通过过孔刻蚀功率、气压、气体流量的变更可以消除倒角现象,垂直线不良由1.4%降为0.7%。     

一种新型的自对准源漏接触技术

提出了一种用于亚微米尺寸以下MOSFET器件的自对准源漏接触技术。这种新型的集成方法改变了传统的工艺步骤,即光刻接触孔,然后向里填充导电材料。在形成栅极、绝缘介质侧墙以及自对准金属硅化物以后,通过沉积金属膜层,并各向异性刻蚀以在绝缘介质侧墙两旁形成一对金属的侧墙结构。这个侧墙连接底部的源漏区和上部的互联区,作为底层的金属接触引出。这个方法不仅减小了刻蚀接触孔的难度,且采用自对准的方法形成金属接触也减小了源漏接触的距离,提高了集成度。这项工艺集成技术尝试应用于0.5μm栅长MOSFET器件结构中,并仿真得到了良好的电学性能。     

整平前处理对过孔进锡的影响及其改善

随着PCB产品朝着精密化、微型化方向发展,尺寸越小的过孔就越能提供足够的布线空间,以求达到高密度布线的目的。由于过孔尺寸偏小以及高厚径比板的局限,过孔进锡问题是PCB热风整平工艺制程中的一大难点。本人从整平前处理对过孔进锡的影响机理出发,通过试验最终找到解决过孔进锡的有效方法。     

深亚微米工艺ESD电路设计参数研究

通过器件级仿真来评估ESD保护器件的鲁棒性的方法,对ESD电路的关键设计参数进行了研究.通过器件仿真软件MEDICI对栅极到源极接触孔的距离,栅极到漏极接触孔的距离以及栅极的宽度和长度对ESD性能的影响进行了研究,并分析了它们的失效机理.从而得出经验公式,可以在流片前估算出器件的ESD失效电压.通过在设计阶段预测器件的ESD性能可以缩短设计周期,节约成本.     

高速PCB单端过孔研究

在高速数字电路设计中,过孔的寄生电容、电感的影响不能忽略,过孔在传输路径上表现为阻抗不连续的断点,会产生信号的反射、延时、衰减等信号完整性问题。文章采用矢量网络分析仪研究了过孔长度、过孔孔径、焊盘/反焊盘直径对过孔阻抗的影响。通过在信号孔旁增加接地孔,为过孔电流提供回路方法,提高过孔阻抗的连续性,并有效降低过孔损耗。此外,文章还探讨了过孔多余短柱对过孔阻抗及损耗的影响。本研究可为高速数字电路过孔设计和优化提供依据。     

TFT-LCD制造工艺中金属或金属复合膜层坡度角的研究

在薄膜晶体管液晶显示器(TFT-LCD)面板制程中,Gate层(栅极)电路和SD层(源极)电路根据产品电阻等要求可以使用纯金属膜层,如钼、铜等金属膜层,也可以使用金属复合膜层,如铝钼、铝钕钼、钼铝钼等金属复合膜层。当使用不同金属或金属复合膜层作为Gate、SD电路时,应当对应不同的刻蚀液。但在实际生产时,往往是一种刻蚀液同时对应金属膜层或金属复合膜层。由于钼金属膜层的Etch Rate(刻蚀速率)大于铝钼等金属复合膜层Etch Rate,所以当铝钼等金属复合膜层刻蚀完成后对应坡度角有时会存在异常,如膜层角度较大(80～90°)、顶层金属钼发生尖角或缩进等现象,产生宏观不良及进行后工序时会产生相应的光学不良或导致后层物质残留,影响产品品质。本文针对金属膜层或金属复合膜层坡度角进行影响因素分析,主要受刻蚀工序及曝光工序影响。通过对刻蚀液浓度调整、温度调整、刻蚀方式调整及曝光工序等调整减少金属钼发生尖角、缩进几率,将金属膜层坡度角控制在60°左右及金属复合膜层坡度角控制在50°左右,从而降低不良的发生率,提高产品品质。     

栅极导电层Au迁移导致放大器失效原因分析

针对限幅低噪声放大器使用过程中出现输出不稳定现象,利用扫描电镜和能谱仪对场效应管栅极表面的金属缺失层和栅源之间的金属堆积物进行微观分析,寻找放大器工作不正常的原因。结果表明:场效应管栅极Au层的电迁移,使导线局部电阻增大,温度升高,导致Au的热迁移加重,引起导线出现孔洞和栅源中间堆积金属颗粒,使栅极导线出现开路和栅源极间产生不稳定接触,最终导致场效应管的工作参数漂移和放大器工作不正常。     

栅极导电层Au迁移导致放大器失效原因分析

针对限幅低噪声放大器使用过程中出现输出不稳定现象,利用扫描电镜和能谱仪对场效应管栅极表面的金属缺失层和栅源之间的金属堆积物进行微观分析,寻找放大器工作不正常的原因。结果表明:场效应管栅极Au层的电迁移,使导线局部电阻增大,温度升高,导致Au的热迁移加重,引起导线出现孔洞和栅源中间堆积金属颗粒,使栅极导线出现开路和栅源极间产生不稳定接触,最终导致场效应管的工作参数漂移和放大器工作不正常。     

Electroluminescence from phenylenevinylene-based polymer blends

The electroluminescent behaviour of films of poly(phenylphenylenevinylene) (PPPV), of PPPV blended with polystyrene (PS) and of PS doped with oligo(phenylenevinylene) sandwiched between indium–tin oxide (ITO) and Al contacts has been investigated. Polymer blending increases the relative quantum efficiency by up to two orders of magnitude. Studying the cell performance under application of rectangular voltage pulses as a function of temperature indicates that (i) hole injection at the ITO contact occurs by tunnelling, (ii) tunnel injection of electrons at the cathode is promoted by a space charge field across an interfacial Al₂O₃ layers and (iii) leakage of holes through the cathodic barrier is the main loss mechanism for holes.     

Electrical measurement of submicrometer contact holes

A technique to measure submicrometer-sized isolated features electrically is described. P.M. Hall's formula (1967-8) modified with an experimentally determined coefficient is used to obtain the hole diameter and the hole area from the electrically measured linewidth with a higher precision than the precision of the linewidth itself. By incorporating a large number of features in a single test structure, a gain in precision of better than 3 nm is shown analytically. The contact hole diameter and the area of the isolated features obtained in this way, were found to be accurate when compared with physical measurements using a scanning electron microscope. The test pattern used is a combination of two basic four-point probe linewidth-measuring structures and two modified ones. The modified structures contain a large number of contact holes in the 10-μm lines running in the horizontal and vertical directions, which reduce the apparent electrical linewidth. Subtracting the reduced linewidth from that of a solid reference line removes the other contributions to linewidth variation. The size of the contact holes can then be derived from these results. The special test pattern, an analytic expression for interpretation of the results, and hole size data from a variety of exposure dosages are discussed     

Mutual coupling in a finite planar array with interelement holespresent

The mutual coupling in a finite planar array with interelement holes present was considered. A computer program designed to study mutual coupling between rectangular waveguides was modified to include coupling between elements of different sizes. This modified program was used to study the problem of widely spaced rectangular waveguides that form smaller rectangular holes in the ground plane. Comparisons with experimental data confirmed the validity of the model. Tests run at various hole sizes showed that holes that are much smaller than their cutoff size have little effect on the coupling. For the rectangular-hole case, hole widths of less than half the cutoff width of the dominant mode had little effect     

Effects of contact electrode size on the characteristics of polycrystalline-Si p-i-n solar cells

The effects of contact electrode size on the photo-voltaic characteristics of polycrystalline-Si p-i-n solar cells have been studied,with respect to a unit-cell pitch size of 1μm width.For the non-transparent Al contact electrode with a contact width of 0.05-0.2μm,the short-circuit current is obviously reduced with increasing contact width,due to a larger area of optical reflection by the electrode.On the other hand,even when using a transparent ITO(indium-tin-oxide) electrode,a larger width of contact electrode may also cause a smaller short-circuit current, due to a larger area of optical absorption by the electrode.However,for this ITO electrode,the contact electrode of 0.05μm width causes a smaller short-circuit current than that of 0.1μm width,primarily ascribed to a smaller area for collecting carrier and a larger contact resistance.As a result,while using the ITO contact electrode to enhance the conversion efficiency of the solar cell,a proper width of contact electrode should be employed to optimize the photo-voltaic characteristics.     

电磁脉冲对带孔缝腔体的耦合特性

利用时域有限差分方法(FDTD)研究了电磁脉冲对带孔缝导体腔的耦合特性。为减少存储空间而采用非均匀网格法,分别对腔体上开有不同形状(正方形、长方形)和不同数目孔缝时的耦合效应进行分析。结果表明,在孔洞面积相同的情况下,电磁脉冲对正方形孔洞的耦合能量较小;而对长方形,当脉冲的极化方向与孔洞短边平行时,耦合能量最大;此外,把单个孔洞分成总面积不变的多孔洞后,耦合能量减小;同时,在保持通风面积不变的情况下,将原本开在一层屏蔽板上的孔缝交错地开在两层板上,能够明显改善屏蔽效果。     

ITO薄膜的电阻并联效应研究

采用电子束蒸发镀膜方法在K9玻璃基底上分别镀制了ITO/SiO₂/ITO,ITO/Ti₂O₃/ITO和ITO/MgF₂/ITO结构的多层薄膜,用四探针方块电阻仪测量薄膜表面的方块电阻,用原子力显微镜观测样品的表面微观形貌。结果显示,当ITO薄膜的粗糙度较大且介质薄膜的物理厚度小于100nm时,各层ITO薄膜之间通过山峰状的凸起结构相连通,导致样片表面的方块电阻测量值与各层ITO薄膜电阻的并联值相当。这表明,当ITO薄膜的粗糙度较大且介质薄膜厚度较小时,各层ITO薄膜表现出电阻并联效应。利用多层ITO薄膜的电阻并联效应设计并制备了450～1200nm超宽光谱透明导电薄膜,用四探针方块电阻仪测量了试验样片的表面方块电阻,用紫外-可见-近红外分光光度计测试了样片的光谱透射率。结果显示,在相同表面方块电阻条件下,相比于单层ITO薄膜,利用ITO薄膜电阻并联效应所制备的多层透明导电薄膜具有更高的光谱透射率。     

新型的3D堆叠封装制备工艺及其实验测试

为了满足超大规模集成电路(VLSI)芯片高性能、多功能、小尺寸和低功耗的需求,采用了一种基于贯穿硅通孔(TSV)技术的3D堆叠式封装模型.先用深反应离子刻蚀法(DRIE)形成通孔,然后利用离子化金属电浆(IMP)溅镀法填充通孔,最后用Cu/Sn混合凸点互连芯片和基板,从而形成了3D堆叠式封装的制备工艺样本.对该样本的接触电阻进行了实验测试,结果表明,100 μm2Cu/Sn混合凸点接触电阻约为6.7 mΩ高90 μm的斜通孔电阻在20～30mΩ该模型在高达10 GHz的频率下具有良好的机械和电气性能.     

横向接触式RF MEMS开关

提出了一种横向接触式RF MEMS开关,采用金属叉指结构进行驱动。通过结构建模和性能仿真,对叉指结构进行了优化,提高了机械性能,减小开关的尺寸。通过加大横向接触面积,降低接触电阻,减小开关导通态的插损,提高了开关的射频性能。利用低温表面牺牲层工艺在砷化镓衬底上进行了开关的流片,通过工艺的改进最终得到满意的流片结果。测试结果表明:在DC-20GHz频率范围内,开关的插入损耗小于0.3dB,隔离度大于20dB。     

Novel contact hole fabrication using selective liquid-phasedeposition instead of reactive ion etching

This work forms a contact hole utilizing the selectively liquid-phase deposited (S-LPD) silicon-oxide technique instead of the conventional reactive ion etching (RIE). The n⁺/p junction diode with contact hole formed by S-LPD exhibits an order of magnitude less reverse current, larger forward current, smaller ideality factor, and better thermal stability than that formed by RIE. A Schottky junction with S-LPD contact hole also possesses several excellent characteristics, including ideality factor, reverse current and barrier height, even without sintering treatment. These characteristics confirm the effectiveness of the S-LPD technique in replacing conventional RIE to form contact holes, particularly for future ultra-shallow junctions     

BGA密集孔耐热性能影响因素分析

文章以球栅阵列（BGA）密集孔耐热性能影响因素进行分析，考虑多层压合、机械钻孔、湿处理等工艺流程参数对耐热性能的影响，通过DOE方式，确定各制程对耐热性的影响程度，优化加工参数，改善BGA孔耐热性能。