TFT-LCD器件Al电极TFT特性研究

本文对Mo/Al/Mo作为TFT-LCD器件源/漏极的TFT特性进行了研究。与单层Mo相比,存在沟道界面粗糙,I_(off)偏大问题,通过优化膜层结构,改善界面状态,得到了平整的沟道界面和良好的TFT特性。增加Bottom Mo的厚度,可以有效减少Al的渗透,防止Al-Si化合物的形成,得到界面平整的沟道;N~+刻蚀后SF6处理对特性影响不大,增加刻蚀时间可以使I_(on)和I_(off)同时降低;PVX沉积前处理气体N_2+NH_3与H_2区别不大,都可以减少沟道缺陷,而增加H_2处理时间会增强等离子的轰击作用,减少了沟道表面Al-Si化合物,但处理时间过长可能会使沟道缺陷增加;采用bottom Mo加厚,N~+刻蚀以及PVX沉积前处理等最优条件,可以得到沟道界面良好,TFT特性与单层Mo相当的TFT器件。     

a-Si剩余膜厚对TFT特性的影响

本文通过电学特性测试设备在黑暗(Dark)和光照(Photo)两种测试环境下,研究了沟道不同a-Si剩余厚度对TFT电学特性的影响。通过调整刻蚀时间改变沟道内a-Si剩余厚度,找出电学特性稳定区域以及突变的临界点。实验结果表明:在黑暗(Dark)环境下a-Si剩余厚度在30%～48%之间时,TFT器件的电学特性比较稳定,波动较小;而剩余厚度少于30%时,TFT特性变差,工作电流变小,开启电压变大,电子迁移率变小;在光照环境下主要考虑漏电流的影响,在a-Si剩余厚度43%以内时,光照I_(off)相对较低(小于Spec 20pA),同时变化趋势较缓;而剩余厚度大于43%时,光照I_(off)增加25%,同时变化趋势陡峭。综合黑暗和光照测试环境,在其他条件不变的情况下,a-Si剩余厚度在30%～43%之间时TFT的电学特性较好,同时相对稳定。     

a-Si TFT亚阈特征参数与有源层的厚度效应

从异质界面处的有效界面态出发 ,研究了 a-Si Nx:H/a-Si:H异质结 a-Si:H TFT的亚阈特征参数的界面效应和有源层的厚度效应 ,发现 a-Si:H的特性不仅与材料、工艺有关 ,而且其几何结构参数对 a-Si:H TFT的特性也有明显的影响。实验结果表明 :亚阈特征参数主要由异质界面的有效界面态密度决定 ,当 NH3/Si H4 比增加时亚阈特征参数下降 ,增加 a-Si Nx 材料的淀积温度 ,可使亚阈特性得到明显的改善 ,a-Si:H有源层的厚度减小 ,抑制了亚阈参数的增加 ,阈值电压也减小并趋于稳定 ,且 TFT的 ION/IOF F随有源层厚度呈现近似抛物线状变化规律。文中从理论上分析了有源层厚度与 TFT特性的关系 ,计算的最佳有源层的厚度约为 2 0 0 nm,这与实验结果基本一致。     

氧化锌基TFT稳定性研究进展

总结了氧化锌基TFT稳定性的最新研究进展,分析了栅偏压、栅绝缘层和背沟道影响TFT稳定性,尤其是阈值电压稳定性的主导机制.结果表明,氧化锌基TFT的不稳定性主要取决于陷阱缺陷态对可动载流子的俘获作用,以及新陷阱态的产生.总结了提高氧化锌基TFT稳定性的三种途径:降低栅偏压;提高沟道/栅绝缘层界面质量,降低缺陷态密度;钝化保护背沟道.     

a-Si厚度对TFT开关特性的影响

通过在线电学测试设备,研究了不同a-Si厚度对TFT开关电学特性的影响。本试验通过调整刻蚀时间改变沟道内a-Si的剩余厚度,在此基础上找出电学特性比较稳定的区域和电学特性变差的临界点。试验结果表明,在其它条件不变的情况下,a-Si剩余厚度在33～61%时TFT的电学特性比较好,a-Si剩余厚度小于33%之后,TFT的电学特性变差,即工作电流变小,阈值电压变大,迁移率变小。     

顶栅共面结构非晶氧化物薄膜晶体管的低成本制备及性能研究

将溶液法制备的不含镓的非晶InAlZnO薄膜和有机聚甲基丙烯酸甲酯薄膜分别作为沟道层和介质层,制备了顶栅共面结构的非晶氧化物薄膜晶体管(TFT)器件,探讨了沟道层中Al含量对器件性能的影响。结果表明：Al对InZnO薄膜中氧空位的形成能起到一定抑制作用,增加Al含量即可降低沟道层中的电子载流子浓度,使得InAlZnO TFT器件阈值电压正向移动、关态电流减小,以有利于器件开关比的提升。此外,基于沟道层中Al含量的调整可通过优化沟道层/介质层界面状态来促进器件阈值电压滞回稳定性的提升。当沟道层中Al含量为30%时,制备的器件具有最佳综合性能。     

浸渍提拉法制备有机介质层铝铟锌氧薄膜晶体管

利用溶液法的浸渍提拉工艺制备了以有机聚甲基丙烯酸甲酯(PMMA)为介质层、非晶铝铟锌氧化物(a-AIZO)为沟道层的顶栅共面结构薄膜晶体管(TFT),研究了沟道层退火温度对TFT性能的影响机理。结果表明:较低退火温度(如300和350℃)下处理的沟道层中存在未彻底分解的金属氢氧化物,其以缺陷态形式存在于TFT沟道层内或沟道层/介质层界面处,对导电沟道中电子进行捕获或散射,劣化TFT的迁移率、电流开关比以及亚阈值摆幅。综合来看,退火温度高于400℃下制备的a-AIZO适用于TFT器件的沟道层,相应的器件呈现出较高的迁移率(大于20cm2/(V·s))、较低的亚阈值摆幅(小于0.5V/decade)以及高于104的电流开关比。     

a-Si:H TFT亚阈值区SPICE模型的研究

研究了将非晶硅薄膜晶体管（a-Si：H TFT）在电路模拟程序（SPICE）中使用的亚阈值区模型,将亚阈值区分为亚阈值前区和亚阈值后区并建立了模型,对比了不同模型下的模拟结果,发现亚阈值区的TFT特性依赖于材料性质,而且亚阈值前区和亚阈值后区的特性受栅源电压Vcs和漏源电压V DS的影响,呈指数变化。提出的新模型考虑了前界面态、后界面态、局域态、材料及制作工艺等因素,体现了该区域电流对漏源电压Vvs强烈的依赖关系。使用新模型对实验数据的拟合结果优于以往的模型,能够比较精确地模拟亚阈值区的特性,可用来预测a-Si：H TFT的性能．对TFT阵列的模拟设计具有重要价值。     

SiO2/4H-SiC界面氮化退火

通过1 300℃高温干氧热氧化法在n型4H-SiC外延片上生长了厚度为60 nm的SiO2栅氧化层.为了开发适合于生长低界面态密度和高沟道载流子迁移率的SiC MOSFET器件产品的栅极氧化层退火条件,研究了不同退火条件下的SiO2/SiC界面电学特性参数.制作了MOS电容和横向MOSFET器件,通过表征SiO2栅氧化层C-V特性和MOSFET器件I-V特性,提取平带电压、C-V磁滞电压、SiO2/SiC界面态密度和载流子沟道迁移率等电学参数.实验结果表明,干氧氧化形成SiO2栅氧化层后,在1 300℃通入N2退火30 min,随后在相同温度下进行NO退火120 min,为最佳栅极氧化层退火条件,此时,SiO2/SiC界面态密度能够降低至2.07×1012 cm-2·eV-1@0.2 eV,SiC MOSFET沟道载流子迁移率达到17 cm2·V-1·s-1.     

TFT-LCD高温光照漏电流改善研究

造成TFT不稳定的问题点一般认为有两种:一是沟道内半导体材料内部的缺陷,另一个是栅极绝缘层内的或是绝缘层与沟道层界面的电荷陷阱。TFT-LCD在长期运行时由于高温及光照的影响会导致漏电流增加,进而对TFT造成破坏。分析研究表明,TFT沟道在刻蚀完成后,沟道内部存在一定的缺陷以及绝缘层与沟道层界面存在电荷陷阱,平面电场宽视角核心技术-高级超维场转换技术型产品由于设计的原因面临着如果进行氢处理会导致与其与氧化铟锡中的铟发生置换反应,导致铟的析出,所以无法采用氢处理。理论分析表明Si-O键稳定,本文主要介绍通过氯气/氧气和六氟化硫/氧气对TFT沟道进行处理改善高温光照漏电流。结果表明,通过氯气/氧气和六氟化硫/氧气处理TFT沟道后,高温光照漏电流从18.19pA下降到5.1pA,可见氯气/氧气和六氟化硫/氧气对沟道处理可有效改善高温光照漏电流。     

TFT栅极绝缘层和非晶硅膜层的ITO污染对电学特性影响的研究

本文对TFT在栅极绝缘层和非晶硅膜层沉积过程中,透明电极ITO成分对膜层的污染和TFT电学性质的影响进行分析研究。通过二次离子质谱分析和电学测试设备对样品进行分析。ITO成分会对PECVD设备、栅极绝缘层和非晶硅膜层产生污染,并会影响TFT的电学特性。建议采用独立的PECVD设备完成ITO膜层上面的栅极绝缘层和非晶硅膜层的沉积,并且对设备进行周期性清洗,可降低ITO成分的污染和提高产品的电学性能。     

Amorphous silicon thin-film transistor with fluorinated siliconoxide ion stopper

We propose fluorinated silicon oxide (SiOF) as the ion-stopper of bottom-gate amorphous silicon thin film transistors (a-Si:H TFTs). The low dielectric constant SiOF on both the back-channel of the TFT and the crossover regions of gate/data lines can contribute to reducing the RC delay of the gate pulse signal in active-matrix liquid-crystal displays. Besides, the a-Si:H TFT with a SiOF stopper shows an improved performance compared to the widely-employed silicon nitride (SiN_x ) stopper TFT, because the fluorine incorporation reduces the interface state density between a-Si:H and SiOF     

Hydrogen dilution effect on the properties of coplanar amorphoussilicon thin-film transistors fabricated by inductively-coupled plasmaCVD

The electrical and optical properties of the hydrogenated amorphous silicon (a-Si:H) films deposited by inductively-coupled plasma (ICP) chemical vapor deposition (CVD) with a variation of H₂ flow rate have been studied. The photosensitivity of a-Si:H is ~10⁷ when the H₂/SiH₄ ratio is between 3 and 8. With increasing H₂/SiH₄, the SiH₂ mode infrared absorption has a minimum at a H₂/SiH₄ ratio of 8. Coplanar a-Si:H thin-film transistors (TFT's) were fabricated using a triple layer of thin a-Si:H, silicon-nitride, and a-Si:H deposited by ICP-CVD using ion doping and low resistivity Ni silicide. After patterning the thin a-Si:H/silicon-nitride layers on the channel region, the gate and source/drain regions were ion-doped and then heated at 230°C to form Ni silicide layers. The low resistive Ni silicide formed on the a-Si:H reduces the offset length between gate and source/drain, leads to a coplanar a-Si:H TFT. The TFT exhibited a field effect mobility of 0.6 cm²/Vs and a threshold voltage of 2.3 V at the H₂/SiH₄ ratio of 8. The effect of H₂ dilution in SiH₄ on the coplanar a-Si:H TFT performance has been investigated. We found that the performance of the TFT is the best when the SiH₂ mode density in a-Si:H is the minimum. The coplanar TFT is very suitable for large-area, high density TFT displays because of its low parasitic capacitance between gate and source/drain contacts     

Copper gate hydrogenated amorphous silicon TFT with thin bufferlayers

We demonstrated a Cu gate hydrogenated amorphous silicon thin-film transistor (TFT) with buffer layers. We introduced an AlN/Cu/Al₂ O₃ multilayer for a gate of an a-Si:H TFT. The Al₂ O₃ improves the adhesion to glass substrate and AlN protect the Cu diffusion to the TFT and plasma damage to Cu during plasma enhanced chemical vapor deposition of silicon-nitride. An a-Si:H TFT with a Cu gate exhibited a field effect mobility of 1.18 cm² V/s, a gate voltage swing of 0.87 V/dec., and a threshold voltage of 3.5 V     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

Application of liquid phase deposited silicon dioxide tometal-oxide-semiconductor capacitor and amorphous silicon thin-filmtransistor

Liquid phase deposited silicon dioxide (LPD-SiO₂) is applied to crystalline Si metal-oxide-semiconductor (MOS) capacitor as the gate insulator. It is demonstrated that slow states exist at the Si/SiO₂ interface which cause hysteresis in the capacitance-voltage (C-V) characteristics. These slow states can be removed effectively by post-metallization-anneal. By means of C-V measurement and infrared absorption spectroscopy, it is concluded that the slow states are originated from the residual water or hydroxyl molecules in LPD-SiO₂. The LPD-SiO₂ is also applied to fabricate amorphous silicon (a-Si:H) thin film transistor (TFT) based on a new self-aligned process. The performance of this device is comparable to those of thin film transistors employed other kinds of SiO₂, i.e., thermal, plasma, vacuum evaporation, etc., as the gate insulator. The bias-stress measurement shows that the threshold voltage shift is dominated by charge trapping in the gate insulator     

Hydrogenated amorphous silicon thin-film transistor with a thingate insulator

Thinning the gate insulator in an hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) has been studied in a coplanar structure. The threshold voltage decreases with decreasing gate insulator thickness without changing the field effect mobility significantly. The reduction in the threshold voltage is due to the decrease in the charge traps in the SiN_x and in its film thickness. The coplanar a-Si:H TFT with a gate insulator thickness of 35 nm exhibited a field effect mobility of 0.45 cm²/Vs and a threshold voltage of 1.5 V. The thickness of the gate insulator can be decreased in the coplanar a-Si:H TFTs because of the planarized gate insulator     

Hydrogenated amorphous silicon thin-film transistor on plastic with an organic gate insulator

We developed a high-performance, hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) on plastic substrate using an organic gate insulator. The TFT with a silicon-nitride (SiN/sub x/) gate insulator exhibited a field-effect mobility of 0.3 cm/sup 2//Vs and a threshold voltage of 5 V. On the other hand, an a-Si:H TFT with an organic gate insulator of BCB (benzocyclobutene) has a field-effect mobility of 0.4 cm/sup 2//Vs and a threshold voltage of 0.7 V. The leakage currents through the gate insulator of an a-Si:H TFT with an organic gate insulator is about two orders of magnitude lower than that of an a-Si:H TFT with a SiN/sub x/ gate insulator.     

Device analysis for a-Si:H thin-film transistors with organicpassivation layer

Two dimensional device analysis has been performed to explain the experimental drain current-gate voltage (I_D-V_GS) characteristics of hydrogenated amorphous silicon thin-film transistors with various passivation layers. The shift of the I_D-V_GS curve in the negative direction and the increase of S-factor (the inverse of subthreshold slope in logarithmic I_D-V_GS curve) can be explained well by introducing positive fixed charges and defect states in the back interface region. It was found that the positive fixed charge and the defect density of a-Si:H TFT with an organic passivation layer are higher than those of conventional a-Si:H TFT with a silicon-nitride (SiN_x) passivation layer. The simulation shows that the front and back interfaces interact and this explains why the passivation affects the device performance such as V_th and S-factor in a-Si:H TFTs