Arrays of monocrystalline silicon micromirrors fabricated using CMOS compatible transfer bonding

In this paper, we present CMOS compatible fabrication of monocrystalline silicon micromirror arrays using membrane transfer bonding. To fabricate the micromirrors, a thin monocrystalline silicon device layer is transferred from a standard silicon-on-insulator (SOI) wafer to a target wafer (e.g., a CMOS wafer) using low-temperature adhesive wafer bonding. In this way, very flat, uniform and low-stress micromirror membranes made of monocrystalline silicon can be directly fabricated on top of CMOS circuits. The mirror fabrication does not contain any bond alignment between the wafers, thus, the mirror dimensions and alignment accuracies are only limited by the photolithographic steps. Micromirror arrays with 4/spl times/4 pixels and a pitch size of 16 /spl mu/m/spl times/16 /spl mu/m have been fabricated. The monocrystalline silicon micromirrors are 0.34 /spl mu/m thick and have feature sizes as small as 0.6 /spl mu/m. The distance between the addressing electrodes and the mirror membranes is 0.8 /spl mu/m. Torsional micromirror arrays are used as spatial light modulators, and have potential applications in projection display systems, pattern generators for maskless lithography systems, optical spectroscopy, and optical communication systems. In principle, the membrane transfer bonding technique can be applied for integration of CMOS circuits with any type of transducer that consists of membranes and that benefits from the use of high temperature annealed or monocrystalline materials. These types of devices include thermal infrared detectors, RF-MEMS devices, tuneable vertical cavity surface emitting lasers (VCSEL) and other optical transducers.     

Silicon–glass wafer bonding with silicon hydrophilic fusion bonding technology

Silicon–glass wafer bonding is realized with silicon hydrophilic fusion bonding technology. Tensile strength testing shows that the bonding strength is large enough for most applications of integrated circuits and transducers. The bonding strengths of 4 in. 525 μm thick #7740 glass–4 in. 525 μm thick silicon and of 1.5 in. 1000 μm thick #7740 glass–2 in. 380 μm thick silicon are larger than 9 MPa both with an annealing temperature of 450°C.     

Stamp-and-stick room-temperature bonding technique for microdevices

Multilayer MEMS and microfluidic designs using diverse materials demand separate fabrication of device components followed by assembly to make the final device. Structural and moving components, labile bio-molecules, fluids and temperature-sensitive materials place special restrictions on the bonding processes that can be used for assembly of MEMS devices. We describe a room temperature "stamp and stick (SAS)" transfer bonding technique for silicon, glass and nitride surfaces using a UV curable adhesive. Alternatively, poly(dimethylsiloxane) (PDMS) can also be used as the adhesive; this is particularly useful for bonding PDMS devices. A thin layer of adhesive is first spun on a flat wafer. This adhesive layer is then selectively transferred to the device chip from the wafer using a stamping process. The device chip can then be aligned and bonded to other chips/wafers. This bonding process is conformal and works even on surfaces with uneven topography. This aspect is especially relevant to microfluidics, where good sealing can be difficult to obtain with channels on uneven surfaces. Burst pressure tests suggest that wafer bonds using the UV curable adhesive could withstand pressures of 700 kPa (7 atmospheres); those with PDMS could withstand 200 to 700 kPa (2-7 atmospheres) depending on the geometry and configuration of the device.     

Wafer-level plasma activated bonding: new technology for MEMS fabrication

Manufacturing and integration of MEMS devices by wafer bonding often lead to problems generated by thermal properties of materials. These include alignment shifts, substrate warping and thin film stress. By limiting the thermal processing temperatures, thermal expansion differences between materials can be minimized in order to achieve stress-free, aligned substrates without warpage. Achieving wafer level bonding at low temperature employs a little magic and requires new technology development. The cornerstone of low temperature bonding is plasma activation. The plasma is chosen to compliment existing interface conditions and can result in conductive or insulating interfaces. A wide range of materials including semiconductors, glasses, quartz and even plastics respond favorably to plasma activated bonding. The annealing temperatures required to create permanent bonds are typically ranging from room temperature to 400°C for process times ranging from 15–30 min and up to 2–3 h. This new technique enables integration of various materials combinations coming from different production lines.     

Thermal isolation of high-temperature superconducting thin filmsusing silicon wafer bonding and micromachining

Using a new micromachining technology, thermally isolated thin films of high-temperature superconductor have been microfabricated. The intended application for these structures is in infrared bolometers. A silicon wafer bonding process produces a low thermal mass island of single-crystal silicon on a silicon nitride membrane which provides thermal isolation. The silicon can act as a seed for the epitaxial growth of YBa₂Cu₃O₇ on a yttria-stabilized zirconia buffer layer. This paper describes the overall concept of the thermally isolated device, and demonstrates that the micromachined structure can be fabricated with high-quality superconducting films     

Localized silicon fusion and eutectic bonding for MEMS fabricationand packaging

Silicon fusion and eutectic bonding processes based on the technique of localized heating have been successfully demonstrated. Phosphorus-doped polysilicon and gold films are applied separately in the silicon-to-glass fusion bonding and silicon-to-gold eutectic bonding experiments. These films are patterned as line-shape resistive heaters with widths of 5 or 7 μm for the purpose of heating and bonding. In the experiments, silicon-to-glass fusion bonding and silicon to gold eutectic bonding are successfully achieved at temperatures above 1000°C and 800°C, respectively, by applying 1-MPa contact pressure. Both bonding processes can achieve bonding strength comparable to the fracture toughness of bulk silicon in less than 5 min. Without using global heating furnaces, localized bonding process is conducted in the common environment of room temperature and atmospheric pressure. Although these processes are accomplished within a confined bonding region and under high temperature, the substrate temperature remains low. This new class of bonding scheme has potential applications for microelectromechanical systems fabrication and packaging that require low-temperature processing at the wafer level, excellent bonding strength, and hermetic sealing characteristics     

Low temperature wafer bonding for thin silicon film transfer

In this work, we investigate the low temperature (<200 °C) wafer bonding using wet chemical surface activation and we demonstrate high bonding strength sufficient to achieve the transfer of a thin silicon film of thickness less than 400 nm on top of another silicon wafer using spin-on-glass (SOG) film as an intermediate layer. The process developed is the first critical step that can enable three-dimensional (3D) integration and wafer level packaging of MEMS with electronic circuits.     

InP dies transferred onto silicon substrate for optical interconnects application

We bonded quantum well InP dies on a photonic layer transferred on silicon CMOS processed wafer using direct molecular bonding. This approach is suitable for new applications, viz., photonics on silicon, 3D packaging and integrated sensors. The chips are diced from a bulk substrate and bonded directly onto a silicon substrate without any organic nor metallic adhesive layer. A thin silicon dioxide layer can be added on both assembled surfaces to enhance bonding quality. After bonding, the dies can mechanically be thinned down to 20 μm and chemically etched. The InAsP quantum well stack of the InP dies keeps its optoelectronics features and performances after being transferred onto a silicon substrate.     

Micromachining of buried micro channels in silicon

A new method for the fabrication of micro structures for fluidic applications, such as channels, cavities, and connector holes in the bulk of silicon wafers, called buried channel technology (BCT), is presented in this paper. The micro structures are constructed by trench etching, coating of the sidewalls of the trench, removal of the coating at the bottom of the trench, and etching into the bulk of the silicon substrate. The structures can be sealed by deposition of a suitable layer that closes the trench. BCT is a process that can be used to fabricate complete micro channels in a single wafer with only one lithographic mask and processing on one side of the wafer, without the need for assembly and bonding. The process leaves a substrate surface with little topography, which easily allows further processing, such as the integration of electronic circuits or solid-state sensors. The essential features of the technology, as well as design rules and feasible process schemes, will be demonstrated on examples from the field of μ-fluidics     

MEMS packaging process by film transfer using an anti-adhesive layer

A low cost and low temperature thin film packaging process based on the transfer of an electroplated Nickel 3D cap is proposed. This process is based on adhesion control of a thick molded cap Ni film on the carrier wafer by using a plasma deposited fluorocarbon film, on mechanical debonding and on adhesive bonding of the microcaps on the host wafer with BCB sealing rings. Mechanical characterizations show that the transferred microcaps have a high stiffness, a low stress and a high adhesion. Because this process is simple and only involves a low temperature (250°C) heating of the host wafer, it is highly versatile and suitable for the encapsulation of micro and nano devices, circuits and systems elaborated on a large range of substrate materials.     

Low‐temperature poly‐Si TFT transferred onto plastic substrates by using surface free technology by laser ablation/annealing (SUFTLA®)

A novel technology that makes it possible to transfer electronic devices from an original substrate to another substrate is introduced. Because laser irradiation is utilized during the transfer process, this technology was named SUFTLA® (surface free technology by laser ablation/annealing). Low‐temperature poly‐Si TFTs first manufactured on a quartz substrate were transferred onto a PES substrate without any damage or characteristic degradation. A trial TFT‐LCD device with peripheral integrated driver circuits was also transferred onto the PES substrate and their operation was observed under typical conditions. These results indicate that the SUFTLA technology is one of the leading candidates for fine‐patterned high‐performance electronic‐device manufacturing on flexible substrate.     

A Capacitive Micromachined Ultrasonic Transducer Array for Minimally Invasive Medical Diagnosis

A capacitive micromachined ultrasonic transducer (CMUT) array for minimally invasive medical diagnosis has been developed. Unlike traditional ultrasonic transducers, which generally use a bulky piece of substrate, this transducer array was integrated on a 40--thick micromachined silicon substrate into a probe shape with a typical shank width of 50-80 and a shank length of 4-8 mm. For 1-D arrays, 24-96 CMUT devices were integrated on one such silicon probe and formed an accurately configured phase array. In addition to miniaturization, reduction of the substrate thickness also decreases the intertransducer crosstalk due to substrate Lamb waves. Due to its miniature size, this array can be placed or implanted close to the target tissue/organ and can perform high-resolution high-precision diagnosis and stimulation using high-frequency ultrasounds. The issue of conflict between resolution and penetration depth of ultrasonic diagnosis can therefore be resolved. A two-layer polysilicon surface micromachining process was used to fabricate this device. Suspended polysilicon membranes of diameters ranging from 20 to 90 and thicknesses from 1.0 to 2.5 were used to generate and detect ultrasounds of frequencies ranging from 1 to 10 MHz. B-mode imaging using this transducer array has been demonstrated.     

An electrohydrodynamic polarization micropump for electroniccooling

This paper presents the design, fabrication, and characterization of an innovative microcooling device for microelectronics applications. The device incorporates an active evaporative cooling surface, a polarization micropump, and temperature sensors into a single chip. The micropump provides the required pumping action to bring the working fluid to the evaporating surface, allowing the effective heat transfer coefficient through a thin-film evaporation/boiling process. The device is based on VLSI microfabrication technology, allowing the electrohydrodynamic (EHD) electrodes to be integrated directly onto the cooling surface. Since the EHD electrodes are fabricated using the same technology as the electronic systems themselves, the proposed microelectronic cooling system in the form of an integrated microchip is very suitable for mass production. The prototype devices demonstrated a maximum cooling capacity of 65 W/cm² with a corresponding pumping head of 250 Pa. The results of this investigation will assist in the development of future microcooling devices capable of operating at high power levels     

Selective Transfer Technology for Microdevice Distribution

We have developed a generic cost-efficient CMOS-compatible heterogeneous device integration method at wafer-scale level. This method enables the distribution of devices from one to numerous wafers using selective transfer technology. We have applied this method for the distribution of atomic force microscopy (AFM) cantilevers and successfully demonstrated the population of multiple wafers from one source wafer. The distribution function has been designed such as to populate 42 wafers with only one source wafer. This CMOS back-end-of-the-line compatible method is particularly suitable for microelectromechanical systems and integrated circuits. Electrical interconnects are compatible with this technology. We present the concept, the selective transfer method, including a laser ablation technique used for the transfer, as well as the process and results of the application for AFM cantilever distribution.     

现代微电子行业的新型湿法清洗工艺

随着半导体技术的不断发展,集成电路的线宽在不断减小,对硅抛光片表面质量的要求也越来越高,为使芯片上的器件功能正常．避免硅片制造中的沾污是绝对必要的。传统的RCA清洗方法已不能满足其需求。因此,必须发展新的清洗方法。本文对传统的RCA清洗方法进行了简单的介绍,在此基础上,介绍新发展的HF／O3清洗法,从而对450mm硅片清洗方法的未来发展方向进行了简单论述。     

Wafer- and piece-wise Si tip transfer technologies for applicationsin scanning probe microscopy

A novel tip transfer technology is proposed for applications in scanning probe microscopy (SPM). The technology is based on the concept of fabricating tips on an independent wafer and transferring them onto the target wafer. The transfer is also feasible on a full 4-in wafer scale. This is especially attractive for postprocessing CMOS wafers, e.g., for atomic force microscopy chips with integrated electronics. A yield of more than 90% has been achieved in a first experimental set-up. Moreover, a piece-wise tip transfer onto a free-standing cantilever is also shown. During this transfer, the tip is completely encapsulated in a resist post and, hence, protected against mechanical impact. This technology can be applied not only to SPM probe fabrication but also to create a new kind of MEMS device     

Packaging of a 3-axial piezoresistive force sensor with backside contacts

In this paper design aspects and challenging packaging solution of a monolithic 3D force sensor will be presented. The previously developed design and process flow (Vázsonyi et al. 123–124:620–626, 2005; Molnár et al. 90:40–43, 2012) were improved by an additional hybrid wafer bonding step of simultaneous anodic and metal bonding processes. This electrostatic force assisted metal bonding can ensure both the mechanical and the electrical integrity of the device. The applied novel process sequence can eliminate the need of a possible flip-chip bonding and chemical–mechanical polishing steps. The applied glass substrate improves the thermal isolation and thermo-mechanical stability of the integrated system considering the thermal expansion coefficients of the chosen glass material and the silicon (Si) only slightly differ minimizing the residual thermo-mechanical stress during the operation.     

Microfabricated Lamb wave device based on PZT sol-gel thin film formechanical transport of solid particles and liquids

The fabrication using silicon micromachining and characterization of an acoustic Lamb wave actuator is presented. The intended use of the device is for mass transport and sensor applications. The device consists of dual interdigitated transducers patterned on a thin-film composite membrane of silicon nitride, platinum, and a sol-gel-derived piezoelectric ceramic (PZT) thin film. The acoustic properties of the device are presented along with preliminary applications to mechanical transport and liquid delivery systems. Improved acoustic signals and improved mass transport are achieved with PZT over present Lamb wave devices utilizing ZnO or AlN as the piezoelectric transducer     

现代微电子行业的新型湿法清洗工艺

随着半导体技术的不断发展,集成电路的线宽在不断减小,对硅抛光片表面质量的要求也越来越高,为使芯片上的器件功能正常,避免硅片制造中的沾污是绝对必要的。传统的RCA清洗方法已不能满足其需求。因此,必须发展新的清洗方法。本文对传统的RCA清洗方法进行了简单的介绍,在此基础上,介绍新发展的HF/O3清洗法,从而对450mm硅片清洗方法的未来发展方向进行了简单论述。     

Integration of Trench-Isolated Through-Wafer Interconnects with 2D Capacitive Micromachined Ultrasonic Transducer Arrays

This paper presents a method to provide electrical connection to a 2D capacitive micromachined ultrasonic transducer (CMUT) array. The interconnects are processed after the CMUTs are fabricated on the front side of a silicon wafer. Connections to array elements are made from the back side of the substrate via highly conductive silicon pillars that result from a deep reactive ion etching (DRIE) process. Flip-chip bonding is used to integrate the CMUT array with an integrated circuit (IC) that comprises the front-end circuits for the transducer and provides mechanical support for the trench-isolated array elements. Design, fabrication process and characterization results are presented. The advantages when compared to other through-wafer interconnect techniques are discussed.