A Self-Consistent Full 3-D Real-Space NEGF Simulator for Studying Nonperturbative Effects in Nano-MOSFETs

In this paper, we present a full 3-D real-space quantum-transport simulator based on the Green's function formalism developed to study nonperturbative effects in ballistic nanotransistors. The nonequilibrium Green function (NEGF) equations in the effective mass approximation are discretized using the control-volume approach and solved self-consistently with the Poisson equation in order to obtain the electron and current densities. An efficient recursive algorithm is used in order to avoid the computation of the full Green function matrix. This algorithm, and the parallelization scheme used for the energy cycle, allow us to compute very efficiently the current-voltage characteristic without the simplifying assumptions often used in other quantum-transport simulations. We have applied our simulator to study the effect of surface roughness and stray charge on the I_D-V_G characteristic of a 6-nm Si-nanowire transistor. The results highlight the distinctly 3-D character of the electron transport, which cannot be accurately captured by using 1-D and 2-D NEGF simulations, or 3-D mode-space approximations.     

Hot-carrier-induced degradation of LDD polysilicon TFTs

In order to improve the stability of polysilicon thin-film transistors (TFTs) several drain junction architectures have been proposed. In this paper, the hot-carrier (HC) related stability of the lightly doped drain (LDD) TFT architecture is analyzed by using an iterative algorithm that relates the HC induced damage to the carrier injection across the device interfaces with gate and substrate oxide. The resulting creation of interface states and trapped charge is taken into account by using a system of rate equations that implements mathematically the Lais two step model, in which the generation of interface states is attributed to the trapping of hot-holes by centres into the oxide followed by the recombination with hot electrons. The rate equations are solved self-consistently with the aid of a device simulation program. By successive iterations, the time evolution of the interface state density and positive trapped charge distribution has been reconstructed, and the electrical characteristics calculated with this model are in good agreement with experimental data. This algorithm represent an improvement of an already proposed degradation model, in which the interface states formation dynamics is accounted by using a phenomenological approach. The present model has been applied to reproduce the degradation pattern of LDD TFTs and it is found that generation of interface states proceed almost symmetrically on the front and back device interfaces, starting from the points in which the transverse electric field peaks, and moving toward the drain side of the device. The final interface states distribution determines a sort of "bottleneck" in the active layer carrier density, that can explain the sensitivity to HC induced damage of both transfer and output characteristics.     

Gate oxide thickness dependence of edge charge trapping in NMOS transistors caused by charge injection under constant-current stress

This brief reports a study of charge injection-induced edge charge trapping in the gate oxide overlapping the drain extension which has an impact on the drain leakage current. The edge charge trapping is determined for the gate oxide thickness of 6.5, 3.9, and 2.0 nm by using a simple approach to analyze the change of the band-to-band tunneling current measured with a three-terminal gate-controlled-diode configuration. The edge charge trapping has a strong dependence on the gate oxide thickness, and it is different from the charge trapping in the oxide over the channel. A plausible explanation for both the oxide thickness dependence of the edge charge trapping and the difference between the edge charge trapping and the charge trapping over the channel is presented.     

Simulation of substrate hot-electron injection

Electron trapping in thin oxide and interface state generation has been investigated using a constant-current stressing technique. Assuming finite-temperature Fowler-Nordheim tunneling, semiempirical simulations of voltage versus stress time behavior were obtained for an MOS diode. A trapped charge model was used to simulate voltage versus stress-time behavior. The comparison between measurement and simulation results yields information about trapped charges in the oxide and at the oxide-substrate interface. The model can serve as the basis for improved understanding of the more complex phenomenon of channel hot-carrier injection in MOS transistors     

A step-accurate model for the trapping and release of charge carriers suitable for the transient simulation of analog circuits

A compact add-on model is proposed to simulate the mechanism of charge trapping and release (detrapping) and its effect on the threshold voltage of MOSFET devices. The model uses implicit algebraic differential equations compatible with transient analysis in SPICE. It also shares the accuracy level of the transient analysis. A micro-model approach is used, and each trap is treated by a two-state Markov process. The normalization of trap behavior can be enabled or disabled, so that the designer can compare average trap behavior to the result of repeated Monte-Carlo simulations of a circuit. In this manner, the model can compromise between device-level modeling and circuit-level modeling. Unlike models geared towards digital circuit design, the trapping and release rates need not be constant during electrical stress. The trapping and release rates are a function of time, as they depend on the circuit state-space equations. An operational amplifier is analyzed using the new model, and the proposed approach is compared with the state of the art.     

Two-dimensional simulation for resonant tunneling transistor

A new two-dimensional device simulation for the resonant tunneling transistor is presented. In the simulation, the one-dimensional Schrodinger equation is solved for the intrinsic area of the transistor and the conventional two-dimensional drift-diffusion equations are solved for the extrinsic part. Both equations are coupled with the carrier generation-recombination term in the drift-diffusion equations. In addition, the Poisson equation is also solved self-consistently with them to take the charge distribution effect into account. The two-dimensional simulator has been successfully applied to the analysis of a resonant tunneling transistor and it was found that the current-voltage characteristics sensitively depend on the base resistance. This means that a two-dimensional treatment of the voltage drop in the base region is essential for an accurate simulation     

热载流子应力下超薄栅pMOS器件氧化层陷阱电荷的表征

利用电荷泵技术研究了4nm pMOSFET的热载流子应力下氧化层陷阱电荷的产生行为.首先,对于不同沟道长度下的热载流子退化,通过直接的实验证据,发现空穴陷阱俘获特性与应力时间呈对数关系.然后对不同应力电压、不同沟道长度下氧化层陷阱电荷(包括空穴和电子陷阱俘获)的产生做了进一步的分析.发现对于pMOSFET的热载流子退化,氧化层陷阱电荷产生分两步过程:在较短的应力初期,电子陷阱俘获是主要机制;而随着应力时间增加,空穴陷阱俘获作用逐渐显著,最后主导了氧化层陷阱电荷的产生.     

热载流子应力下超薄栅p MOS器件氧化层陷阱电荷的表征

利用电荷泵技术研究了 4nmpMOSFET的热载流子应力下氧化层陷阱电荷的产生行为 .首先 ,对于不同沟道长度下的热载流子退化 ,通过直接的实验证据 ,发现空穴陷阱俘获特性与应力时间呈对数关系 .然后对不同应力电压、不同沟道长度下氧化层陷阱电荷 (包括空穴和电子陷阱俘获 )的产生做了进一步的分析 .发现对于 pMOSFET的热载流子退化 ,氧化层陷阱电荷产生分两步过程 :在较短的应力初期 ,电子陷阱俘获是主要机制 ;而随着应力时间增加 ,空穴陷阱俘获作用逐渐显著 ,最后主导了氧化层陷阱电荷的产生.     

Walk-out phenomena in 6H-SiC mesa diodes with SiO2/Si3N4 passivation and charge trapping in dry and wet oxides on N-type 6H-SiC

The drift or “walk-out” of the breakdown voltage in 6H-SiC mesa diodes passivated by a double layer of 1000 Å SiO₂ and 3000 Å Si₃N₄ was studied and related to the charge trapping in the oxide. The first-order trapping kinetics using four distinct electron traps with trapping cross-sections in the range 10⁻¹⁶ to 10⁻¹⁹ cm² were found to best describe the breakdown voltage drift curves. The wet oxide trapping cross-sections are 2 to 10 times larger compared to the dry oxide ones, resulting in about one order of magnitude faster charging of the traps. No significant differences in the amount of drift and saturation level of breakdown voltage were found between the different passivations. The influence of UV illumination, supplied by a HeCd laser with wavelength 325 nm, on the walk-out characteristics and on the reverse current was also investigated. The build-up of the surface states was observed in wet oxide under UV illumination and DC stress. The results are consistent with the coexistence of large concentrations of positive charge and acceptor type deep interface electron traps. The walk-out is a result of the acceptor states being filled by hot electrons supplied by the mechanism of avalanche injection. The suitability of the walk-out measurements as a tool for characterisation of the charge trapping properties of the passivation is demonstrated.     

Novel SONOS – type nonvolatile memory device with stacked tunneling and charge trapping layers

Operation properties of polysilicon–oxide–nitride–oxide–silicon (SONOS)-type nonvolatile semiconductor memory (NVM) devices with stacked tunneling and charge trapping layers were investigated in this work. Clear enhancement on operation speed and satisfactory retention of NVM device were achieved by adopting stacked tunneling oxide. Enhancement on programming speed but degradation on erasing operation was observed for device with stacked charge trapping layer. Finally, operating characteristics of devices with stacked tunneling oxide, stacked charge trapping layer, and combining both stacked tunneling oxide and charge trapping layer were compared and discussed.     

Separation of hot-carrier-induced interface trap creation and oxidecharge trapping in PMOSFETs studied by hydrogen/deuterium isotope effect

By using the hydrogen/deuterium isotope effect, we propose a new technique to separate and quantify the effects of hot-carrier-induced interface trap creation and oxide charge trapping on the degradation in PMOSFETs. In addition to the well-known hot-electron-induced-punchthrough (HEIP) mechanism, we find that two additional mechanisms, namely, interface trap creation and hole trapping in the oxide, also play important roles in PMOSFET degradation. The degradation mechanisms are highly dependent on stress conditions. For low gate voltage V_gs stress, HEIP is found to dominate the shift of threshold voltage V_t. When V_gs increases to a moderate value, the V_t shift can be fully dominated by interface trap creation. Hole injection and trapping into the oxide occurs when V_gs is increased further to V_gs=V_ds. For the first time, the effects of interface trap creation and oxide charge trapping on the V_t shift are quantified by the proposed technique     

Square-Root Domain Operational Simulation of LC Ladder Elliptic Filters

A technique for designing square-root domain elliptic filters that simulate the operation of the corresponding LC ladder prototypes is introduced in this paper. This is achieved by manipulating the equations that describe the operation of differentiation in such a way that only lossless integrator and weighted summation blocks are needed. The derived signal flow graph (SFG) is transposed to the corresponding one in the square-root domain using an appropriate set of operators in order to preserve the linear operation of the whole filter. In order to demonstrate the validity of the proposed technique, a third-order elliptic lowpass filter was simulated and its behavior was evaluated using an HSPICE simulator.     

Simplified 0.35-μm flash EEPROM process using high-temperatureoxide (HTO) deposited by LPCVD as interpoly dielectrics and peripheraltransistors gate oxide

A simplified flash EEPROM process was developed using high-temperature LPCVD oxide both as flash cells interpoly dielectrics and as peripheral transistors gate oxide (decoding logic). An O₂ anneal at 850°C lowers charge trapping and interface trap density induced by Fowler-Nordheim injection. However, electron trapping remains slightly higher than with dry thermal oxide. Similar memory charge loss and write-erase endurance are obtained as for ONO-insulated cells. HTO thus proves to have the required quality and reliability to be used in flash EEPROMs     

Charge-control modeling of power bipolar junction transistors

This paper describes an improved lumped circuit model of power bipolar junction transistors (BJTs) that can predict the turn-off fall time to a greater accuracy than currently available models. Though the existing models simulate the storage time and delay time to a good accuracy, the fall time performance is neglected. This is because the existing models do not account for the charge decay due to recombination. The model presented in this paper is based on the charge dynamics of the device. The charge dynamics are explained in detail using simulation results from an advanced two-dimensional (2-D) device and circuit simulator. Based on a physical understanding of the charge dynamics, this model is implemented to incorporate the charge decay due to recombination to account for the current tail during turn-off. The lumped-circuit model is implemented in PSPICE using the existing quasisaturation model along with controlled sources. To validate the model, the device was subjected to hard- as well as soft-switching renditions (zero current switching and zero voltage switching). The modeled results are observed to have a good match with measured results     

Analysis of the trapping characteristics of silicon dioxide after Fowler-Nordheim degradation

An analysis of the trapping characteristics of silicon dioxide (SiO₂) subjected to Fowler-Nordheim degradation is presented. Based on the Fowler-Nordheim threshold and flat-band voltage shifts, the total charge trapped in the oxide (Q_ox) and the centroid ( ) of the trapped charge distribution is extracted while taking into account the charge stored in the fast Si-SiO₂ interface states as a function of the Fowler-Nordheim injection dose. Using qausi-first-order kinetic equations the capture cross sections (σ_i) and densities (N_tⁱ) of the oxide bulk traps are also determined.     

高压pLEDMOS器件在不同应力条件下导通电阻的衰退及改进方法

实验测试结果揭示高压pLEDMOS器件在不同的应力条件下,导通电阻的衰退结果不同,半导体器件专业软件MEDICI模拟结果表明Si/SiO2表面的陷阱产生以及热电子的注入和俘获导致了高压pLEDMOS器件在不同的应力条件下产生不同的导通电阻衰退.文中同时提出了一种改进方法:用场氧代替厚栅氧作为高压pLEDMoS器件的栅氧,MEDICI模拟结果显示该方法可以明显降低/减缓高压pLEDMOS导通电阻的衰退.     

三维圆柱形电荷俘获存储器件的继续微缩对其性能的影响

本文详细地研究了关键尺寸的继续微缩对三维圆柱形无结型电荷俘获存储器器件性能的影响。通过Sentaurus三维器件仿真器,我们对器件性能的主要评价指标进行了系统地研究,包括编程擦除速度和高温下的纵向电荷损失及横向电荷扩散。沟道半径的继续微缩有利于操作速度的提升,但使得纵向电荷损失, 尤其是通过阻挡层的纵向电荷损失,变得越来越严重。栅极长度的继续微缩在降低操作速度的同时将导致俘获电荷有更为严重的横向扩散。栅间长度的继续微缩对于邻近器件之间的相互干扰有决定性作用,对于特定的工作温度及条件其值需谨慎优化。此外,栅堆栈的形状也是影响电荷横向扩散特性的重要因素。研究结果为高密度及高可靠性三维集成优化提供了指导作用。     

Properties of the MZOS surface wave convolver configuration

The MZOS (metal-zinc oxide-silicon dioxide-silicon) structure is investigated in order to provide a phenomenological understanding of the charge transfer and trapping properties of the zinc oxide layer. Results of fast-ramp measurements of capacitance versus voltage are presented, and on the basis of these results, some biasing and operating procedures are suggested to make effective use of the memory capabilities of this configuration or to avoid unwanted memory effects. A technique for optical imaging is described which offers several advantages over other surface wave imaging techniques. Finally, some potential applications are mentioned.     

Optimization of hafnium oxide for use in nanoparticle memories

In this work we investigate the dielectric properties of hafnium oxide deposited by RF magnetron sputtering with the purpose to implement it as control oxide for non-volatile memories based on metallic nanoparticles as charge storage centers. The influence of deposition temperature, ambient and post-deposition annealing onto the trapping properties of hafnium oxide, deposited over a tunneling silicon oxide layer, will be discussed and optimized conditions under which no charge trapping is observed into the dielectric stack will be presented.