A monolithic fully-integrated vacuum-sealed CMOS pressure sensor

This paper presents an integrated multi-transducer capacitive barometric pressure sensor that is vacuum-sealed at wafer level. The interface circuitry is integrated directly within the sealed reference cavity, making the device immune to parasitic environmental effects. The overall device process merges CMOS circuitry with a dissolved-wafer transducer process and is compatible with bulk- and surface-micromachined transducers. The process employs chemical-mechanical polishing (CMP), anodic bonding, and hermetic lead transfers. The sensor achieves 25 mtorr resolution and is suitable for low-cost packaging. It is composed of a programmable switched-capacitor (SC) readout circuit, five segmented-range pressure transducers, and a reference capacitor, all integrated on a 6.5×7.5 mm² die using 3 μm features     

A time-to-digital-converter-based CMOS smart temperature sensor

A time-to-digital-converter-based CMOS smart temperature sensor without a voltage/current analog-to-digital converter (ADC) or bandgap reference is proposed for high-accuracy portable applications. Conventional smart temperature sensors rely on voltage/current ADCs for digital output code conversion. For the purpose of cost reduction and power savings, the proposed smart temperature sensor first generates a pulse with a width proportional to the measured temperature. Then, a cyclic time-to-digital converter is utilized to convert the pulse into a corresponding digital code. The test chips have an extremely small area of 0.175 mm/sup 2/ and were fabricated in the TSMC CMOS 0.35-/spl mu/m 2P4M process. Due to the excellent linearity of the digital output, the achieved measurement error is merely -0.7/spl sim/+0.9/spl deg/C after two point calibration, but without any curvature correction or dynamic offset cancellation. The effective resolution is better than 0.16/spl deg/C, and the power consumption is under 10 /spl mu/W at a sample rate of 2 samples/s.     

一种应用于RFID的低功耗温度传感器

This paper presents the design and implement of a CMOS smart temperature sensor,which consists of a low power analog front-end and a 12-bit low-power successive approximation register(SAR) analog-to-digital converter(ADC).The analog front-end generates a proportional-to-absolute-temperature(PTAT) voltage with MOSFET circuits operating in the sub-threshold region.A reference voltage is also generated and optimized in order to minimize the temperature error and the 12-bit SAR ADC is used to digitize the PTAT voltage.Using 0.18 m CMOS technology,measurement results show that the temperature error is0.69/C0.85 °C after one-point calibration over a temperature range of40 to 100 °C.Under a conversion speed of 1K samples/s,the power consumption is only 2.02 W while the chip area is 230225 m2,and it is suitable for RFID application.     

A dynamically reconfigurable interconnect for array processors

Reconfigurability of processor arrays is important due to two reasons (1) to efficiently execute different algorithms and (2) to isolate faulty processors. An array processor that is reconfigurable by the user any number of times to yield a different topology or to isolate faults is envisaged in this paper. The system has a host or controller that broadcasts a command to the interconnect to configure itself into a particular fashion. The interconnect uses static-RAM programming technology and can be programmed to different configurations by sending a different set of bits to the configuration random access memory (RAM) in the interconnect. We present three designs reconfigurable into array, ring, mesh, or Illiac mesh topologies. The first design provides no redundancy or fault tolerance. The second design is capable of graceful degradation by bypassing faulty elements. The third design is capable of graceful degradation by rerouting. The details of the interconnect and the configuration RAM contents for typical configurations are illustrated. It is seen that reconfigurable interconnect results in a highly reconfigurable or polymorphic computer     

A monolithic capacitive pressure sensor with pulse-period output

A new microminiature monolithic capacitive pressure transducer (CPT I) is 20 times more sensitive than piezoresistive strain-gauge pressure transducers, requires one percent of the power, and can be batch fabricated through current integrated circuit technology. A second device (CPT II) incorporates bipolar signal-processing electronics on the same silicon chip to produce a low-duty-cycle pulse-mode output with period related to pressure. This output format helps to re-solve the problem of shunting between leads, which is one of the principal causes of long-term drift in piezoresistive transducers designed for implantable medical applications. Because this device uses capacitance change as a transductional mechanism rather than piezo-resistivity, it is not susceptible to drift caused by temperature variations in the piezoresistive coefficient. Optimization for totally implantable biomedical applications places special emphasis on small size, high sensitivity, improved long-term baseline stability, and greatly reduced power consumption. These properties are also important for a wide range of pressure-sensing applications-from automotive to general industrial use.     

A simulation tool for dynamically reconfigurable field programmablegate arrays

The emergence of static memory-based field programmable gate arrays (FPGAs) that are capable of being dynamically reconfigured, i.e., partially reconfigured while active, has initiated research into new methods of digital systems synthesis. At present, however, there are virtually no specific CAD tools to support the design and investigation of digital systems using dynamic reconfiguration. This paper reports on an investigation of new CAD tools and the development of a new simulation technique, called dynamic circuit switching (DCS), for dynamically reconfigurable systems. The principles of DCS are presented and examples of its application are described     

Simulations for thermal warpage and pressure nonlinearity of monolithic CMOS pressure sensors

The operation function of a piezoresistive pressure sensor utilizes a voltage output to detect the magnitude of pressure. The basic design concept for monolithic pressure sensors is to fabricate a standard submicron CMOS process with appropriate modifications to integrate on-chip signal conditioning circuits with anisotropic-etched piezoresistive sensing elements. In this study, thermal stress simulations with applied pressure loadings are used to estimate the electromechanical behavior of a new monolithic sensing element concept design. The major tasks are to predict the ripple deformation of a silicon diaphragm due to the thermal residual stresses from multiple passivation layers and estimate the pressure nonlinearities on the transducer. More detailed approaches with design and performance concerns are also discussed.     

CMOS integrated silicon pressure sensor

The sensor described includes a four-arm piezoresistance bridge circuit, an amplifier, and a bridge excitation circuit. This circuit is used to stabilize changes in sensitivity due to variations in temperature and supply voltage. The sensor was fabricated using a self-aligned double-poly Si gate p-well CMOS process combined with an electrochemical etch-stop technique using N/SUB 2/H/SUB 4/-H/SUB 2/O anisotropic etchant for the thin-square diaphragm formation. The silicon wafer was electrostatically adhered to a glass plate to minimize thermally induced stress. Less than a /spl plusmn/0.5% sensitivity shift and less than a /spl plusmn/5-mV offset shift were obtained in the 0-70/spl deg/C range, with a 1-V/kg/cm/SUP 2/ pressure sensitivity. By using a novel excitation technique, a sensitivity change of less than /spl plusmn/1.5% under a /spl plusmn/10% supply voltage variation was also achieved.     

A programmable intraocular CMOS pressure sensor system implant

We present a programmable intraocular pressure sensor system implant integrated on a single CMOS chip. It contains an on-chip micromechanical pressure sensor array, a temperature sensor, readout and calibration electronics, a μC-based digital control unit, and an RF transponder. The transponder enables wireless data transmission and wireless power reception, thus making batteryless operation feasible. The chip has been fabricated in a 1.2-μm n-well CMOS process complemented by additional processing steps     

一种基于标准CMOS工艺的新型单片集成紫外图像传感器

我们提出了一种基于标准CMOS工艺的浮栅紫外图像传感器。传感器单元是由一个非常紧凑的紫外线灵敏器件构成。整个紫外图像传感器有一CMOS像素单元阵列、高压开关、读出电路和数字控制等部分组成。在一0.18μm标准工艺上实现了1个1616的图像传感器芯片。我们对传感器单元和阵列进行了测试,测试结果表明传感器的灵敏度为0.072 V/(mJ/cm2),并且可以获得紫外图像。此紫外图像传感器适合于大规模集成的生物医药和太空探测等领域。     

A novel monolithic ultraviolet image sensor based on a standard CMOS process

We present a monolithic ultraviolet(UV) image sensor based on a standard CMOS process.A compact UV sensitive device structure is designed as a pixel for the image sensor.This UV image sensor consists of a CMOS pixel array,high-voltage switches,a readout circuit and a digital control circuit.A 16×16 image sensor prototype chip is implemented in a 0.18μm standard CMOS logic process.The pixel and image sensor were measured. Experimental results demonstrate that the image sensor has a high sensitivity of 0.072 V/(mJ/cm~2) and can capture a UV image.It is suitable for large-scale monolithic bio-medical and space applications.     

A 256×256 pixel smart CMOS image sensor for line-based stereovision applications

This paper presents a 256×256 pixel smart CMOS image sensor for line based vision applications. By combining the edge-based analog processing technique with an active pixel array, a dense and fast on-chip analog image processing has been achieved. The on-chip processing unit includes (1) an analog histogram equalizer, (2) a programmable recursive Gaussian filter, (3) a spatio-temporal differentiator, and (4) a local extrema extractor. An electronic shutter is applied to the active pixel sensor array in order to adapt the exposure time as a function of global illumination. The on-chip histogram equalizer extends the image into a constant and optimal range for all the following processing operators and gives a stable and predictable precision of the analog processing. A prototype chip has been designed and fabricated in a standard 0.8-μm CMOS process with double poly and double metal, giving a pixel pitch of 20 μm and die size of 7×7 mm². A line processing time is compatible with TV line scan period. The worst case power consumption measures 40 mA at 5 V     

A CMOS monolithic amplifier for cardiac EIT applications

Analog Integrated Circuits and Signal Processing - This paper presents a low-noise amplifier (LNA) with superior linearity for ultra-wideband (UWB) purposes. Linearity is a significant parameter...     

An ultraminiature CMOS pressure sensor for a multiplexedcardiovascular catheter

A multiplexed ultraminiature pressure sensor designed for use in a cardiovascular catheter is described. The sensor operates from only two loads, which are shared by two sensors per catheter. The sensing chip is 350 μm wide by 1.4 mm long by 100 μm thick. CMOS readout circuitry at the sensing site converts applied pressure to a frequency variation in the supply current, which is detected at the end of the catheter by a microprocessor-controlled interface. The nominal pressure sensitivity is 2 kHz/fF about a zero-pressure output frequency of 2.7 MHz. This on-site circuitry contains two reference capacitors which allow external compensation for nonlinearity and temperature sensitivity and has an idle-state power dissipation of less than 50 μW. With the transducer sealed at ambient pressure, the device can resolve pressure variations of about 3 mmHg, while vacuum-sealed devices do considerably better and should permit <2 mmHg resolution in practical systems     

HW/SW codesign techniques for dynamically reconfigurable architectures

Hardware/software (HW/SW) codesign and reconfigurable computing are commonly used methodologies for digital-systems design. However, no previous work has been carried out in order to define a HW/SW codesign methodology with dynamic scheduling for run-time reconfigurable architectures. In addition, all previous approaches to reconfigurable computing multicontext scheduling are based on static-scheduling techniques. In this paper, we present three main contributions: 1) a novel HW/SW codesign methodology with dynamic scheduling for discrete event systems using dynamically reconfigurable architectures; 2) a new dynamic approach to reconfigurable computing multicontext scheduling; and 3) a HW/SW partitioning algorithm for dynamically reconfigurable architectures. We have developed a whole codesign framework, where we have applied our methodology and algorithms to the case study of software acceleration. An exhaustive study has been carried out, and the obtained results demonstrate the benefits of our approach.     

A reconfigurable ATM switch fabric for fault tolerance and trafficbalancing

A large-scale asynchronous transfer mode (ATM) switch fabric that can be constructed with currently feasible technology is proposed. Based on analysis of the technology, it is found that module interconnection becomes the bottleneck for a large fast packet switch. Fault tolerance for the switch is achieved by dynamic reconfiguration of the module interconnection network. The design improves system reliability with relatively low hardware overhead. An abstract model of the replacement problem for the design is presented, and the problem is transformed into a well-known assignment problem. The maximum fault tolerance is found, and a fast replacement algorithm is given. The reconfiguration capability can also be used to ameliorate imbalanced traffic flows. The authors formulate this traffic flow assignment problem for the switch fabric and show that the problem is NP-hard. A simple heuristic algorithm is proposed, and an example is given     

Efficient metrics and high-level synthesis for dynamically reconfigurable logic

The increase in complexity of programmable hardware platforms results in the need to develop efficient high-level synthesis (HLS) tools since it allows more efficient exploration of the design space while predicting the effects of technology specific tools on the design space. Much of the previous works however neglect the delay of interconnects (e.g. multiplexer) which can indeed contribute heavily on the overall performance of the design. In addition, in the case of dynamic reconfigurable logic (DRL) circuits, unless an appropriate design methodology is followed, large number of configurable logic blocks (CLBs) could be used for communication between contexts, rather than for implementing functional units (FUs). The aim of this paper is to present a new technique to perform interconnect-sensitive synthesis, targeting dynamic reconfigurable circuits. Further, the proposed technique exploits multiple hardware contexts to achieve efficient designs. Experimental results on several benchmarks, which have been done on our DRL LSI circuit (Meribout, 2000 and Motomura, 1997), demonstrate that by jointly optimizing the interconnect, communication, and function-unit cost, higher quality designs than other previous techniques (e.g. force-directed scheduling) can be achieved.     

A dynamically reconfigurable NRTI switched-capacitor-based hybrid DC-DC converter suitable for embedded applications

In this paper, a dynamically reconfigurable, Non-overlap Rotational Time Interleaved (NRTI) switched capacitor (S-C) DC-DC converter is presented. Its S-C module is reconfigurable to generate three different fractions (viz., 1/3, 1/2 and 2/3) of its input supply (Vdd). This maintains good power efficiency while its output voltage gets adjusted over a large range. In addition, a load-current-sensing circuit is integrated within it to dynamically reconfigure the S-C module based on the required driving capability. This feature enables to extend load current range to higher limit and at the same time improves the power efficiency in low load current regime. The S-C module is integrated with a current control loop for load and line regulation.The proposed architecture is simulated in a 0.18 μm CMOS process using dual oxide transistors to demonstrate the efficacy of the proposed topology. The input supply voltage is 3.3 V and the regulated output range is 0.8-1.6 V. Total flying capacitance is 330 pF and the load capacitor value is 50 pF. For an output of 1.35 V, its power efficiency is maintained above 50% over a load current range of 4 -17.6 mA with a peak of 66% at 9 mA. Throughout this current range the output voltage ripple remains within 12 mV.     

A monolithic 200-V CMOS analog switch

A new high-voltage CMOS technology is described which can increase the operating voltage of these circuits to more than 200 V. This represents approximately an order of magnitude improvement over present-day commercially available CMOS devices. The technology is straightforward to implement and uses n-channel MOS transistors and high-voltage p-channel devices. As an example of the capability of the technology, a monolithic quad CMOS analog switch has been fabricated which can handle 200-V, 0.3-A analog signals, with a dynamic range in excess of 150 dB.     

A monolithic CMOS 20-b analog-to-digital converter

The authors present a monolithic 20-b analog-to-digital converter (ADC) based on an oversampling feedback architecture. The converter consists of a time-continuous integrator at the input, a pulsewidth modulator in the forward branch of the loop (corresponding to a 10-b ADC), and a 1-b DAC (digital-to-analog converter) to generate the feedback voltage. The digital evaluation is carried out with a uniformly weighted rectangular window filter. The circuit is implemented in a standard 2-μm CMOS n-well process and requires 14 mm² of silicon, including the pads. Measurement results are presented that demonstrate the feasibility of this architecture for 20-b accuracy. The complete circuit has a power consumption of 6.7 mW