Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package

Microvias of 50 μm diameter in a Si chip were filled with Zn or Sn-Zn to form through-silicon vias by means of an electroplating/reflow process or a dipping method. In the case of the electroplating/reflow process, Zn was electroplated on a Cu seed layer in via holes, and a reflow was then performed to fill the via holes with the electroplated Zn. In the case of the dipping method, Zn via-filling and Sn-Zn via-filling were performed by dipping a via hole specimen into a molten bath of Zn or Sn-Zn. A filling pressure greater than 3 MPa during the via-filling is essential for ensuring that the via holes are completely filled with Zn or Sn-Zn and for preventing voids from being trapped in the vias. The melting temperature and electrical conductivity of the Sn-Zn alloys increases almost linearly with the content of Zn, implying that the thermal and electrical properties of the Sn-Zn vias can be easily controlled by varying the composition of the Sn-Zn vias. A chip-stack specimen was fabricated by flip-chip bonding of three chips with Zn vias.     

Effect of Migration and Condensation of Pre-existing Voids on Increase in Bump Resistance of Flip Chips on Flexible Substrates during Electromigration

In Pb-free solder joints formed by reflowing a bump of solder paste, voids are formed within the solder due to the residue of flux in the reflow process. These voids migrate toward the cathode contact during electromigration under current stressing. Accompanying the electromigration, resistance jumps of a few 100 mΩ were observed. It was postulated that a jump occurs when a void touches the cathode contact. This study investigated the effect of the void migration and condensation on the change in bump resistance using three-dimensional (3D) simulations and finite element analysis. It was found that there was negligible change in bump resistance during void migration towards the high-current-density region before touching the cathode contact opening. When a small void condensed on the contact opening and depleted 18.4% of the area, the bump resistance increased only 0.4 mΩ. Even when a large void depleted 81.6% of the opening, the increase in bump resistance was 3.3 mΩ. These values are approximately two orders of magnitude smaller than those reported in the literature for the change in resistance due to void migration in flip chips on flexible substrates. We conclude that the reported change in resistance was most likely that of the Al or Cu interconnection in the flip-chip samples.     

Contact Resistance of Flip-Chip Joints in Wearable Electronic Textiles

Flip-chip bonding to a Cu lead frame transferred to a fabric was achieved by use of a non-conducting adhesive. Average contact resistance of the flip-chip joints was evaluated on variation of the Cu and Sn thickness of Cu/Sn bumps of size 150 × 220 μm². The total thickness of the Cu/Sn bumps was fixed at 15 μm. The average contact resistance of the flip-chip joints on the fabric was 5.4–10.8 mΩ, depending on the Sn thickness of the Cu/Sn bumps; this was lower than for flip-chip joints on a rigid Si substrate (15.6–26.5 mΩ). The average contact resistance of flip-chip joints on the fabric decreased from 10.8 mΩ to 5.5 mΩ when the chip–bump configuration was changed from 15-μm-thick Sn to 7-μm-thick Cu/8-μm-thick Sn. The contact resistance of flip-chip joints bonded with the 7-μm-thick Cu/8-μm-thick Sn bumps remained below 10 mΩ for up to 750 h in the 85°C/85% relative humidity test and even decreased to below 4 mΩ in the storage test at 125°C for up to 1000 h.     

A Study on the Thermal Reliability of Cu/SnAg Double-Bump Flip-Chip Assemblies on Organic Substrates

The Cu/SnAg double-bump structure is a promising candidate for fine-pitch flip-chip applications. In this study, the interfacial reactions of Cu (60 μm)/SnAg (20 μm) double-bump flip chip assemblies with a 100 μm pitch were investigated. Two types of thermal treatments, multiple reflows and thermal aging, were performed to evaluate the thermal reliability of Cu/SnAg flip-chip assemblies on organic printed circuit boards (PCBs). After these thermal treatments, the resulting intermetallic compounds (IMCs) were identified with scanning electron microscopy (SEM), and the contact resistance was measured using a daisy-chain and a four-point Kelvin structure. Several types of intermetallic compounds form at the Cu column/SnAg solder interface and the SnAg solder/Ni pad interface. In the case of flip-chip samples reflowed at 250°C and 280°C, Cu₆Sn₅ and (Cu, Ni)₆Sn₅ IMCs were found at the Cu/SnAg and SnAg/Ni interfaces, respectively. In addition, an abnormal Ag₃Sn phase was detected inside the SnAg solder. However, no changes were found in the electrical contact resistance in spite of severe IMC formation in the SnAg solder after five reflows. In thermally aged flip-chip samples, Cu₆Sn₅ and Cu₃Sn IMCs were found at the Cu/SnAg interface, and (Cu, Ni)₆Sn₅ IMCs were found at the SnAg/Ni interface. However, Ag₃Sn IMCs were not observed, even for longer aging times and higher temperatures. The growth of Cu₃Sn IMCs at the Cu/SnAg interface was found to lead to the formation of Kirkendall voids inside the Cu₃Sn IMCs and linked voids within the Cu₃Sn/Cu column interfaces. These voids became more evident when the aging time and temperature increased. The contact resistance was found to be nearly unchanged after 2000 h at 125°C, but increases slightly at 150°C, and a number of Cu/SnAg joints failed after 2000 h. This failure was caused by a reduction in the contact area due to the formation of Kirkendall and linked voids at the Cu column/Cu₃Sn IMC interface.     

Low-Resistance Cu-Sn Electroplated–Evaporated Microbumps for 3D Chip Stacking

Low-resistance copper-tin (Cu-Sn) microbumps, with sizes varying from 5 μm × 5 μm to 20 μm × 20 μm and formed by electroplating–evaporation bumping (EEB) technology for three-dimensional integration of large-scale integrated chips, have been evaluated for their microstructure and electrical resistance. It was inferred from x-ray diffraction data that the formation of low-resistance Cu₃Sn intermetallic compound (IMC) is facilitated at higher bonding temperature. Electron probe microanalysis mapping showed that, even before bonding, Cu-Sn IMCs were formed at the interface between Cu and Sn, whereas they were sandwiched between the Cu of the upper and lower microbumps after bonding. Electron backscatter diffraction analysis revealed that the crystal orientation of Sn grains was sharply localized in the (100) orientation for physical vapor deposited (PVD) sample, while electroplated Sn film exhibited a mixed crystal orientation in all (100), (110), and (001) axes. A resistance value of ~35 mΩ per bump was obtained for Cu-Sn microbumps with area of 400 μm², which is several times lower than the resistance value reported for Cu-Sn microbumps fabricated by a pure electroplating method. The low resistance value obtained for EEB-formed Cu-Sn microbumps after bonding is explained by (i) the reduced surface roughness for evaporated Sn, (ii) the high degree of crystal grain orientation resulting from layer-by-layer growth in the PVD Sn, despite their smaller grain size, and (iii) the absence of impurity segregation at grain boundaries.     

新型的3D堆叠封装制备工艺及其实验测试

为了满足超大规模集成电路(VLSI)芯片高性能、多功能、小尺寸和低功耗的需求,采用了一种基于贯穿硅通孔(TSV)技术的3D堆叠式封装模型.先用深反应离子刻蚀法(DRIE)形成通孔,然后利用离子化金属电浆(IMP)溅镀法填充通孔,最后用Cu/Sn混合凸点互连芯片和基板,从而形成了3D堆叠式封装的制备工艺样本.对该样本的接触电阻进行了实验测试,结果表明,100 μm2Cu/Sn混合凸点接触电阻约为6.7 mΩ高90 μm的斜通孔电阻在20～30mΩ该模型在高达10 GHz的频率下具有良好的机械和电气性能.     

Geometrical effect of bump resistance for flip-chip solder joints: Finite-element modeling and experimental results

The bump resistance of flip-chip solder joints was measured experimentally and analyzed by the finite-element method. Kelvin structures for flip-chip solder joints were designed and fabricated to measure the bump resistance. The measured value was only about 0.9 mΘ at room temperature, which was much lower than that expected. Three-dimensional (3-D) modeling was performed to examine the current and voltage distribution in the joint. The simulated value was 7.7 mΘ, which was about 9 times larger than the experimental value. The current crowding effect was found to be responsible for the difference in bump resistance. Therefore, the measured bump resistance strongly depended on the layout of the Kelvin structure. Various layouts were simulated to investigate the geometrical effect of bump resistance, and a significant geometrical effect was found. A proper layout was proposed to measure the bump resistance correctly. The Kelvin structure would play an important role in monitoring void formation and microstructure changes during the electromigration of flip-chip solder joints.     

Double-level copper interconnections using selective copper CVD

Selective copper CVD technique involving hydrogen reduction of hexafluoro acetylacetonate copper has been used to fill vias for fabricating double-level copper interconnect structure. The surface morphology of selectively deposited copper on copper substrate of the via bottom depends strongly on via opening process. A two-step via opening process consisting of an reactive ion etching of the insulating interlayer and a wet removal of the interlayer metal results in smooth copper plug formation by CVD. Double-level copper interconnect structures have been fabricated using this technique and a via resistance as low as 100 mΩ has been obtained for a 1 μ diameter via.     

Electroless Ni/Au Bump on a Copper Patterned Wafer for the CMOS Image Sensor Package in Mobile Phones

Wafer bumping technology using an electroless Ni/Au bump on a Cu patterned wafer is studied for the flip chip type CMOS image sensor (CIS) package for the camera module in mobile phones. The effect of different pretreatment steps on surface roughness and etching of Cu pads is investigated to improve the adherence between the Cu pad and the Ni/Au bump. This study measures the shear forces on Ni/Au bumps prepared in different ways, showing that the suitable pretreatment protocol for electroless Ni plating on Cu pads is “acid dip followed by Pd activation” rather than the conventional progression of “acid-dip, microetching, and Pd activation.” The interface between the Cu pad and the Ni/Au bump is studied using various surface analysis methods. The homogeneous distribution of catalytic Pd on the Cu pad is first validated. The flip chip package structure is designed, assembled, and tested for reliability. The successful flip chip bonding in the CIS package is characterized in terms of the cross-sectional structure in which the anisotropic conductive film (ACF) particles are deformed to about 1.5 μm in diameter. The experimental results suggest that electroless Ni/Au can be applied to the flip chip type CIS package using Cu patterned wafers for high mega pixel applications.     

Wafer level and flip chip design through solder prediction modelsand validation

In flip chip package applications, bumped dies are flip-chip assembled to substrate metal pads creating joints that serve electrically and mechanically. Resulting solder joint profiles are defined by the solder bump volume, the under bump metallurgy (LTBM) area, and the substrate metal pad size and shape. Solder bump height and diameter was predicted by the geometrical truncated sphere model and surface evolver model at the wafer level, using the known solder volume deposited by stencil printing method. The surface evolver model was used to predict the assembled solder joint height, gap height, collapse height, and maximum bump diameter of flip chip assemblies. In turn, substrate pads were fine-tuned to achieve required gap heights. Collapse heights provided the means to develop assembly tolerances and relative risk of bridging was determined from knowledge of resulting bump diameters. Through validated design of the stencil printing technology and prediction of realistic bump and assembly solder geometries, the results are improved processes and die level design and assembly. Optimized design parameters are incorporated and accurately represented in simulation and experimentally validated with assemblies     

A study in flip-chip UBM/bump reliability with effects of SnPb solder composition

This paper aims to investigate the electromigration phenomenon of under-bump-metallization (UBM) and solder bumps of a flip-chip package under high temperature operation life test (HTOL). UBM is a thin film Al/Ni(V)/Cu metal stack of 1.5 μm; while bump material consists of Sn/37Pb, Sn/90Pb, and Sn/95Pb solder. Current densities of 2500 and 5000 A/cm² and ambient temperatures of 150–160 °C are applied to study their impact on electromigration. It is observed that bump temperature has more significant influence than current density does to bump failures. Owing to its higher melting point characteristics and less content of Sn phase, Sn/95Pb solder bumps are observed to have 13-fold improvement in Mean-Time-To-Failure (MTTF) than that of eutectic Sn/37Pb. Individual bump resistance history is calculated to evaluate UBM/bump degradation. The measured resistance increase is from bumps with electrical current flowing upward into UBM/bump interface (cathode), while bumps having opposite current polarity cause only minor resistance change. The identified failure sites and modes from aforementioned high resistance bumps reveal structural damages at the region of UBM and UBM/bump interface in forms of solder cracking or delamination. Effects of current polarity and crowding are key factors to observed electromigration behavior of flip-chip packages.     

Controllability of novel Sn/sub 0.95/Au/sub 0.05/ microbumps using interlaminated tin and gold layers for flip-chip interconnection

A flip-chip interconnection technology using novel lead-free solder microbumps with a balling temperature as low as 220 /spl deg/C is presented. Controllability of newly developed Sn/sub 0.95/Au/sub 0.05/ microbumps has been examined experimentally. By varying the bump volume and the diameter of the wettable bump electrodes, Sn/sub 0.95/Au/sub 0.05/ microbumps with heights from 11 /spl mu/m to 37 /spl mu/m were successfully fabricated with a standard deviation of 1.5 /spl mu/m. The deviation of on-chip CPW impedance from 50 /spl Omega/ was lower than 10% for nonmetallization motherboard. The smaller bumps exhibited a better performance since the degradation of reflection properties is ascribed to the bump capacitance, which was estimated 10-20 fF. Because of high process yield and good performance, the flip-chip bonding using Sn/sub 0.95/Au/sub 0.05/ microbumps of the order of 20 /spl mu/m in height may be advantageous for W-band interconnection of InP- or GaAs-based devices.     

Evaluation of Cu-bumps with lead-free solders for flip-chip package applications

Low cost electroplated Cu-bump with environmental friendly Sn solder was developed for flip-chip applications. The seed layer used was Ti/WN_x/Ti/Cu where WN_x was used as the Cu diffusion barrier and Ti was used to enhance the adhesion between bump and the chip pad. Thick negative photoresist (THB JSR-151N) with a high aspect ratio of 2.4 was used for electroplating of copper bump and Sn solder. The Sn solder cap was reflowed at 225° for 6 min at N₂ atmosphere. No wetting phenomenon was observed for the Sn solder as evaluated by energy-dispersed spectroscopy (EDS). The Cu-bump with Ti/WN_x/Ti/Cu seed layer not only have higher shear force than the Cu-bump with Ti/Cu seed layer but also has higher resistance to fatigue failure than the Au, SnCu, SnAg bumps.     

Three-Dimensional Thermoelectrical Simulation in Flip-Chip Solder Joints with Thick Underbump Metallizations during Accelerated Electromigration Testing

In flip-chip solder joints, thick Cu and Ni films have been used as under bump metallization (UBM) for Pb-free solders. In addition, electromigration has become a crucial reliability concern for fine-pitch flip-chip solder joints. In this paper, the three-dimensional (3-D) finite element method was employed to simulate the current-density and temperature distributions for the eutectic SnPb solder joints with 5-μm Cu, 10-μm Cu, 25-μm Cu, and 25-μm Ni UBMs. It was found that the thicker the UBM is the lower the maximum current density inside the solder. The maximum current density is 4.37 × 10⁴ A/cm², 1.69 × 10⁴ A/cm², 7.54 × 10³ A/cm², and 1.34 × 10⁴ A/cm², respectively, when the solder joints with the above four UBMs are stressed by 0.567 A. The solder joints with thick UBMs can effectively relieve the current crowding effect inside the solder. In addition, the joint with the thicker Cu UBM has a lower Joule heating effect in the solder. The joint with the 25-μm Ni UBM has the highest Joule heating effect among the four models.     

Under bump metallurgy study for Pb-free bumping

The demand for Pb-free and high-density interconnection technology is rapidly growing. The electroplating-bumping method is a good approach to meet finepitch requirements, especially for high-volume production, because to volume change of patterned-solder bumps during reflow is not so large compared with the stencil-printing method. This paper proposes a Sn/3.5 Ag Pb-free electroplating-bumping process for high-density Pb-free interconnects. It was found that a plated Sn/Ag bump becomes Sn/Ag/Cu by reflowing when Cu containing under bump metallurgy (UBM) is used. Another important issue for future flip-chip interconnects is to optimize the UBM system for high-density and Pb-free solder bumps. In this work, four UBM systems, sputtered TiW 0.2 μm/Cu 0.3 μm/electroplated Cu 5 μm, sputtered Cr 0.15 μm/Cr-Cu 0.3 μm/Cu 0.8 μm, sputtered NiV 0.2 μm/Cu 0.8 μm, and sputtered TiW 0.2 μm/NiV 0.8 μm, were investigated for interfacial reaction with electroplated Pb/63Sn and Sn/3.5Ag solder bumps. Both Cu-Sn and Ni-Sn intermetallic compound (IMC) growth were observed to spall-off from the UBM/solder interface when the solder-wettable layer is consumed during a liquid-state “reflow” process. This IMC-spalling mechanism differed depending on the barrier layer material.     

Effect of bump height on the strain variation during the thermalcycling test of ACA flip-chip joints

Flip chip joining using anisotropically conductive adhesive (ACA) has become a very attractive technique for electronics packaging. Many factors can influence the reliability of the ACA flip-chip joint. Bump height, is one of these factors. In this work, the strain development during the thermal cycling test of flip-chip joining with different bump heights was studied. The effect of bump height is significant in the interface between the bumps and the pads. Bigger volume area of high strain is found for higher bump in the interface between the bumps and the pads. Our calculations show that there is practically no effect of the bump height on the strain variation in the bumps and in the pads     

Ultra-high-density interconnection technology of three-dimensional packaging

The study of 20-μm-pitch interconnection technology of three-dimensional (3D) packaging focused on reliability, ultrasonic flip–chip bonding and Cu bump bonding is described. The interconnection life under a temperature cycling test (TCT) was at an acceptable level for semiconductor packages. Failure analysis and finite element analysis revealed the effect of material properties. Basic studies on ultrasonic flip–chip bonding and very small Cu bump formation were investigated for low-stress bonding methods. The accuracy of ultrasonic flip–chip bonding was almost the same level as that of thermocompression bonding and the electrical connection was also confirmed. Atomic-level bonding was established at the interface of Au bumps. For Cu bump bonding, a dry process was applied for under bump metallurgy (UBM) removal. Electroless Sn diffusion in Cu was investigated and the results clarified that the intermetallic layer was formed just after plating. Finally, we succeeded in building a stacked chip sample with 20-μm-pitch interconnections.     

倒装焊对探测器频响特性影响的理论分析及工艺优化

针对光探测器在倒装焊过程中频响性能恶化的问题,建立等效电路模型分析出其原因,并通过优化倒装焊工艺条件予以有效解决。该电路模型包括探测器芯片、过渡热沉和倒装焊环节三个部分。基于倒装焊后探测器的S11参数和频响曲线提取出倒装焊环节特征参数,确认焊点接触电阻过大是引起探测器频响下降的主要原因。通过优化倒装焊工艺条件,有效减小了焊点接触电阻,基本消除了倒装焊对探测器频响特性的影响。     

Comparative study of electrically conductive thick films with and without glass

An air-fireable, glass-free, electrically conductive thick-film material (96.6% Ag, 1.38% Cu, 0.28% Al, 0.35% Ti, and 1.39% Sn by weight) and a conventional glass-containing, electrically conductive thick-film materials (96.6% Ag and 3.4% glass frit by weight), both on alumina substrates, were studied by electrical, mechanical, thermal, and microscopic methods. The volume electrical resistivity of the glass-free thick film (2.5×10⁻⁶ Ω·cm, 30-μm thick) is lower than that of the glass-containing thick film (3.9×10⁻⁶ Ω·cm, 19-μm thick), with each film processed at its optimum firing temperature. The optimum firing temperature is 930°C and 850°C for glass-free and glass-containing thick films, respectively, as indicated by the criteria of low resistivity and high scratch resistance. The glass-free thick film has a higher scratch resistance than the glass-containing thick film, both fired at their respective optimum temperatures, suggesting that the former has higher bond strength to the alumina substrate. The formation process of the glass-free and glass-containing thick films is similar. The process involves solid-state diffusion of silver, which results in a silver network and grain boundaries. However, the sintering of silver particulates in the glass-containing thick film is enhanced by the viscous flow of glass.     

The microstructure characterization of ultrasmall eutectic Bi-Sn solder bumps on Au/Cu/Ti and Au/Ni/Ti under-bump metallization

The microstructure of the ultrasmall eutectic Bi-Sn solder bumps on Au/Cu/Ti and Au/Ni/Ti under-bump metallizations (UBMs) was investigated as a function of cooling rate. The ultrasmall eutectic Bi-Sn solder bump, about 50 μm in diameter, was fabricated by using the lift-off method and reflowed at various cooling rates using the rapid thermal annealing system. The microstructure of the solder bump was observed using a backscattered electron (BSE) image and the intermetallic compound was identified using energy dispersive spectroscopy (EDS) and an x-ray diffractometer (XRD). The Bi facet was found at the surface of the ultrasmall Bi-Sn solder bumps on the Au/Cu/Ti UBM in almost all specimens, and the interior microstructure of the bumps was changed with the solidification rate. The faceted and polygonal intermetallic compound was found in the case of the Bi-Sn solder bump on the Au (0.1 μm)/Ni/Ti UBM, and it was confirmed to be the (Au_1−x−yBi_xNi_y)Sn₂ phase by XRD. The intermetallic compounds grown form the Au (0.1 μm)/Ni/Ti UBM interface, and they interrupted the growth of Bi and Sn phases throughout the solder bump. The ultrasmall eutectic Bi-Sn solder bumps on the Au (0.025 μm)/Ni/Ti UBM showed similar microstructures to those on the Au/Cu/Ti UBM.