Prediction of Conditions for Chloride–Hydride Epitaxy of Ga1 – yInyAs1 – xPx Layers Isoperiodic with GaAs and GaAs1 – xPx

Semiconductors - For obtaining multicomponent III–V solid solutions, the vapor-phase methods such as the chloride–hydride epitaxy, the epitaxy from organometallic compounds, and the...     

A 1 V, 0.53 ns, 59 μW Current Comparator Using Standard 0.18 μm CMOS Technology

Wireless Personal Communications - This letter aim to propose a current comparator based on simple current mirror which use single amplifier to reduce input offset, the improving symmetry current...     

津华无线电厂简介

天津市津华无线电厂是电子工业部定点的录音机机芯生产厂。该厂生产的LX—501V型机芯和LX—401型机芯荣获全国第一届录音机机芯质量评比二等奖。 LX—501V型机芯是以镀锌钢板为基板、铁塑结合的单电机、单飞轮普及型机芯。该机芯结构简单、布局合理,体积小,重量轻,功能齐全、性能可靠。     

Temperature Coefficient of Movement of the Resonance Level of Iron in Pb1 – x – ySnxFeyTe Alloys

Semiconductors - The phase and elemental composition and the temperature dependences of the resistivity and Hall coefficient (temperature range 4.2 K ≤ T ≤ 300 K, magnetic fields B...     

45 nm/32 nm CMOS – Challenge and perspective

Production of 45 nm node CMOS has already started. However, difficulty of new technology development is increasing and some company dropped off from the competition. The big challenge for 45 nm node is the introduction of ArF immersion lithography. Most of the other technologies used for 45 nm node are the extension of those used for 65 nm node. On the other hand, there will be a big jump for 32 nm node technology. The biggest item is metal gate and high-k gate insulator system. Self barrier layer formation for BEOL is also the promising item. Variability is the biggest concern for 32 nm node SRAM. To overcome these difficulties, collaboration between device and circuit engineer is important.     

High-frequency, 6.2 Å pN heterojunction diodes

Sb-based pN heterojunction diodes at 6.2 Å, consisting of narrow bandgap p-type In_0.27Ga_0.73Sb and wide bandgap n-type In_0.69Al_0.41As_0.41Sb_0.59, have been fabricated and measured. These diodes show excellent electrical characteristics with an ideality factor of 1.2 and high current density. S-parameter measurements and subsequent analysis show that these diodes have RC-cutoff frequencies over 1 THz, making these diodes excellent choices for high-frequency applications, such as sub-harmonic mixers for frequency conversion.     

Band offsets at interfaces of (1 0 0)InxGa1−xAs (0 ⩽ x ⩽ 0.53) with Al2O3 and HfO2

The electron energy band alignment at interfaces of In_xGa_1?xAs (0 ? x ? 0.53) with atomic-layer deposited insulators Al₂O₃ and HfO₂ is characterized using combined measurements of internal photoemission of electrons and photoconductivity. The measured energy of the In_xGa_1?xAs valence band top is found to be only marginally influenced by the semiconductor composition. This result suggests that the observed bandgap narrowing from 1.42 to 0.75 eV when the In content increases from 0 to 0.53 occurs mostly through downshift of the semiconductor conduction band bottom. Electron states originating from the interfacial oxidation of In_xGa_1?xAs lead to reduction of the electron barrier at the semiconductor/oxide interface.     

北京无线电厂试制成功热熔胶枪

过去我厂收音机、收录机生产流水线上铭牌的粘接,一直采用88号胶用手工粘接,不仅有毒有味,同时粘合效果不佳。为解决这一老大难问题,北京无线电厂用了两年的时间参考国外资料样品试制出一种小型轻巧使用方便的 P—130型热熔胶枪,与北京新     

Shared hardware,high throughput implementation of 2D 4 × 4 and 8 × 8 integer transform for H.264/AVC high-profile coders

Two-dimensional discrete cosine transforms are used in the core transformations in all profiles of the H.264/Advanced video coding (AVC) standard. In this paper, implementing the resource sharing of high throughput 4 × 4 and 8 × 8 forward and inverse integer transforms for high definition H.264 is presented. It is shown that the 4 × 4 forward/inverse transform can be obtained from 8 × 8 forward/inverse transform using selective data input and data arrangement at intermediate stages. Fast 8 × 8 forward and inverse transform is implemented using matrix decomposition and matrix operation such as Kronecker product and direct sum. The proposed implementation does not require any transpose memory and has a dual clocked pipeline structure. Compared with existing designs, the gate count is reduced by 27.7% in the proposed design. The maximum operating frequency of the proposed system is approx. 1.3 GHz, while the throughput is 7 G and 18.7 G pixels/s for 4 × 4 and 8 × 8 forward integer transforms, respectively. The proposed design can be used for real time H.264/AVC high definition processing owing to its high throughput and low hardware cost.     

A 0.33 V 2.5 μW cross-point data-aware write structure,read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS

Conventional data-aware structure SRAMs consume unnecessary dynamic power during the read phase due to the read-half-select issue. In this paper, a 9T-based read-half-select disturb-free SRAM architecture with the cross-point data-aware write strategy is proposed. Based on the proposed write-half-select and read-half-select disturb-free strategy, our 9T bitcell structure improves the read and write SNM by 2.5X and 2.4X compared to traditional bitcells. Furthermore, the proposed strategy and 9T bitcell structure can reduce the read power dissipation on bitline of the SRAM array by 5.14X compared with traditional SRAMs. Based on the proposed architecture, a 16Kb SRAM is fabricated in a 130 nm CMOS which is fully functional from 1.2 V down to 0.33 V. The minimal energy per cycle is 11.8pJ at 0.35 V. The power consumption at 0.33 V is 2.5 µW with 175 kHz. The proposed SRAM has 1.5X and 4.2X less total power and leakage power than other works.     

Forming Low-Resistance p-Type Layers in Ga1 – xAlxN/GaN Heterostructures

Semiconductors - A technique for fabricating a GaN-based functional heterostructure is proposed, which allows the growth of n-type GaN and InxGa1 – xN layers and р-type GaN and...     

Direct measurement of optical phase difference in a 3 × 3 fiber coupler

The precise phase difference in a 3 × 3 coupler is calculated by using Fourier transform based white-light interferometry. The phase relationships between any two of the three outputs are directly measured, and the result is in agreement with the ideal value. The phase difference of two re-constructed signals in a 3 × 3 coupler is also measured. In a passive homodyne system, this technique is helpful in removing the distortion of the demodulated signals, which is caused by imperfect properties of the 3 × 3 coupler.     

A high-performance 1.2 V–99 μW rail-to-rail CMOS class AB amplifier

This paper presents a compact, reliable 1.2 V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated battery powered systems which require rail-to-rail input/output swing and high slew-rate while maintaining low power consumption. The OpAmp, fabricated in a standard 0.18 μm CMOS technology, exhibits 86 dB open loop gain and 97 dB CMRR. Experimental measurements prove its correct functionality operating with 1.2 V single supply, performing very competitive characteristics compared with other similar amplifiers reported in the literature. It has rail-to-rail input/output operation, 5 MHz unity gain frequency and a 3.15 V/μs slew-rate for a capacitive load of 100 pF, with a power consumption of 99 μW.     

Economic and system impact of hybrid Raman–EDFA amplification in a 40 × 40 Gbps optical transmission network with DPSK modulation

Demands of modern high-bandwidth services drive the need to constantly improve existing optical amplification technology beyond its current bounds. In this paper, we demonstrate a hybrid broadband amplification scheme which is capable of improving the system performance of a wavelength-division-multiplexed (WDM) network. We present the study of optical signals with differential-phase-shift keying (DPSK) modulation at 40 Gbps and its transmission in a 50-GHz spaced, 40-channel WDM system over an 80-km link with hybrid optical amplification. A comparison of the system and cost impacts of a Raman-only amplification scheme with two hybrid Raman–erbium doped fiber amplifier schemes (Hybrids I and II) is performed. It is shown that one of the proposed hybrid schemes (Hybrid II) outperforms the other by (i) improving the tolerance to signal input power by 17 dB and (ii) increasing the system reach by 55 km for input signal power of 5 dBm, for a bit error rate (BER) performance of 10⁻¹².     

Comparative study of low-frequency noise in 0.18 μm and 0.35 μm gate-length nMOSFETs with gate area of 1.1 μm2

We analyzed the noise characteristics of 0.18 μm and 0.35 μm nMOSFETs with a gate area of 1.1 μm² in the frequency range of 1 Hz to 100 kHz. Both two- and four-finger devices were investigated and analyzed. The experimental results show that the noise of 0.35 μm gate-length nMOSFET possesses lower 1/f component than the 0.18 μm one, whereas the four-finger devices reveal less 1/f noise than those of with two-finger ones. Furthermore, we used time domain measurement of drain current and also the statistical analysis of wafer level on the random telegraph signals (RTS) tests, and the results showed that RTS noise is higher in devices with a 0.35 μm gate-length, and devices with a smaller gate finger width produce more RTS noise than devices with a larger gate finger width.     

Atomistic model structure of the Ge(1 0 0)–GeO2 interface

An atomistic model of the Ge–GeO₂ interface has been generated through first-principle methods based on density functional theory. The interface model consists of amorphous GeO₂ connected to crystalline Ge through a substoichiometric oxide region showing regular structural parameters. Structural and electronic properties are compared to available experimental data and studied as they evolve across the Ge–GeO₂ interface.     

Erratum to: First-Principles Investigation of Electronic Properties of GaAsxSb1 – x Ternary Alloys

Semiconductors - erratum