Network random keys - a tree representation scheme for genetic and evolutionary algorithms

When using genetic and evolutionary algorithms for network design, choosing a good representation scheme for the construction of the genotype is important for algorithm performance. One of the most common representation schemes for networks is the characteristic vector representation. However, with encoding trees, and using crossover and mutation, invalid individuals occur that are either under- or over-specified. When constructing the offspring or repairing the invalid individuals that do not represent a tree, it is impossible to distinguish between the importance of the links that should be used. These problems can be overcome by transferring the concept of random keys from scheduling and ordering problems to the encoding of trees. This paper investigates the performance of a simple genetic algorithm (SGA) using network random keys (NetKeys) for the one-max tree and a real-world problem. The comparison between the network random keys and the characteristic vector encoding shows that despite the effects of stealth mutation, which favors the characteristic vector representation, selectorecombinative SGAs with NetKeys have some advantages for small and easy optimization problems. With more complex problems, SGAs with network random keys significantly outperform SGAs using characteristic vectors. This paper shows that random keys can be used for the encoding of trees, and that genetic algorithms using network random keys are able to solve complex tree problems much faster than when using the characteristic vector. Users should therefore be encouraged to use network random keys for the representation of trees.     

Application of Feed-forward Artificial Neural Networks to the Identification of Defective Analog Integrated Circuits

This paper presents a new approach for detecting defects in analog integrated circuits using a feed-forward neural network trained by the resilient error back-propagation method. A feed-forward neural network has been used for detecting faults in a simple analog CMOS circuit by representing the differences observed in power supply current of fault-free and faulty circuits. The identification of defects was performed in time and frequency domains, followed by a comparison of results achieved in both domains. We show that resilient back-propagation neural networks can be a very efficient and versatile approach for identifying defective analog circuits. Moreover, this approach is not limited to the supply current analysis, because it also offers monitoring of other circuit parameters. The type of defects detected by the resilient backpropagation neural networks, as well as other possible applications of this approach, are discussed.     

Wavelet based fault detection in analog VLSI circuits using neural networks

This paper deals with a new method of testing analog VLSI circuits, using wavelet transform for analog circuit response analysis and artificial neural networks (ANN) for fault detection. Pseudo-random patterns generated by Linear Feedback Shift Register (LFSR) are used as input test patterns. The wavelet coefficients obtained for the fault-free and faulty cases of the circuits under test (CUT) are used to train the neural network. Two different architectures, back propagation and probabilistic neural networks are trained with the test data. To minimize the neural network architecture, normalization and principal component analysis are done on the input data before it is applied to the neural network. The proposed method is validated with two IEEE benchmark circuits, namely, the operational amplifier and state variable filter.     

Synaptic dynamics in analog VLSI

Synapses are crucial elements for computation and information transfer in both real and artificial neural systems. Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatiotemporal spike patterns. Within the context of hardware implementations of pulse-based neural networks, several analog VLSI circuits modeling synaptic functionality have been proposed. We present an overview of previously proposed circuits and describe a novel analog VLSI synaptic circuit suitable for integration in large VLSI spike-based neural systems. The circuit proposed is based on a computational model that fits the real postsynaptic currents with exponentials. We present experimental data showing how the circuit exhibits realistic dynamics and show how it can be connected to additional modules for implementing a wide range of synaptic properties.     

Equivalence between some dynamical systems for optimization

It is shown by the derivation of solution methods for an elementary optimization problem that the stochastic relaxation in image analysis, the Potts neural networks for combinatorial optimization and interior point methods for nonlinear programming have common formulation of their dynamics. This unification of these algorithms leads us to possibility for real time solution of these problems with common analog electronic circuits.     

A two-variable silicon neuron circuit based on the Izhikevich model

The silicon neuron is an analog electronic circuit that reproduces the dynamics of a neuron. It is a useful element for artificial neural networks that work in real time. Silicon neuron circuits have to be simple, and at the same time they must be able to realize rich neuronal dynamics in order to reproduce the various activities of neural networks with compact, low-power consumption, and an easy-to-configure circuit. We have been developing a silicon neuron circuit based on the Izhikevich model, which has rich dynamics in spite of its simplicity. In our previous work, we proposed a simple silicon neuron circuit with low power consumption by reconstructing the mathematical structure in the Izhikevich model using an analog electronic circuit. In this article, we propose an improved circuit in which all of the MOSFETs are operated in the sub-threshold region.     

模拟电路故障诊断新方法

提出了一种新颖的基于多小波神经网络的模拟电路故障诊断方法。介绍了多小波的原理,分析了多小波神经网络的结构、逼近性质及多小波神经网络的算法,提出了用多小波来处理故障信号,提取故障特征向量输入给神经网络,从而进行模拟电路故障诊断。由于多小波函数具有连续、对称性及支撑集短等一系列优点,所以用多小波神经网络来进行模拟电路故障诊断比一般的小波神经网络具有诊断精度高、诊断速度快的优点。给出了仿真诊断实例,验证了该方法的有效性。     

图文法遗传算法

本文讨论了进化神经网络的编码表示机制，分析了它们的优缺点；提出了遗传算法的一种图文法编码表示机制，给出了相应的算子定义，以及模式、模式长度及其阶的定义；证明了一个基于图文法表示机制的遗传算法模式定理，描述了交叉和突变对模式作用的效果。     

Genetically Evolved Neural Networks for Fault Classification in Analog Circuits

A new fault classification system for analog circuits is presented. The proposed system utilises the pattern recognition potential of neural networks and the population-based search strategy of genetic algorithms in detecting and isolating faults in analog circuits. Features that characterise the circuit behaviour under fault-free and fault situations are first simulated or measured. An unsupervised fault-grouping algorithm that estimates the overlaps between different faults in the features space is then introduced. Accordingly, a suitable training set is constructed and employed to train a population of genetically evolved neural networks to recognise circuit faults. A two-phase analog fault classification strategy is also developed. Experimental results demonstrate the high classification accuracy of the proposed system. ID="A1" Correspondence and offprint requests to: M.A. El-Gamal, Department of Engineering Physics Mathematics, Cairo University, Giza, Egypt Email: mhgamal@alpha1-eng.cairo.eun.eg     

基于遗传BP网络的模拟电路故障诊断方法及其应用

针对BP网络诊断模拟电路故障时存在网络结构复杂且可能出现误诊断的不足,提出一种小波变换、遗传算法与神经网络相结合的模拟电路故障诊断的新方法.该方法使用节点电压信号经小波变换、主元分析和归一化处理来实现故障特征的提取,以减少信号的冗余;由于BP网络易陷入局部最优,采用遗传箅法来优化BP网络的结构和初始权值分布,使优化后的神经网络具有较好的收敛性能.最后结合电路实例,对文中提出诊断方法的原理与实现进行了较深入的分析,建立了该方法的测试系统,并通过工程应用效果进一步验证了文中方法的正确性.     

A novel approach for analog fault diagnosis based on neural networks and improved kernel PCA

We have developed a neural-network-based fault diagnosis approach of analog circuits using maximal class separability based kernel principal components analysis (MCSKPCA) as preprocessor. The proposed approach can detect and diagnose faulty components efficiently in the analog circuits by analyzing their time responses. First, using wavelet transform to preprocess the time responses obtains the essential and reduced candidate features of the corresponding response signals. Then, the second preprocessing by MCSKPCA further reduces the dimensionality of candidate features so as to obtain the optimal features with maximal class separability as inputs to the neural networks. This simplifies the architectures reasonably and reduces the computational burden of neural networks drastically. The simulation results show that our resulting diagnostic system can classify the faulty components of analog circuits under test effectively and achieves a competitive classification performance.     

Digit and command interpretation for electronic book using neural network and genetic algorithm

This paper presents the interpretation of digits and commands using a modified neural network and the genetic algorithm. The modified neural network exhibits a node-to-node relationship which enhances its learning and generalization abilities. A digit-and-command interpreter constructed by the modified neural networks is proposed to recognize handwritten digits and commands. A genetic algorithm is employed to train the parameters of the modified neural networks of the digit-and-command interpreter. The proposed digit-and-command interpreter is successfully realized in an electronic book. Simulation and experimental results will be presented to show the applicability and merits of the proposed approach.     

基于多小波变换的模拟电路IDDT故障诊断

动态电源电流测试（I_DDT ）对模拟电路故障诊断非常有效。针对小波神经网络在模拟电路I_DDT故障诊断中存在的缺陷,提出了一种基于多小波变换的模拟电路I_DDT故障诊断方法。即利用多小波变换提取电源电流各频段的能量,作为神经网络的输入特征向量进行故障诊断。仿真结果表明,该方法是有效的,而且比小波神经网络方法的收敛速率快。     

An artificial neural network approach for routing in distributed computer networks

This paper presents a new approach based on the Hopfield model of artificial neural networks to solve the routing problem in a context of computer network design. The computer networks considered are packet switching networks, modeled as non-oriented graphs where nodes represent servers, hosts or switches, while bi-directional and symmetric arcs represent full duplex communication links. The proposed method is based on a network representation enabling to match each network configuration with a Hopfield neural network in order to find the best path between any node pair by minimizing an energy function. The results show that the time delay derived from flow assignment carried out by this approach is, in most cases, better than those determined using conventional routing heuristics. Therefore, this neural-network approach is suitable to be integrated into an overall topological design process of moderate-speed and high-speed networks subject to quality of service constraints as well as to changes in configuration and link costs.     

基于多小波变换的模拟电路IDDT故障诊断

动态电源电流测试（IDDT）对模拟电路故障诊断非常有效。针对小波神经网络在模拟电路IDDT故障诊断中存在的缺陷,提吐了一种基于多小波变换的模拟电路IDDT故障诊断方法。即利用多小波变换提取电源电流各频段的能量,作为神经网络的输入特盘向量进行故障诊断。仿真结果表明,该方法是有效的,而且比小波神经网络方法的收敛速率快。     

社交网络中基于IAUE模型的锚链识别

社交网络中的锚链识别对于跨网络信息传播、跨平台推荐、社交链预测等具有重要意义.针对当前锚链识别研究中准确率低的问题,提出了一种有效提高锚链识别准确率的方法：IAUE模型.该模型首先利用网络结构信息进行网络表征学习,然后利用BP神经网络、随机梯度下降和负采样等方法得到异构网络节点间的锚链候选集,最后辅以G-S算法精化锚链匹配结果,提高异构网络对齐的准确率.多个数据集上的实验结果表明,IAUE方法相比其他方法具有较高的性能和很好的泛化能力,可以较为准确地识别网络中的锚链.     

遗传BP神经网络在大宗商品市场风险预警中的应用

研究利用遗传BP神经网络预警大宗商品电子交易市场风险的应用方法,将定量分析的思维方式引入大宗商品市场风险评价管理中.为此目的,建构了一个基于遗传BP神经网络的预警模型（GA-BPNNM）,在市场调研的基础上建立了大宗商品电子交易市场风险评价指标体系,并通过实验确定了预警模型的最佳训练函数和隐层的最佳节点数.GA-BPNNM借助BP神经网络强大的自学习能力和非线性映射能力,克服传统手段在分析大宗商品电子交易市场风险时因其定义的模糊性和诱发因素的多样性所带来的困难;同时通过遗传算法与BP网络两者相互融合优化,解决BP神经网络易落入局部最优、收敛速度慢以及遗传算法易早熟等问题.仿真测试实验表明,GA-BPNNM预测结果优于标准BP神经网络预测方法,用于大宗商品电子交易市场风险损失程度预警是有效可行的.