瞬变电压抑制器失效模式和失效机理研究

由于目前对TVS自身可靠性的研究较少,提出了对TVS产品的可靠性研究.这项研究得到国内TVS生产厂家的支持,对该厂6个型号TVS筛选进行了跟踪.根据筛选失效数据,对温度循环、箝位冲击、高温反偏和功率老炼等TVS失效比例较大的筛选项目的失效品,经过电参数测试、解剖、显微观察,确定失效模式、分析失效机理.结果表明,TVS主要失效模式有短路、开路、反向漏电流大和异常击穿,且高击穿电压TVS更易发生失效.     

典型ESD防护器件失效机理研究

瞬态电压抑制管(TVS)是电子线路设计中常用的静电放电(ESD)防护器件,其可靠性将直接影响整个电路的安全。选取常见的TVS器件PESD5V0U1BA进行研究,通过实验和仿真分析了TVS器件的短路失效机理及其影响。研究表明,当TVS器件注入高压时,器件存在缺陷的SiO2层会发生自愈性击穿。当器件的pn结发生击穿时,器件将失效。如果两个pn结都被击穿,器件的I-V曲线表现为电阻特性。当TVS器件出现损伤后,器件仍具有箝位作用,且其表现的箝位电压更低,但由于器件的漏电流发生较大的增长,将影响被保护电路的正常工作。     

片式多层陶瓷电容失效模式研究

介绍了片式陶瓷电容的基本结构和材料特性及其常见的短路、开路和参数漂移失效模式;分析了失效的主要原因.结合工程实践,从器件选型、用前筛选、版图及结构设计和装配工艺选择等方面,给出了提高多层陶瓷电容使用可靠性的建议.     

片式钽电容短路失效故障分析及改进

该文针对片式钽电容在实际生产和使用过程中短路失效故障率过高的问题,从元器件自身故障原理、使用工艺、电路板设计等方面进行深入分析,最终确定钽电容短路失效是钽电容自身缺陷与外界应力综合作用的结果,外界应力主要有焊接温度应力和反向电压冲击。针对以上原因,从钽电容自身质量、工艺、设计等方面进行改进,通过加严筛选、改手工焊、优化回流曲线等具体措施,有效控制了片式钽电容短路失效故障,保证了其可靠性,提高了钽电容使用质量。     

集成电路封装用绝缘胶漏电失效分析

在电子元器件封装领域中,塑封器件正逐步替代气密性封装器件。目前工业级塑封器件已不能满足器件的高可靠性要求,工业级塑封器件在严酷的环境应力试验中经常出现失效。研究了工业级塑封器件在可靠性筛选试验中出现失效的问题,通过X射线观察和芯片切面分析等方法,查明了造成器件失效的原因,并提出了优化改进措施。     

耿氏二极管的几种失效模式及其机理分析

介绍了耿氏二极管的工作原理及其基本结构,通过外观检查、电特性测试、环境试验、内部目检、X射线及扫描电镜(SEM)检查等失效分析手段和方法,针对耿氏二极管在使用过程中较常出现的短路、开路及管帽脱落等失效模式及失效机理进行了分析和讨论,并根据上述几种失效模式对应的机理,指出了避免失效的一些措施,对该器件的制造商和使用者具有一定的参考价值.     

电池保护电路中MOSFET器件常见失效机理研究

受限于电子设备的内部空间,电池保护电路中MOSFET器件通常采用晶圆级芯片规模封装（WLCSP）。由于WLCSP的特点,电池保护电路中的MOSFET器件在生产、使用中会出现各种类型的失效模式和失效机理。介绍了采用WLCSP技术封装的MOSFET器件常用的分析方法与设备,结合相关的失效案例,论述了芯片开裂、芯片工艺缺陷、芯片腐蚀和过电应力这4种常见的失效机理,为MOSFET器件及其他电子元器件的失效分析和问题解决提供一定的参考。     

50例微波器件失效分析结果汇总与分析

对约50例微波器件失效分析结果进行了汇总和分析,阐述了微波器件在使用中失效的主要原因、分类及其分布。汇总情况表明,由于器件本身质量和可靠性导致的失效约占80%,其余20%是使用不当造成的。在器件本身的质量和可靠性问题方面,具体失效机理有引线键合不良、芯片缺陷(包括沾污、裂片、工艺结构缺陷等)、芯片粘结、管壳缺陷、胶使用不当等;在使用不当方面,主要是静电放电(ESD)损伤和过电损伤(EOS),EOS损伤中包括输出端失配、加电顺序等操作不当引入的过电应力等。     

PBGA器件焊点的可靠性分析研究

根据PBGA器件组装特点,分析了器件焊点的失效机理,并针对实际应用中失效的PBGA器件在温度循环前后,分别使用染色试验、切片分析、X-射线分析等方法进行失效分析.分析结果显示样品PBGA焊点存在不同程度的焊接问题,并且焊接质量的好坏直接影响器件焊点抵抗外界应变应力的能力.最后,开展了PBGA器件焊接工艺研究和可靠性试验,试验结果显示焊接工艺改进后焊点的可靠性良好.     

多层瓷介电容器失效模式和机理

系统介绍了开路、短路和电参数漂移这三种主要的MLCC失效模式,以及介质层内空洞和电极结瘤、介质层分层、热应力和机械应力引起介质层裂纹、其他微观机理等五种主要的失效机理。针对MLCC的失效分析技术,从生产工艺和使用设计上提出了预防MLCC失效的措施。     

宫腔镜对阴道超声发现子宫内膜异常的诊治价值

目的：研究阴道超声发现子宫内膜异常患者的宫腔镜诊治价值。方法：对827例经阴道超声检查发现子宫内膜异常的患者行官腔镜检查,并行诊断性刮宫或宫腔内病变电切,组织物送病检。结果：以病检结果为诊断标准,宫腔镜检查对子宫内膜息肉、子宫粘膜下肌瘤、正常子宫内膜、宫颈管息肉及子宫内膜癌的诊断符合率均明显高于阴道超声检查（P〈0．01）;宫腔镜检查对子宫内膜病变诊断的敏感性和特异性分别是95．23％和86,82％,而阴道超声检查对子宫内膜病变诊断的敏感性和特异性分别是83．99％和41．23％。结论：对阴道超声检查发现子宫内膜异常的患者应常规行宫腔镜检查并取组织活检,才能提高诊断符合率,减少误诊和漏诊。     

A new wafer level reliability method for evaluation of ionic induced pmosfet drift effects

An ionic induced pMOSFET drift effect was investigated by deliberately enhancing the sodium concentration in interlevel dielectric layers.High frequency capacitance voltage and triangular voltage sweep (TVS) measurements as well as different bias temperature stress sequences were employed to show that the degradation is a two step process: sodium drift into active areas and charging of traps which were generated by sodium interactions with the semiconductor oxide interface.A special wafer level reliability method was developed which takes into consideration the two phase nature of the failure mechanism.     

A numerical approach based on transient thermal analysis toestimate the safe operating frequencies of thyristors

The spatio-temporal distribution of temperatures in high-power SCRs used for switching high di/dt current pulses were simulated using the finite element method (FEM). Two types of SCRs, with amplifying gate (unshorted device), and without amplifying gate (shorted device) structures, were analyzed. The details of the numerical simulation, such as the meshing strategy, the heat source model and the boundary conditions are discussed. Based on the analysis, the failure temperature of the unshorted device was computed to be 1100°C. The peak temperature in the shorted device was, however, found to be 335°C. The instantaneous cooling cycles of the devices and their cooling time constants, as obtained from the simulations, are presented. Based on these parameters, the safe operating frequencies of these devices were estimated     

Lateral punch-through TVS devices for on-chip protection in low-voltage applications

A novel lateral punch-through TVS (Transient Voltage Suppressor) structure addressed to on-chip protection in very low voltage applications is reported in this paper. Different lateral TVS structures have been studied in order to optimize the electrical performances related with the surge protection capability. Lateral TVS structures with a four-layer doping profile exhibit the best electrical performances, as in the case of vertical TVS devices. The dependence of the basic electrical characteristics on the technological and geometrical parameters is also analysed. Finally, the electrical performances of lateral TVS structures are compared with those of vertical punch-through TVS devices and conventional Zener diodes, being the leakage current level reduced two orders of magnitude in the case of the lateral architecture. Lateral TVS structures exhibits similar performance than vertical counterparts with the advantage of easiest on-chip integration.     

Shorted matrices in star and related orderings

A new class of shorted operators is considered. The shorted operator has an intimate relationship with electrical networks and has been extensively studied. In this work we consider the class of matrices with row and column spans in specified linear subspaces and dominated in a given partial order by a matrixA. If this class of matrices has an unique maximal element under the partial order, then this maximal element is called the shorted matrix ofA relative to the given linear subspaces and the relevant partial order. We study the shorted matrix under the star order of Drazin, the minus order, and also under partial orders induced by the minimum norm and least squares g-inverses. The parallel sum of matrices is intimately related to the shorted matrix and results are given for parallel addition.     

电子设备中的ESD保护设计

介绍了静电放电(ESD)的工作机理以及静电放电给电子元器件所带来的损伤。通过对比压敏电阻与瞬变电压抑制二极管(TVS管)的特点,给出了如何选择ESD保护器件的一些建议。在分析了TVS管的工作原理及关键参数基础上,对TVS管选型标准进行了简要介绍。针对使用TVS管的保护电路,以IEC61000-4-2最高严酷度级别4的环境对电路中的寄生参数进行了分析,提出了优化ESD保护器件性能及PCB保护电路设计时需要注意的事项。以MAX3490E为例指出了集成片上ESD系统芯片的优点。     

Electromigration and electrochemical reaction mixed failure mechanism in gold interconnection system

Power bipolar devices with gold metallization experience high failure rates. The failures are characterized as shorts, detected during LSI testing at burn-in. Many of these shorted locations in the chip are the same for the failed devices. From a statistical analysis for wafer lots, it is found that the short failure rate is higher for the lots with thinner SiON interlayer dielectric films. Cracks are commonly observed in the SiON films at step edge portions of the device. The SiON film is locally turned to Au–Si eutectic at short positions by the reaction of Au with the SiON film and the reaction is only generated at specific step edge portions, i.e., at step edge on emitter electrodes in driver transistors and/or at cross-points of power lines. Based upon these results, a new electromigration and electrochemical reaction mixed failure mechanism is proposed for the failure.     

Stacked shorted patch antenna

A novel stacked shorted patch antenna is proposed and investigated both theoretically and experimentally. The new antenna has significantly greater bandwidth than a conventional shorted patch and its behaviour is less susceptible to manufacturing errors. The stacked shorted patch is small in size and, thus, is suitable for mobile communication applications