A virtual metrology system for semiconductor manufacturing

Nowadays, the semiconductor manufacturing becomes very complex, consisting of hundreds of individual processes. If a faulty wafer is produced in an early stage but detected at the last moment, unnecessary resource consumption is unavoidable. Measuring every wafer’s quality after each process can save resources, but it is unrealistic and impractical because additional measuring processes put in between each pair of contiguous processes significantly increase the total production time. Metrology, as is employed for product quality monitoring tool today, covers only a small fraction of sampled wafers. Virtual metrology (VM), on the other hand, enables to predict every wafer’s metrology measurements based on production equipment data and preceding metrology results. A well established VM system, therefore, can help improve product quality and reduce production cost and cycle time. In this paper, we develop a VM system for an etching process in semiconductor manufacturing based on various data mining techniques. The experimental results show that our VM system can not only predict the metrology measurement accurately, but also detect possible faulty wafers with a reasonable confidence.     

Evaluating the reliability level of virtual metrology results for flexible process control: a novelty detection-based approach

The purpose of virtual metrology (VM) in semiconductor manufacturing is to support process monitoring and quality control by predicting the metrological values of every wafer without an actual metrology process, based on process sensor data collected during the operation. Most VM-based quality control schemes assume that the VM predictions are always accurate, which in fact may not be true due to some unexpected variations that can occur during the process. In this paper, therefore, we propose a means of evaluating the reliability level of VM prediction results based on novelty detection techniques, which would allow flexible utilization of the VM results. Our models generate a high-reliability score for a wafer’s VM prediction only when its process sensor values are found to be consistent with those of the majority of wafers that are used in model building; otherwise, a low-reliability score is returned. Thus, process engineers can selectively utilize VM results based on their reliability level. Experimental results show that our reliability generation models are effective; the VM results for wafers with a high level of reliability were found to be much more accurate than those with a low level.     

Virtual metrology and feedback control for semiconductor manufacturing processes using recursive partial least squares

Virtual metrology (VM) is the prediction of metrology variables (either measurable or non-measurable) using process state and product information. In the past few years VM has been proposed as a method to augment existing metrology and has the potential to be used in control schemes for improved process control in terms of both accuracy and speed. In this paper, we propose a VM based approach for process control of semiconductor manufacturing processes on a wafer-to-wafer (W2W) basis. VM is realized by utilizing the pre-process metrology data and more importantly the process data from the underlying tools that is generally collected in real-time for fault detection (FD) purposes. The approach is developed for a multi-input multi-output (MIMO) process that may experience metrology delays, consistent process drifts, and sudden shifts in process drifts. The partial least squares (PLS) modeling technique is applied in a novel way to derive a linear regression model for the underlying process, suitable for VM purposes. A recursive moving-window approach is developed to update the VM module whenever metrology data is available. The VM data is then utilized to develop a W2W process control capability using a common run-to-run control technique. The proposed approach is applied to a simulated MIMO process and the results show considerable improvement in wafer quality as compared to other control solutions that only use lot-to-lot metrology information.     

Machine learning-based novelty detection for faulty wafer detection in semiconductor manufacturing

Since semiconductor manufacturing consists of hundreds of processes, a faulty wafer detection system, which allows for earlier detection of faulty wafers, is required. statistical process control (SPC) and virtual metrology (VM) have been used to detect faulty wafers. However, there are some limitations in that SPC requires linear, unimodal and single variable data and VM underestimates the deviations of predictors. In this paper, seven different machine learning-based novelty detection methods were employed to detect faulty wafers. The models were trained with Fault Detection and Classification (FDC) data to detect wafers having faulty metrology values. The real world semiconductor manufacturing data collected from a semiconductor fab were tested. Since the real world data have more than 150 input variables, we employed three different dimensionality reduction methods. The experimental results showed a high True Positive Rate (TPR). These results are promising enough to warrant further study.     

测量时延在线估计与批间控制器协同设计

批间控制是半导体批次生产过程中常用算法,其关键问题在于能够及时获取上一批次的制程输出,受测量手段及其成本限制,实际的生产制程很难满足这一要求.为此,本文提出一种基于贝叶斯统计分析的测量时延估计算法.在分析晶圆质量与实测时延、估计时延、以及制程漂移之间的逻辑关系的基础上,并将晶圆的质量信息按加工时间顺序划分两个相邻的滚动时间窗口.基于贝叶斯后验概率函数,及时捕获后一个滚动时间窗口内过程输出发生漂移的概率,从而判断是否有测量时延发生,并估算该时延大小.在此基础上,给出批间控制器的测量时延补偿策略,及时调整制程的控制量,提高晶圆的加工品质.仿真结果验证所提出算法的有效性.     

含随机测量时延的EWMA批间控制器设计

批间控制(RtR)是半导体晶圆生产过程控制的有效算法. 然而, 受测量手段与测量成本的限制, 难以实时检 测晶圆的品质数据, 即: 存在一定的测量时延, 通常该测量时延是随机, 时变的, 且直接影响批间控制器的性能. 为 此, 本文基于指数加权移动平均(EWMA)算法, 提出一种含随机测量时延的扰动估计方法. 在分析测量概率的基础 上, 建立包含测量时延概率的扰动估计表达式; 并采用期望最大化(EM)算法估计该测量时延的概率; 然后分析系统 可能存在的静差项, 给出相应的补偿算法; 最后讨论系统的稳定性. 仿真实例验证所提算法的有效性.     

Causal modelling of semiconductor fabrication

Semiconductor fabrication is the manufacturing process by which wafers of silicon are turned into integrated circuits. Reasoning about how wafers are affected by fabrication operations is an important aspect in getting computers to aid in the diagnosis of manufacturing faults and in the design of new fabrication processes. Our research has been aimed at characterizing the knowledge needed to construct qualitative, causal models that can support diagnosis and design of the processes by which semiconductors are manufactured. This article presents our models of wafer structure and the operations that are used in semiconductor fabrication, and describes how a domain-independent simulator uses these models to determine how the operations affect the wafer structure. We also demonstrate how the causal dependencies recorded by the simulator can be used to diagnose manufacturing faults. We conclude with a comparison of our method of using discrete, causal models to other methods of modelling semiconductor fabrication.     

An intelligent virtual metrology system with adaptive update for semiconductor manufacturing

Virtual metrology involves the estimation of metrology values using a prediction model instead of metrological equipment, thereby providing an efficient means for wafer-to-wafer quality control. Because wafer characteristics change over time according to the influence of several factors in the manufacturing process, the prediction model should be suitably updated in view of recent actual metrology results. This gives rise to a trade-off relationship, as more frequent updates result in a higher accuracy for virtual metrology, while also incurring a heavier cost in actual metrology. In this paper, we propose an intelligent virtual metrology system to achieve a superior metrology performance with lower costs. By employing an ensemble of artificial neural networks as the prediction model, the prediction, reliability estimation, and model update are successfully integrated into the proposed virtual metrology system. In this system, actual metrology is only performed for those wafers where the current prediction model cannot perform reliable predictions. When actual metrology is performed, the prediction model is instantly updated to incorporate the results. Consequently, the actual metrology ratio is automatically adjusted according to the corresponding circumstances. We demonstrate the effectiveness of the method through experimental validation on actual datasets.     

Real-time virtual metrology and control for plasma etch

Plasma etch is a semiconductor manufacturing process during which material is removed from the surface of semiconducting wafers, typically made of silicon, using gases in plasma form. A host of chemical and electrical complexities make the etch process notoriously difficult to model and troublesome to control. This work demonstrates the use of a real-time model predictive control scheme to control plasma electron density and plasma etch rate in the presence of disturbances to the ground path of the chamber. Virtual metrology (VM) models, using plasma impedance measurements, are used to estimate the plasma electron density and plasma etch rate in real time for control, eliminating the requirement for invasive measurements. The virtual metrology and control schemes exhibit fast set-point tracking and disturbance rejection capabilities. Etch rate can be controlled to within 1% of the desired value. Such control represents a significant improvement over open-loop operation of etch tools, where variances in etch rate of up to 5% can be observed during production processes due to disturbances in tool state and material properties.     

A fuzzy hierarchical reinforcement learning based scheduling method for semiconductor wafer manufacturing systems

Scheduling semiconductor wafer manufacturing systems has been viewed as one of the most challenging optimization problems owing to the complicated constraints, and dynamic system environment. This paper proposes a fuzzy hierarchical reinforcement learning (FHRL) approach to schedule a SWFS, which controls the cycle time (CT) of each wafer lot to improve on-time delivery by adjusting the priority of each wafer lot. To cope with the layer correlation and wafer correlation of CT due to the re-entrant process constraint, a hierarchical model is presented with a recurrent reinforcement learning (RL) unit in each layer to control the corresponding sub-CT of each integrated circuit layer. In each RL unit, a fuzzy reward calculator is designed to reduce the impact of uncertainty of expected finishing time caused by the rematching of a lot to a delivery batch. The results demonstrate that the mean deviation (MD) between the actual and expected completion time of wafer lots under the scheduling of the FHRL approach is only about 30 % of the compared methods in the whole SWFS.     

Application of a genetic algorithm in solving the capacity allocation problem with machine dedication in the photolithography area

Wafer fabrication is a complicated manufacturing process with high process capability. Hence, maximizing machine capacity to meet customer deadlines is a very important issue in this field. This study proposes an integer programming model and a heuristic algorithm approach to solve the loading balance problem for the photolithography area in the semiconductor manufacturing industry. Considering process capability, machine dedication, and reticle constraints, we aim to minimize the difference in loading between machines. Process capability means that each product must be processed in machines that meet the process specification. Machine dedication means that if the first critical layer of a wafer is assigned to a certain machine, then the following critical layers of such wafer must be processed in this certain machine to ensure wafer quality. This research compares the results of two methods and finds the best parameter settings of the genetic algorithm (GA). The computational performance results of the GA shows that we can find the near-optimal solution within a reasonable amount of time. Finally, this research analyzes machine capability and reticle flexibility to determine the best percentage that can be used as reference for application in the semiconductor industry.     

A virtual metrology model based on recursive canonical variate analysis with applications to sputtering process

In data driven process monitoring, soft-sensor, or virtual metrology (VM) model is often employed to predict product's quality variables using sensor variables of the manufacturing process. Partial least squares (PLS) are commonly used to achieve this purpose. However, PLS seeks the direction of maximum co-variation between process variables and quality variables. Hence, a PLS model may include the directions representing variations in the process sensor variables that are irrelevant to predicting quality variables. In this case, when direction of sensor variables’ variations most influential to quality variables is nearly orthogonal to direction of largest process variations, a PLS model will lack generalization capability. In contrast to PLS, canonical variate analysis (CVA) identifies a set of basis vector pairs which would maximize the correlation between input and output. Thus, it may uncover complex relationships that reflect the structure between quality variables and process sensor variables. In this work, an adaptive VM based on recursive CVA (RCVA) is proposed. Case study on a numerical example demonstrates the capability of CVA-based VM model compared to PLS-based VM model. Superiority of the proposed model is also presented when it applied to an industrial sputtering process.     

Control relevant issues in semiconductor manufacturing: Overview with some new results

The quality control of integrated circuit (IC) processing is becoming more and more important as the wafer becomes larger and the feature size shrinks. However, an advanced IC fabrication process consists of 300+ steps with scarce and usually difficult quality measurements. Thus product yield may not be realized until months into production while in-line measurements are available on the order of a millisecond. The series production nature and measurement setup lead to a unique process control problem. In this work, typical disturbances are explained and the possibility for inferential control is explored. This leads to a control architecture with multiple layers in a cascade structure. Next, the rapid thermal processing (RTP) is used to illustrate recipe generation and control structure design at the tool level. The resultant multivariable controller gives satisfactory setpoint tracking for a triangular-like temperature program. Effective delay in a feedback loop at the process level is also clarified which can be used to design a run-to-run controller or to prioritize the measurement queue for the metrology tool. In order to prolong the time between maintenance and to reduce rework, process trend monitoring of a tool is essential. Instead of using entire batch data, a key process variable is identified and an index is computed to capture dynamic behavior of the tool. An IC processing example is used to illustrate this approach and results clearly indicate that process trend is well predicted using the index-based time-series model. Finally, future research directions for improved semiconductor manufacturing are also described.     

A new state estimation method for high-mix semiconductor manufacturing processes

In semiconductor manufacturing upstream processes may affect the wafer substrate in a manner that alters performance in downstream operations, and the context within which a process is run may fundamentally change the way the process behaves. Incorporating these influences into a control method ultimately leads to better predictability and improved control performance, because one lot of a specific product may take a very different processing path through the fabrication facility than the next lot of that same product. This paper provides a new method for state estimation in a high-mix manufacturing scenario, based on a random walk model. This model, combined with a moving window approach and least squares solution, provides better estimates for simulated processes with a high-mix of tools and products with many low-runners as compared to alternative methods. An approach combining the Kalman filter and the least squares solution is also developed, with improved results in some cases. In the case of manufacturing data, we modify the model parameters and the weights on processing contexts to get better results.     

Simulation-based optimization of sampling plans to reduce inspections while mastering the risk exposure in semiconductor manufacturing

Semiconductor manufacturing processes are very long and complex, needing several hundreds of individual steps to produce the final product (chip). In this context, the early detection of process excursions or product defects is very important to avoid massive potential losses. Metrology is thus a key step in the fabrication line. Whereas a 100 % inspection rate would be ideal in theory, the cost of the metrology devices and cycle time losses due to these measurements would completely inhibit such an approach. On another hand, the skipping of some measurements is risky for quality assurance and processing machine reliability. The purpose is to define an optimized quality control plan that reduces the required capacity of control while maintaining enough trust in quality controls. The method adopted by this research is to employ a multi-objective genetic algorithm to define the optimized control plan able to reduce the used metrology capacity without increasing risk level. Early results based on one month of real historical data computation reveal a possible reallocation of controls with a decrease by more than 15 % of metrology capacity while also reducing the risk level on the processing machine (expressed by the wafer at risk (\(W\!@\!R\))) by 30 %.     

An integrated advanced process control framework using run-to-run control,virtual metrology and fault detection

This paper develops a new advanced process control (APC) system for the multiple-input multiple-output (MIMO) semiconductor processes using the partial least squares (PLS) technique to provide the run-to-run control with the virtual metrology data, via the gradual mode or the rapid mode depending on the current system status, in order to deal with metrology delays and compensate for different types of system disturbances. First, we present a controller called the PLS-MIMO double exponentially weighted moving average (PLS-MIMO DEWMA) controller. It employs the PLS method as the model building/estimation technique to help the DEWMA controller generate more consistent and robust control outputs than purely using the conventional DEWMA controller. To cope with metrology delays, the proposed APC system uses the pre-processing metrology data to build up the virtual metrology (VM) system that can provide the estimated process outputs for the PLS-MIMO DEWMA controller. Lastly, the Fault Detection (FD) system is added based upon the principal components of the PLS modeling outcomes, which supplies the process status for the VM mechanism and the PLS-MIMO DEWMA controller as to how the process faults are responded. Two scenarios of the simulation study are conducted to illustrate the APC system proposed in this paper.     

Virtual metrology modeling of time-dependent spectroscopic signals by a fused lasso algorithm

This paper proposes a fused lasso model to identify significant features in the spectroscopic signals obtained from a semiconductor manufacturing process, and to construct a reliable virtual metrology (VM) model. Analysis of spectroscopic signals involves combinations of multiple samples collected over time, each with a vast number of highly correlated features. This leads to enormous amounts of data, which is a challenge even for modern-day computers to handle. To simplify such complex spectroscopic signals, dimension reduction is critical. The fused lasso is a regularized regression method that performs automatic variable selection for the predictive modeling of highly correlated datasets such as those of spectroscopic signals. Furthermore, the fused lasso is especially useful for analyzing high-dimensional data in which the features exhibit a natural order, as is the case in spectroscopic signals. In this paper, we conducted an experimental study to demonstrate the usefulness of a fused lasso-based VM model and compared it with other VM models based on the lasso and elastic-net models. The results showed that the VM model constructed with features selected by the fused lasso algorithm yields more accurate and robust predictions than the lasso- and elastic net-based VM models. To the best of our knowledge, ours is the first attempt to apply a fused lasso to VM modeling.     

Hierarchical indices to detect equipment condition changes with high dimensional data for semiconductor manufacturing

During semiconductor manufacturing process, massive and various types of interrelated equipment data are automatically collected for fault detection and classification. Indeed, unusual wafer measurements may reflect a wafer defect or a change in equipment conditions. Early detection of equipment condition changes assists the engineer with efficient maintenance. This study aims to develop hierarchical indices for equipment monitoring. For efficiency, only the highest level index is used for real-time monitoring. Once the index decreases, the engineers can use the drilled down indices to identify potential root causes. For validation, the proposed approach was tested in a leading semiconductor foundry in Taiwan. The results have shown that the proposed approach and associated indices can detect equipment condition changes after preventive maintenance efficiently and effectively.     

Rule-based scheduling in wafer fabrication with due date-based objectives

Wafer fabrication is a capital-intensive and highly complex manufacturing process. In the wafer fabrication facility (fab), wafers are grouped as a lot to go through repeated sequences of operations to build circuitry. Lot scheduling is an important task for manufacturers to improve production efficiency and meet customers’ requirements of on-time delivery. In this research we propose a dispatching rule for lot scheduling in wafer fabs, focusing on three due date-based objectives: on-time delivery rate, mean tardiness, and maximum tardiness. Although many dispatching rules have been proposed in the literature, they usually perform well in some objectives and bad in others. Our rule implements good principles in existing rules by means of (1) an urgency function for a single lot, (2) a priority index function considering total urgency of multiple waiting lots, (3) a due date extension procedure for dealing with tardy lots, and (4) a lot filtering procedure for selecting urgent lots. Simulation experiments are conducted using nine data sets of fabs. Six scenarios formed by two levels of load and three levels of due date tightness are tested for each fab. Performance verification of the proposed rule is achieved by comparing with nine benchmark rules. The experimental results show that the proposed rule outperforms the benchmark rules in terms of all concerned objective functions.     

A two-phase dynamic dispatching approach to semiconductor wafer testing

There have been numerous advancements and rising competition in semiconductor technologies. In light of this, the wafer test plays a more significant role in providing the most prompt yield feedback for quick process improvement. However, the wafer test shop floor is getting more complicated than ever before because of the increasing change-over rate, nonlinear wafer arrival, and preemption by urgent orders. Furthermore, the foundry wafer test is a heterogeneous production with different production cycle times and a large variety of nonidentical testers. Shop floor conditions, including work in process (WIP) pool, tester status, and work order priority, continuously change. There is a need to operate the kind of production line that simultaneously fulfills multiple objectives. Such objectives are maximum confirmed line item performance (CLIP) for normal lots, 100% CLIP for urgent lots, minimum change-over rate, and shortest cycle time. Thus, a reactive dispatching approach is proposed and expected to perform a real-time solution no matter how/what the shop floor would change. The dynamic approach is mainly triggered by two kinds of major events: one is when an urgent lot comes in, and the other is when a tester is idle. In addition, through a two-phase dispatching algorithm, lot ranking, and lot assignment methods, prioritized WIP lots and an appropriate lot assignment are suggested. A better performance measure is obtained by considering the multiple objectives the wafer test operations seek to achieve.