Two-dimensional analytical model of threshold voltage and drain current of a double-halo gate-stacked triple-material double-gate MOSFET

We have developed a two-dimensional analytical model for the channel potential, threshold voltage, and drain-to-source current of a symmetric double-halo gate-stacked triple-material double-gate metal–oxide–semiconductor field-effect transistor (MOSFET). The two-dimensional Poisson’s equation is solved to obtain the channel potential. For accurate modeling of the device, fringing capacitance and effective surface charge are considered. The basic drift–diffusion equation is used to model the drain-to-source current. The midchannel potential of the device is used instead of the surface potential in the current modeling, considering the fact that the punch-through current is not confined only to the surface in a fully depleted MOSFET. An expression for the pinch-off voltage is derived to model the drain current in the saturation region accurately. Various short-channel effects such as drain-induced barrier lowering, gate leakage, threshold voltage, and roll-off have also been investigated. This structure shows excellent ability to suppress various short-channel effects. The results of the proposed model are validated against data obtained from a commercially available numerical device simulator.     

Electrostatic characterization and threshold voltage modeling of inversion type InGaAs gate-all-around MOSFET

Journal of Computational Electronics - This paper presents an analytical investigation of the electrostatic properties of a moderately doped symmetric gate-all-around nanowire MOSFET having InGaAs...     

Analysis of independent gate operation in Si nano tube FET and threshold prediction model using 3D numerical simulation

In this paper, silicon nanotube field effect transistors (SiNT-FETs) are investigated for independent gate operation using 3D numerical simulation. The parameters, \(\mathrm{I_{ON} , I_{OFF}, V_{T}}\), and the unity gain cut-off frequency \(\mathrm{(f_{T}}\)) are studied in the independent-gate mode. The SiNT-FET we have considered has two gates, namely outer and inner gates, and can be simultaneously driven or independently driven. The physical gate oxide thicknesses of the outer and inner gates of the device are to be converted into effective gate oxide thicknesses due to the non-Euclidean geometry associated with the tube structure. The effective gate oxide thicknesses are different for the same outer and inner physical gate oxide thickness. Since the inner and outer gates are asymmetric, the device parameters extracted at the outer and inner gates are different. Since the independent gate operation allows dynamic threshold voltage adjustment, a model to predict the threshold voltage also known as the threshold voltage sensitivity model is developed for the SiNT device by modifying the double gate FinFET model. These models are verified by TCAD simulation results to validate their accuracy.     

Modeling the threshold voltage of PNIN SSOI tunnel field‐effect transistor

In this paper, a physically based analytical threshold voltage model for PNIN strained‐silicon‐on‐insulator tunnel field‐effect transistor (PNIN SSOI TFET) is proposed by solving the two‐dimensional (2D) Poisson equation in narrow N⁺ layer and intrinsic region. In the proposed model, the effect of strain (in terms of equivalent Ge mole fraction), narrow N⁺ layer and gate dielectric, and so on, is being considered. The validity of the proposed model is verified by comparing the model results with 2D device simulation results. It is demonstrated that the proposed model can correctly predicts the trends in threshold voltage with varying the device parameters. This proposed model can be effectively used to design, simulate, and fabricate the PNIN SSOI TFETs with the desired performance. Copyright © 2015 John Wiley & Sons, Ltd.     

Extraction and modeling methods for FET devices

The proposed method is based on spline functions, takes into account thermal and noise effects, allows a scaling of different FET device geometries, and is available in commercial CAD software like Agilents Series IV or ADS     

Comprehensive approach to modeling threshold voltage of nanoscale strained silicon SOI MOSFETs

A comprehensive approach for modeling the threshold voltage of nanoscale strained silicon-on-insulator (SSOI) and strained Si-on-SiGe-on-insulator (SSGOI) MOSFETs is presented. The model includes the effect of strain in terms of Ge mole fraction and various other device parameters—channel length, channel doping, strained silicon film thickness, gate oxide thickness and gate work function. The accuracy of the proposed threshold voltage model is verified using two-dimensional numerical simulations. We have also demonstrated that our model can accurately predict the DIBL effects.     

EE-BESD: molecular FET modeling for efficient and effective nanocomputing design

Molecular transistor is a good candidate as substitute of CMOS device due to small size, expected good performance and suitability to be included in high density-circuits. To date a lot of effort has been carried out to understand the conduction properties in molecular devices. However, minor effort has been devoted to reduce their computational complexity to obtain a compact molecular model. First-principle based methods frequently used are highly computational demanding for a single device, thus they are not suitable for complex circuit design. In this paper we present an accurate and at the same time computationally efficient method (named Efficient and Effective model based on Broadening level, Evaluation of peaks, SCF and discrete levels, ee-besd) to calculate the electron transport characteristics of molecular transistors in presence of applied bias and gate voltages. The results obtained show a remarkable improvement in terms of computational time with respect to existing approaches, while maintaining a very good accuracy. Finally, the ee-besd model has been embedded in a circuit level simulator in order to show its functionalities and, particularly, its computational cost. This is shown to be affordable even for circuits based on a high number of devices.     

GaN-based double-gate (DG) sub-10-nm MOSFETs: effects of gate work function

Double-gate (DG) metal–oxide–semiconductor field-effect transistors (MOSFETs) with GaN channel material are very promising for use in future high-performance low-power nanoscale device applications. In this work, GaN-based sub-10-nm DG-MOSFETs with different gate work function, \(\varPhi \), were designed and their performance evaluated. Short-channel effects (SCEs) were significantly reduced by introduction of gates made of dual metals. Use of gold at the source side, having higher \(\varPhi \) (\(\varPhi _{\mathrm{Au}}=5.11\,\hbox {eV}\)) compared with aluminum (\(\varPhi _{\mathrm{Al}}=4.53\,\hbox {eV}\)), at the drain side enhanced the gate control over the channel and screened the effect of the drain on the channel. Dual-metal (DM) DG-MOSFETs showed better results in the nanoscale regime and were more robust to SCEs. Therefore, GaN-based sub-10-nm DM DG-MOSFETs are suitable candidates for use in future complementary metal–oxide–semiconductor (CMOS) technology.     

Analytical modeling of threshold voltage for symmetrical silicon nano-tube field-effect-transistors (Si-NT FETs)

In this paper, an analytical model of the threshold voltage for short-channel symmetrical silicon nano-tube field-effect-transistors (Si-NT FETs) is presented. The three-dimensional (3D) Poisson equation in cylindrical coordinates has been solved with suitable boundary conditions to find the surface potential along the channel length. The inversion charge density \((Q_{inv} )\) has been calculated in the channel region of the device in the subthreshold regime of device operation, using the Boltzmann relationship. Subsequently, the calculated inversion charge density \((Q_{inv} )\) has been equated to a threshold charge density \((Q_{th})\) in order to find the threshold voltage \((V_{th})\) expression. The effect of physical device parameters, including the tube thickness, on the threshold voltage and drain induced barrier lowering (DIBL) of the device has been discussed. The model results have been verified with the simulation data obtained by the device simulation software ATLAS.     

Study on induced work-function variation of titanium metal gate on various electrical parameters for delta-doped layer germanium source vertical tunnel FET

Journal of Computational Electronics - Workfunction variation (WFV) in a high-k/titanium metal gate stack vertical tunnel field-effect transistor (FET) with a delta-doped layer in the germanium...     

Threshold voltage modeling for dual‐metal quadruple‐gate (DMQG) MOSFETs

In this paper, a three‐dimensional (3D) model of threshold voltage is presented for dual‐metal quadruple‐gate metal‐oxide‐semiconductor field effect transistors. The 3D channel potential is obtained by solving 3D Laplace's equation using an isomorphic polynomial function. Threshold voltage is defined as the gate voltage, at which the integrated charge (Q_inv) at the ‘virtual‐cathode’ reaches to a critical charge Q_th. The potential distribution and the threshold voltage are studied with varying the device parameters like gate metal work functions, channel cross‐section, oxide thickness, and gate length ratio. Further, the drain‐induced barrier lowering has also been analyzed for different gate length ratios. The model results are compared with the numerical simulation results obtained from 3D ATLAS device simulation results. Copyright © 2015 John Wiley & Sons, Ltd.     

A study of threshold voltage fluctuations of nanoscale double gate metal-oxide-semiconductor field effect transistors using quantum correction simulation

In this paper, we computationally investigate fluctuations of the threshold voltage introduced by random dopants in nanoscale double gate metal-oxide-semiconductor field effect transistors (DG MOSFETs). To calculate variance of the threshold voltage of nanoscale DG MOSFETs, a quantum correction model is numerically solved with the perturbation and the monotone iterative techniques. Fluctuations of the threshold voltage resulting from the random dopant, the gate oxide thickness, the channel film thickness, the gate channel length, and the device width are calculated. Quantum mechanical and classical results have similar prediction on fluctuations of the threshold voltage with respect to different designing parameters including dimension of device geometry as well as the channel doping. Fluctuation increases when the channel doping, the channel film thickness, and/or the gate oxide thickness increase. On the other hand, it decreases when the channel length and/or the device width increase. Calculations of the quantum correction model are quantitatively higher than that of the classical estimation according to different quantum confinement effects in nanoscale DG MOSFETs. Due to good channel controllability, DG MOSFETs possess relatively lower fluctuation, compared with the fluctuation of single gate MOSFETs (less than a half of the fluctuation[-11pc] of SG MOSFETs). To reduce fluctuations of the threshold voltage, epitaxial layers on both sides of channel with different epitaxial doping are introduced. For a certain thickness of epitaxial layers, the fluctuation of the threshold voltage decreases when epitaxial doping decreases. In contrast to conventional quantum Monte Carlo approach and small signal analysis of the Schrödinger-Poisson equations, this computationally efficient approach shows acceptable accuracy and is ready for industrial technology computer-aided design application.     

Compact 2D modeling and drain current performance analysis of a work function engineered double gate tunnel field effect transistor

The ongoing trend of device dimension miniaturization is attributed to a large extent by the development of several non-conventional device structures among which tunneling field effect transistors (TFETs) have attracted significant research attention due to its inherent characteristics of carrier conduction by built-in tunneling mechanism which in turn mitigates various short channel effects (SCEs). In this work, we have, incorporated the innovative concept of work function engineering by continuously varying the mole fraction in a binary metal alloy gate electrode along the horizontal direction into a double gate tunneling field effect transistor (DG TFET), thereby presenting a new device structure, a work function engineered double gate tunneling field effect transistor (WFEDG TFET). We have presented an explicit analytical surface potential modeling of the proposed WFEDG TFET by the solving the 2-D Poisson’s equation. From the surface potential expression, the electric field has been derived which has been utilized to formulate the expression of drain current by performing rigorous integration on the band-to-band tunneling generation rate over the tunneling region. Based on this analytical modeling, an overall performance comparison of our proposed WFEDG TFET with its normal DG TFET counterpart has been presented in this work to establish the superiority of our proposed structure in terms of surface potential and drain current characteristics. Analytical results have been compared with SILVACO ATLAS device simulator results to validate our present model.     

MOSFET linearity performance degradation subject to drain and gate voltage stress

Device parameters degradation of nonlinear elements subject to drain and gate voltage stress is examined experimentally. Analysis of metal-oxide-semiconductor field-effect transistor linearity degradation due to stress is given. Effects on radio frequency (RF) circuit linearity are investigated systematically through a SpectreRF simulation based on measured device data.     

3D analytical modeling of surface potential,threshold voltage,and subthreshold swing in dual-material-gate (DMG) SOI FinFETs

Here, we develop a 3D analytical model for potential in a lightly doped dual-material-gate FinFET in the subthreshold region. The model is based on the perimeter-weighted sum of a dual-material double-gate (DMDG) asymmetric MOSFET and a DMDG symmetric MOSFET. The potential model is used to determine the minimum surface potential needed to obtain the threshold voltage \((V_{\mathrm{T}})\) and subthreshold swing (SS) by considering the source barrier changes in the leakiest channel path. The proposed model is capable of reducing the drain-induced barrier lowering (DIBL) as well as the hot carrier effects offered by this device. The impact of control gate ratio and work function difference between the two metal gates on \(V_{\mathrm{T}}\) and SS are also correctly established by the model. All model derivations are validated by comparing the results with technology computer-aided design (TCAD) simulation data.     

Potential‐based threshold voltage and subthreshold swing models for junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with dual‐material gate

On the basis of quasi‐two‐dimensional solution of Poisson's equation, an analytical threshold voltage model for junctionless dual‐material double‐gate (JLDMDG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is developed for the first time. The advantages of JLDMDG MOSFET are proved by comparing the central electrostatic potential and electric field distribution with those of junctionless single‐material double‐gate (JLSMDG) MOSFET. The proposed model explicitly shows how the device parameters (such as the silicon thickness, oxide thickness, and doping concentration) affect the threshold voltage. In addition, the variations of threshold voltage roll‐off, drain‐induced barrier lowering (DIBL), and subthreshold swing with the channel length are investigated. It is proved that the device performance for JLDMDG MOSFET can be changed flexibly by adjusting the length ratios of control gate and screen gate. The model is verified by comparing its calculated results with those obtained from three‐dimensional numerical device simulator ISE. Copyright © 2015 John Wiley & Sons, Ltd.     

Dielectric pocket double gate junctionless FET: a new MOS structure with improved subthreshold characteristics for low power VLSI applications

In this paper, we report the TCAD based simulation of a new double-gate junctionless FETs (DG-JLFETs) structure incorporating dielectric pockets (DPs) at the source and drain ends. The proposed structure not only improves the ON to OFF drain current ratio (by \({\sim }\)900 %), subthreshold swing characteristics (by \({\sim }\)12 %) and Drain Induced Barrier Lowering (DIBL) (by \({\sim }\)56 %) over the conventional DG-JLFETs (i.e. without DPs), but also provides additional flexibility of performance optimization of the device by changing the length and thickness of the DPs. Since only little work has been carried out on the performance optimization of the JLFETs, the present work is believed to be very useful for designing the low-power VLSI circuits using DP-DG JLFETs with improved performance.     

中压电力线信道的仿真与建模

电力线通信具有其自身的特点,利用中压电力线进行通信具有广泛的应用前景;中压电力线信道的特性对于通信的实现有着重要的影响;根据测量结果,结合传输线的基本模型,利用Matlab软件对中压电力线信道进行了仿真模拟,为研究克服电力线信道恶劣传输特性的信号处理方法提供了参考。