A comprehensive two dimensional analytical study of a nanoscale linearly graded binary metal alloy gate cylindrical junctionless MOSFET for improved short channel performance

Over the years, the approach of cylindrical gate MOSFETs has attracted several research initiatives due to the very inherent benefit of the cylindrical geometry over other conventional planar structures. Nowadays, the present boon in the research field of nanoscale device physics is attributed to a large extent by the development of junctionless devices. In our current research endeavor, we have for the first time proposed a new idea by incorporating the innovative concept of work function engineering by the continuous horizontal variation of mole fraction in a binary metal alloy gate into a junctionless cylindrical gate MOS structure, thereby presenting a new device structure, a junctionless work function engineered gate cylindrical gate MOSFET (JL WFEG CG MOSFET). We have presented a rigorous analytical modeling of the proposed JL WFEG CG MOS structure by solving the two dimensional Poisson’s equation in cylindrical co-ordinates. Based on this analytical modeling, an overall performance comparison of the proposed JL WFEG CG MOS and normal JL CG MOS structure has been investigated in order to testify the improved performance of the proposed JL WFEG CG structure over its normal JL CG equivalent in terms of reduced short channel effects, threshold voltage roll off, drain induced barrier lowering and superior current driving capability. The results obtained from our analytical analysis are found to be in good agreement with the simulation results, thereby establishing the accuracy of our modeling.     

A novel high-performance H-gate U-channel junctionless FET

A novel high-performance H-shape-gate U-shape-channel junctionless FET (HGUC JL FET) is proposed. Compared with the saddle junctionless FET, the proposed HGUC JL FET shows better subthreshold characteristics and higher on-current. Its electrical properties were extensively investigated by studying the influence of variation of design parameters such as the H-gate thickness, the source/drain extension region height, and the gate oxide thickness and material. Compared with conventional structures, the proposed HGUC JL FET shows better performance, especially on scaling down to several nanometers. The reverse leakage current is also effectively restrained and the \({I}_{\mathrm{on}}\)/\({I}_{\mathrm{off}}\) ratio greatly improved through design optimization.     

Analysis and modeling of unipolar junction transistor with excellent performance: a novel DG MOSFET with $${N}^{+}{-}{P}^{-}$$ junction

We propose herein a new dual-gate metal–oxide–semiconductor field-effect transistor (MOSFET) with just a unipolar junction (UJ-DG MOSFET) on the source side. The UJ-DG MOSFET structure is constructed from an \({N}^{+}\) region on the source side with the rest consisting of a \({P}^{-}\) region over the gate and drain, forming an auxiliary gate over the drain region with appropriate length and work function (named A-gate), converting the drain to an \({N}^{+}\) region. The new structure behaves as a MOSFET, exhibiting better efficiency than the conventional double-gate MOSFET (C-DG MOSFET) thanks to the modified electric field. The amended electric field offers advantages including improved electrical characteristics, reliability, leakage current, \({I}_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio, gate-induced drain leakage, and electron temperature. Two-dimensional analytical models of the surface potential and electric field over the channel and drain are applied to investigate the drain current in the UJ-DG MOSFET. To confirm their accuracy, the MOSFET characteristics obtained using the 2D Atlas simulator for the UJ-DG and C-DG are analyzed and compared.     

Impact of channel length,gate insulator thickness,gate insulator material,and temperature on the performance of nanoscale FETs

Aggressive technology scaling as per Moore’s law has led to elevated power dissipation levels owing to an exponential increase in subthreshold leakage power. Short channel effects (SCEs) due to channel length reduction, gate insulator thickness change, application of high-k gate insulator, and temperature change in a double-gate metal–oxide–semiconductor field-effect transistor (DG MOSFET) and carbon nanotube field-effect transistor (CNTFET) were investigated in this work. Computational simulations were performed to investigate SCEs, viz. the threshold voltage (V_th) roll-off, subthreshold swing (SS), and I_on/I_off ratio, in the DG MOSFET and CNTFET while reducing the channel length. The CNTFET showed better performance than the DG MOSFET, including near-zero SCEs due to its pure ballistic transport mechanism. We also examined the threshold voltage (V_th), subthreshold swing (SS), and I_on/I_off ratio of the DG MOSFET and CNTFET with varying gate insulator thickness, gate insulator material, and temperature. Finally, we handpicked almost similar parameters for both the CNTFET and DG MOSFET and carried out performance analysis based on the simulation results. Comparative analysis of the results showed that the CNTFET provides 47.8 times more I_on/I_off ratio than the DG MOSFET. Its better control over the threshold voltage, near-zero SCEs, high on-current, low leakage power consumption, and ability to operate at high temperature make the CNTFET a viable option for use in enhanced switching applications and low-voltage digital applications in nanoelectronics.     

Simulation study on deep nanoscale short channel junctionless SOI FinFETs with triple-gate or double-gate structures

In this paper, both the forward and reverse characteristics of junctionless (JL) FinFETs with deep nanoscale design parameters have been studied through TCAD device simulation by considering band-to-band tunneling. Design optimization of the JL TG FinFETs has been performed by investigating the influence of the variations of design parameters such as body doping, channel length, body thickness, fin height and gate oxide thickness. The performance difference between the DG and TG JL FinFETs also has been compared by considering the structure difference. The scheme of device optimization has been proposed.     

Device circuit co‐design to reduce gate leakage current in VLSI logic circuits in nano regime

In this paper, nanoscale metal–oxide–semiconductor field‐effect transistor (MOSFET) device circuit co‐design is presented with an aim to reduce the gate leakage curren t in VLSI logic circuits. Firstly, gate leakage current is modeled through high‐k spacer underlap MOSFET (HSU MOSFET). In this HSU MOSFET, inversion layer is induced in underlap region by the gate fringing field through high‐k dielectric (high‐k) spacer, and this inversion layer in the underlap region acts as extended source/drain region. The analytical model results are compared with the two‐dimensional Sentaurus device simulation. Good agreement is obtained between the model and Sentaurus simulation. It is observed that modified HSU MOSFET had improved off current, subthreshold slope, and drain‐induced barrier lowering characteristics. Further, modified HSU MOSFET is also analyzed for gate leakage in generic logic circuits. Copyright © 2015 John Wiley & Sons, Ltd.     

Design and structural optimization of junctionless FinFET with Gaussian-doped channel

A junctionless (JL) fin field-effect transistor (FinFET) structure with a Gaussian doping distribution, named the Gaussian-channel junctionless FinFET, is presented. The structure has a nonuniform doping distribution across the device layer and is designed with the aim of improving the mobility degradation caused by random dopant fluctuations in JL FinFET devices. The proposed structure shows better performance in terms of ON-current (\(I_{\mathrm{ON}}\)), OFF-current (\(I_{\mathrm{OFF}}\)), ON-to-OFF current ratio (\(I_{\mathrm{ON}}{/}I_{\mathrm{OFF}}\)), subthreshold swing, and drain-induced barrier lowering. In addition, we optimized the structure of the proposed design in terms of doping profile, spacer width, gate dielectric material, and spacer dielectric material.     

Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behavior of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended source/drain region. It is found that optimal source/drain-to-gate non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and drain induced barrier lowering characteristic with a slight degradation in source/drain series resistance and effective gate capacitance.     

Monte Carlo analysis of dynamic characteristics and high‐frequency noise performances of nanoscale double‐gate MOSFETs

In this paper, a full‐band Monte Carlo simulator is employed to study the dynamic characteristics and high‐frequency noise performances of a double‐gate (DG) metal–oxide–semiconductor field‐effect transistor (MOSFET) with 30 nm gate length. Admittance parameters (Y parameters) are calculated to characterize the dynamic response of the device. The noise behaviors of the simulated structure are studied on the basis of the spectral densities of the instantaneous current fluctuations at the drain and gate terminals, together with their cross‐correlation. Then the normalized noise parameters (P, R, and C), minimum noise figure (NF_min), and so on are employed to evaluate the noise performances. To show the outstanding radio‐frequency performances of the DG MOSFET, a single‐gate silicon‐on‐insulator MOSFET with the same gate length is also studied for comparison. The results show that the DG structure provides better dynamic characteristics and superior high‐frequency noise performances, owing to its inherent short‐channel effect immunity, better gate control ability, and lower channel noise. Copyright © 2012 John Wiley & Sons, Ltd.     

Graded channel doping junctionless MOSFET: a potential high performance and low power leakage device for nanoelectronic applications

In this paper, a graded channel doping paradigm is proposed to improve the nanoscale double gate junctionless DGJL MOSFET electrical performance. A careful mechanism study based on numerical investigation and a performance comparison between the proposed and conventional design is carried out. The device figures-of-merit, governing the switching and leakage current behavior are investigated in order to reveal the transistor electrical performance for ultra-low power consumption. It is found that the channel doping engineering feature has a profound implication in enhancing the device electrical performance. Moreover, the impact of the high-k gate dielectric on the device leakage performance is also analyzed. The results show that the proposed design with gate stacking demonstrates superior \(I_{{\textit{ON}}}/I_{{\textit{OFF}}}\) ratio and lower leakage current as compared to the conventional counterpart. Our analysis highlights the good ability of the proposed design including a high-k gate dielectric for the reduction of the leakage current. These characteristics underline the distinctive electrical behavior of the proposed design and also suggest the possibility for bridging the gap between the high derived current capability and low leakage power. This makes the proposed GCD-DGJL MOSFET with gate stacking a potential alternative for high performance and ultra-low power consumption applications.     

Explicit modelling of the double‐gate MOSFET with VHDL‐AMS

This paper presents a new compact model for the undoped, long‐channel double‐gate (DG) MOSFET under symmetrical operation. In particular, we propose a robust algorithm for computing the mobile charge density as an explicit function of the terminal voltages. It allows to greatly reduce the computation time without losing any accuracy. In order to validate the analytical model, we have also developed the 2D simulations of a DG MOSFET structure and performed both static and dynamic electrical simulations of the device. Comparisons with the 2D numerical simulations give evidence for the good behaviour and the accuracy of the model. Finally, we present the VHDL‐AMS code of the DG MOSFET model and related simulation results. Copyright © 2006 John Wiley & Sons, Ltd.     

Analytical modeling and simulation of a linearly graded binary metal alloy gate nanoscale cylindrical MOSFET for reduced short channel effects

In the present era of miniaturization and low power devices, the approach of cylindrical gate MOS structure is in vogue among the researchers for enhancing the performance of nanoscale MOSFETs due to the inherent advantage of the cylindrical geometry compared to the conventional planar structures. In this work, for the first time, the innovative concept of work function engineering by the continuous horizontal variation of mole fraction in a binary metal alloy gate has been incorporated in a cylindrical MOS and a new structure, the work function engineered gate cylindrical gate MOSFET (WFEG CG MOSFET) has been proposed. A detailed analytical modeling of this novel WFEG CG MOS structure has been presented based on the solution of two dimensional Poisson’s equation in cylindrical coordinates. An overall performance comparison of the WFEG CG MOS and normal CG MOSFET has been investigated to establish the superiority of the proposed WFEG structure over its normal CG counterpart in terms of increased immunity against short channel effects, reduced value of drain induced barrier lowering and enhanced current driving capability. The results of our analytical modeling are found to be in good agreement with the simulation results, thereby establishing the accuracy of our modeling.     

Electrostatic discharge effects in ultrathin gate oxide MOSFETs

The effects of destructive and nondestructive electrostatic discharge (ESD) events applied either to the gate or drain terminal of MOSFETs with ultrathin gate oxide, emulating the occurrence of an ESD event at the input or output IC pins, respectively, were investigated. The authors studied how ESD may affect MOSFET reliability in terms of time-to-breakdown (TTBD) of the gate oxide and degradation of the transistor electrical characteristics under subsequent electrical stresses. The main results of this paper demonstrate that ESD stresses may modify the MOSFET current driving capability immediately after stress and during subsequent accelerated stresses but do not affect the TTBD distributions. The damage introduced by ESD in MOSFETs increases when the gate oxide thickness is reduced.     

Quantum correction for DG MOSFETs

The characteristics of modern semiconductor devices are strongly influenced by quantum mechanical effects. Due to this fact, purely classical device simulation is not sufficient to accurately reproduce the device behavior. For instance, the classical semiconductor equations have to be adapted to account for the quantum mechanical decrease of the carrier concentration near the gate oxide. Several available quantum correction models are derived for devices with one single inversion layer and are therefore only of limited use for thin double gate (DG) MOSFETs where the two inversion layers interact. We present a highly accurate quantum correction model which is even valid for extremely scaled DG MOSFET devices. Our quantum correction model is physically based on the bound states that form in the Si film. The eigenenergies and expansion coefficients of the wave functions are tabulated for arbitrary parabolic approximations of the potential in the quantum well. Highly efficient simulation of DG MOSFET devices scaled in the decananometer regime in TCAD applications is made possible by this model.     

大电流下SiC MOSFET模块的暂态温度特性研究

由于碳化硅(SiC)的材料特性,在极端温度下,碳化硅金属氧化物半导体场效应晶体管(SiC MOSFET)相对传统硅基器件有突出优势。目前对SiC MOSFET暂态温度特性的研究,主要以单管小电流实验为主,大电流下暂态温度特性的研究还不充分。为分析和验证大电流下暂态温度这一特性,在理论分析的基础上,以CREE 1200 V/300 A半桥SiC MOSFET模块为研究对象,通过双脉冲测试平台研究SiC MOSFET模块及其驱动电路在不同温度环境下的暂态性能。对比分析了不同温度下开关时间、开关损耗、电应力及电流、电压过冲的差异,实验结果对SiC MOSFET模块在大电流下的选型和驱动设计具有一定的参考意义。     

Junctionless MOSFETs with laterally graded-doping channel for analog/RF applications

In this paper, we propose a laterally graded-channel pseudo-junctionless (GPJL) MOSFET for analog/RF applications. We examine the dynamical performance of GPJL MOSFET and compare it with the common junctionless (JL) MOSFET architecture using a 2-D full-band electron Monte Carlo simulator (MC) with quantum correction. Our results indicate that the GPJL MOSFET outperforms the conventional JL MOSFET, yielding higher values of drain current (I _ds), transconductance (g _m), and cutoff frequency (f _t). Further, the emerging electric field and velocity distributions, as a consequence of the channel engineering introduced by the GPJL MOSFET, result in lower output conductance (g _ds) and higher early voltage (V _ea). The preeminence of the GPJL transistor over the JL transistor is further illustrated by showing improvements on the intrinsic voltage gain (A _vo) in the subthreshold regime, to as high as 61 %. These results indicate that our proposed GPJL MOSFET yields improvement in the analog/RF performance metrics as compared to JL MOSFETs.     

Characteristics and utilization of a new class of low on-resistanceMOS-gated power device

A new class of MOS-gated power semiconductor devices Cool MOS (Cool MOS is a trademark of Infineon Technologies, Germany) has been introduced with a supreme conducting characteristic that overcomes the high on-state resistance limitations of high-voltage power MOSFETs. From the application point of view, a very frequently asked question immediately arises: does this device behave like a MOSFET or an insulated gate bipolar transistor (IGBT)? The goal of this paper is to compare and contrast the major similarities and differences between this device and the traditional MOSFET and IGBT. In this paper, the new device is fully characterized for its: (1) conduction characteristics; (2) switching voltage, current, and energy characteristics; (3) gate drive resistance effects; (4) output capacitance; and (5) reverse-bias safe operating areas. Experimental results indicate that the conduction characteristics of the new device are similar to the MOSFET but with much smaller on-resistance for the same chip and package size. The switching characteristics of the Cool MOS are also similar to the MOSFET in that they have fast switching speeds and do not have a current tail at turn-off. However, the effect of the gate drive resistance on the turn-off voltage rate of rise (dv/dt) is more like an IGBT. In other words, a very large gate drive resistance is required to have a significant change on dv/dt, resulting in a large turn-off delay. Overall, the device was found to behave more like a power MOSFET than like an IGBT     

Shielded channel double-gate MOSFET: a novel device for reliable nanoscale CMOS applications

In this paper, the unique features exhibited by a novel double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) in which the front gate consists of two side gates to 1) electrically shield the channel region from any drain voltage variation and 2) act as an extremely shallow virtual extension to the source/drain are presented. This structure exhibits significantly reduced short-channel effects (SCEs) when compared with the conventional DG MOSFET. Using two-dimensional (2-D) and two-carrier device simulation, the improvement in device performance focusing on threshold voltage dependence on channel length, electric field in the channel, subthreshold swing, and hot carrier effects, all of which can affect the reliability of complementary metal oxide semiconductor (CMOS) devices, was investigated.     

Effect of layout parasitics on the current distribution of power MOSFETs operated at high switching frequency

The internal electrical characteristics of an 800-V 9-A 0.7-Ω silicon power MOSFET are investigated using a distributed modelling approach. A cad tool has been developed to automatically extract layout parasitics and create an equivalent spice-like netlist of the device under investigation. The distributed model is employed to investigate the performance of the device during a turn-off switching at different values of the gate fall time. Simulations show that reducing the gate fall time contributes to increase the internal current imbalance leading to current density overshoots, referred to as hot spots. Moreover, faster switching operation forces current density to crowd towards the slowest parts of the device which in turn degrades the overall device ruggedness. These results demonstrate that the proposed modelling approach allows accurate simulation of the internal current distribution identifying the regions where hot spots are more likely to occur.     

Si IGBT/SiC MOSFET混合器件及其应用研究

综述了Si IGBT/SiC MOSFET混合器件在门极优化控制策略、集成驱动设计、热电耦合损耗模型、芯片尺寸配比优化和混合功率模块研制等方面的最新研究成果与进展。Si IGBT/SiC MOSFET混合器件结合了SiC MOSFET的高开关频率、低开关损耗特性和Si IGBT的大载流能力和低成本优势,已有文献的最新研究和实验结果验证了该类器件的优异特性,表明其对高性能电力电子器件实现更高电流容量、更高开关频率和较低成本具有重要意义,是高性能变换器应用中非常有潜力的功率器件类型。