Quantum analysis based extraction of frequency dependent intrinsic and extrinsic parameters for GEWE-SiNW MOSFET

This paper examines the bias-independent and bias-dependent extrinsic and intrinsic parameters of the gate electrode workfunction engineered (GEWE) silicon nanowire (SiNW) metal–oxide–semiconductor field-effect transistor (MOSFET) by considering quantum effects. The results reveal that the effect of extrinsic parameters such as the resistance, capacitance, and inductance of the electrodes is less pronounced in the GEWE-SiNW compared with the conventional SiNW or conventional MOSFET. The intrinsic transconductance of the GEWE-SiNW device can be further improved by tuning the gate metal workfunction difference, which results in shorter time constant and lower parasitic capacitance, making it suitable for radiofrequency integrated circuit (RFIC) design. It is also observed that, in the saturation region, the device exhibits improved transconductance and noticeable reduction in \(C_{\mathrm{sdx}}\) [due to drain-induced barrier lowering (DIBL)] but the parasitic capacitance and time constant also reduce. In addition, a non-quasi-static small-signal model has been studied in terms of Z and Y parameters; the results show good agreement with the results of three-dimensional (3D) simulations at thousands of GHz.     

Performance enhancement of recessed silicon channel double gate junctionless field-effect-transistor using TCAD tool

In this paper, we propose an n-type double gate junctionless field-effect-transistor using recessed silicon channel. The recessed silicon channel reduces the channel thickness between the underlap regions, results in lowering the number of charge carriers in the silicon channel, and therefore, diminishing the OFF-current in the device. The proposed device shows similar electrical characteristics with improved transconductance, as compared to the conventional double gate junctionless field-effect-transistor. The effect of channel length scaling on the performance have been investigated, and it has been found that the recessed junctionless device shows higher ON-to-OFF current ratio, lower subthreshold swing and better immunity against the short channel effects, namely threshold voltage roll-off and drain-induced-barrier-lowering. For a channel length of 20 nm the OFF-current of the order of 1.20?×?10^–14 A/µm, ON-to-OFF current ratio of the order of 6.01?×?10¹⁰, subthreshold swing of the value of 67 mV/dec, and DIBL of 37.8 mV V^?1 has been achieved with the proposed junctionless device, in comparison of conventional double gate junctionless FET. The performance of proposed device with respect to the variations in depth and length of recessed silicon area, has also been presented as a roadmap for further tuning of its electrical behaviour. Comparatively, steeper DC transfer characteristics and improved rail-to-rail swing in transient behaviour has been reported with the designed complementary metal–oxide–semiconductor inverter, based on recessed double gate junctionless FET. The proposed recessed silicon channel double gate junctionless field-effect-transistor has been simulated using TCAD tool.

     

Effect of temperature on elasticity of P doped silicon nanowires

A semi-continuum approach is developed for mechanical analysis of a Phosphorus (P) doped silicon nanowire. Young's modulus of the silicon (001) nanowire with different size along [100] direction is obtained by the developed semi-continuum approach. The results show that Young's modulus of the P doped silicon nanowire decreases dramatically as the size of the width and thickness scaling down. The approach is extended to perform a mechanical analysis of the silicon nanowire at finite temperature. The dependence of young's modulus of the P doped silicon nanowire on temperature is predicted, and it exhibits a negative temperature coefficient.     

A study of threshold voltage fluctuations of nanoscale double gate metal-oxide-semiconductor field effect transistors using quantum correction simulation

In this paper, we computationally investigate fluctuations of the threshold voltage introduced by random dopants in nanoscale double gate metal-oxide-semiconductor field effect transistors (DG MOSFETs). To calculate variance of the threshold voltage of nanoscale DG MOSFETs, a quantum correction model is numerically solved with the perturbation and the monotone iterative techniques. Fluctuations of the threshold voltage resulting from the random dopant, the gate oxide thickness, the channel film thickness, the gate channel length, and the device width are calculated. Quantum mechanical and classical results have similar prediction on fluctuations of the threshold voltage with respect to different designing parameters including dimension of device geometry as well as the channel doping. Fluctuation increases when the channel doping, the channel film thickness, and/or the gate oxide thickness increase. On the other hand, it decreases when the channel length and/or the device width increase. Calculations of the quantum correction model are quantitatively higher than that of the classical estimation according to different quantum confinement effects in nanoscale DG MOSFETs. Due to good channel controllability, DG MOSFETs possess relatively lower fluctuation, compared with the fluctuation of single gate MOSFETs (less than a half of the fluctuation[-11pc] of SG MOSFETs). To reduce fluctuations of the threshold voltage, epitaxial layers on both sides of channel with different epitaxial doping are introduced. For a certain thickness of epitaxial layers, the fluctuation of the threshold voltage decreases when epitaxial doping decreases. In contrast to conventional quantum Monte Carlo approach and small signal analysis of the Schrödinger-Poisson equations, this computationally efficient approach shows acceptable accuracy and is ready for industrial technology computer-aided design application.     

Performance analysis of fully depleted triple material surrounding gate (TMSG) SOI MOSFET

In this paper, analytical model for threshold voltage is derived for fully depleted Triple material Surrounding gate (TMSG) SOI MOSFET. Three gate material of different work functions are introduced in the SOI MOSFET structure to reduce the short channel effects. The two dimensional Poisson equation is solved and based on parabolic approximation method, the model for threshold voltage is developed. The threshold voltage is analyzed for device parameters such as gate length ratios, oxide thickness, silicon thickness, doping concentration. The results of the analytical model values are validated using MEDICI simulation.     

A dopingless gate-all-around (GAA) gate-stacked nanowire FET with reduced parametric fluctuation effects

This paper proposes a gate-all-around silicon nanowire dopingless field-effect transistor (FET), utilizing a gate-stacked technique. The source and drain regions are formed by employing a charge plasma concept, with the application of appropriate work functions for metal contacts. The charge plasma approach reduces the need for doping control during fabrication, and thus reduces the thermal budget, while the gate-stacked structure solves the problem of scaling limitations with respect to the \(\hbox {SiO}_{2}\) dielectric thickness (< 2 nm). The simulation results show that the proposed device, when compared with a conventional junctionless nanowire FET (JL-NWFET), possesses enhanced performance parameters, with improved immunity to short-channel effects. The random dopant fluctuations (RDFs) of the proposed device are analyzed and compared with those of a conventional JL-NWFET. The conventional device has a high doping concentration, and as a result suffers from higher RDFs, whereas the proposed dopingless device possesses lower RDFs. The process parameters used to measure sensitivity to RDFs include the radius, doping concentration and gate oxide thickness. When the radius of the nanowire is varied by \(+\) 30%, changes in threshold voltage, on-state current and subthreshold slope of 66, 63 and 12%, respectively, are observed in the JL-NWFET, versus 5, 22.6 and 1.8% for the proposed dopingless device (CP-NWFET). Similar variations in doping concentration and gate oxide thickness are seen with the JL-NWFET, whereas the CP-NWFET is largely unaffected. Thus, the proposed gate-stacked dopingless CP-NWFET solves the issue of both doping control and scaling limitation of the gate oxide layer, which paves the way for easier fabrication, with exceptional immunity against parametric variations, making it a good candidate for future nanoscale devices.     

Comprehensive approach to modeling threshold voltage of nanoscale strained silicon SOI MOSFETs

A comprehensive approach for modeling the threshold voltage of nanoscale strained silicon-on-insulator (SSOI) and strained Si-on-SiGe-on-insulator (SSGOI) MOSFETs is presented. The model includes the effect of strain in terms of Ge mole fraction and various other device parameters—channel length, channel doping, strained silicon film thickness, gate oxide thickness and gate work function. The accuracy of the proposed threshold voltage model is verified using two-dimensional numerical simulations. We have also demonstrated that our model can accurately predict the DIBL effects.     

Potential‐based threshold voltage and subthreshold swing models for junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with dual‐material gate

On the basis of quasi‐two‐dimensional solution of Poisson's equation, an analytical threshold voltage model for junctionless dual‐material double‐gate (JLDMDG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is developed for the first time. The advantages of JLDMDG MOSFET are proved by comparing the central electrostatic potential and electric field distribution with those of junctionless single‐material double‐gate (JLSMDG) MOSFET. The proposed model explicitly shows how the device parameters (such as the silicon thickness, oxide thickness, and doping concentration) affect the threshold voltage. In addition, the variations of threshold voltage roll‐off, drain‐induced barrier lowering (DIBL), and subthreshold swing with the channel length are investigated. It is proved that the device performance for JLDMDG MOSFET can be changed flexibly by adjusting the length ratios of control gate and screen gate. The model is verified by comparing its calculated results with those obtained from three‐dimensional numerical device simulator ISE. Copyright © 2015 John Wiley & Sons, Ltd.     

Analytical subthreshold current and subthreshold swing models of short-channel dual-metal-gate (DMG) fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs

In this paper, analytical subthreshold current and subthreshold swing models are derived for the short-channel dual-metal-gate (DMG) fully-depleted (FD) recessed-source/ drain (Re-S/D) SOI MOSFETs considering that diffusion is the dominant current flow mechanism in subthreshold regime of the device operation. The two-dimensional (2D) channel potential is derived in terms of back surface potential and other device parameters. The so called virtual cathode potential in term of the minimum of back surface potential is also derived from 2D channel potential. The virtual cathode potential based subthreshold current and surface potential based subthreshold swing model results are extensively analyzed for various device parameters like the oxide and silicon thicknesses, thickness of source/drain extension in the BOX, control to screen gate length ratio and channel length. The numerical simulation results obtained from ATLAS \(^{\text{ TM }}\) , a 2D numerical device simulator from SILVACO Inc have been used as a tool to verify the model results.     

Effect of elastic processes and ballistic recovery in silicon nanowire transistors

Scaling of silicon devices is fast approaching the limit where a single gate may fail to retain effective control over the channel region. Of the alternative device structures under focus, silicon nanowire transistors (SNWT) show great promise in terms of scalability, performance, and ease of fabrication. Here we present the results of self-consistent, fully 3D quantum mechanical simulations of SNWTs to show the role of surface roughness (SR) and ionized dopant scattering on the transport of carriers. We find that the addition of SR, in conjunction with impurity scattering, causes additional quantum interference which increases the variation of the operational parameters of the SNWT. However, we also find that quantum interference and elastic processes can be overcome to obtain nearly ballistic behavior in devices with preferential dopant configurations.     

A compact interband tunneling current model for Gate-on-Source/Channel SOI-TFETs

A tunneling probability-based drain current model for tunnel field-effect transistors (FETs) is presented. First, an analytical model for the surface potential and the potential at the channel–buried oxide interface is derived for a Gate-on-Source/Channel silicon on insulator (SOI)-tunnel FET (TFET), considering the effect of the back-gate voltage. Next, a drain current model is derived for the same device by using the tunneling probability at the source–channel junction. The proposed model includes physical parameters such as the gate oxide thickness, buried oxide thickness, channel thickness, and front-gate oxide dielectric constant. The proposed model is used to investigate the effects of variation of the front-gate voltage, drain voltage, back-gate voltage, and front-gate dielectric thickness. Moreover, a threshold voltage model is developed and the drain-induced barrier lowering (DIBL) is calculated for the proposed device. The effect of bandgap narrowing is considered in the model. The model is validated by comparison with Technology Computer-Aided Design (TCAD) simulation results.     

Physics-based drain current modeling of gate-all-around junctionless nanowire twin-gate transistor (JN-TGT) for digital applications

Vertically stacked dielectric separated independently controlled gates can be used to realize dual-threshold voltage on a single silicon channel MOS device. This approach significantly reduces the effective layout area and is similar to merging two transistors in series. This multiple independent gate device enables the design of new class of compact logic gates with low power and reduced area. In this paper, we present the junctionless concept based twin gate transistor for digital applications. To analyse the appropriate behaviour of device, this paper presents the modeling, simulation and digital overview of novel gate-all-around junctionless nanowire twin-gate transistor for advanced ultra large scale integration technology. This low power single MOS device gives the full functionality of “AND” gate and can be extended to full functionality of 2-input digital “NAND” gate. To predict accurate behaviour, a physics based analytical drain current model has been developed which also includes the impact of gate depleted source/drain regions. The developed model is verified using ATLAS 3D device simulator. This single channel device can function as “NAND” gate even at low operating voltage.     

Bias and geometry optimization of FinFET for RF stability performance

This paper presents RF stability of FinFET at particular bias and geometry conditions. The article provides guideline for optimizing the FinFET at RF range. The FinFET geometrical parameters such as gate spacer length, height of silicon fin, and thickness of silicon fin along with gate material work function and bias conditions are adjusted to optimize the device for better stability performance at RF range. The critical frequency (f _k ) is obtained for different bias and geometry conditions using numerical simulation. The result shows that the optimized FinFET exhibits good RF stability performance.     

Threshold voltage modeling for dual‐metal quadruple‐gate (DMQG) MOSFETs

In this paper, a three‐dimensional (3D) model of threshold voltage is presented for dual‐metal quadruple‐gate metal‐oxide‐semiconductor field effect transistors. The 3D channel potential is obtained by solving 3D Laplace's equation using an isomorphic polynomial function. Threshold voltage is defined as the gate voltage, at which the integrated charge (Q_inv) at the ‘virtual‐cathode’ reaches to a critical charge Q_th. The potential distribution and the threshold voltage are studied with varying the device parameters like gate metal work functions, channel cross‐section, oxide thickness, and gate length ratio. Further, the drain‐induced barrier lowering has also been analyzed for different gate length ratios. The model results are compared with the numerical simulation results obtained from 3D ATLAS device simulation results. Copyright © 2015 John Wiley & Sons, Ltd.     

Monte Carlo analysis of dynamic characteristics and high‐frequency noise performances of nanoscale double‐gate MOSFETs

In this paper, a full‐band Monte Carlo simulator is employed to study the dynamic characteristics and high‐frequency noise performances of a double‐gate (DG) metal–oxide–semiconductor field‐effect transistor (MOSFET) with 30 nm gate length. Admittance parameters (Y parameters) are calculated to characterize the dynamic response of the device. The noise behaviors of the simulated structure are studied on the basis of the spectral densities of the instantaneous current fluctuations at the drain and gate terminals, together with their cross‐correlation. Then the normalized noise parameters (P, R, and C), minimum noise figure (NF_min), and so on are employed to evaluate the noise performances. To show the outstanding radio‐frequency performances of the DG MOSFET, a single‐gate silicon‐on‐insulator MOSFET with the same gate length is also studied for comparison. The results show that the DG structure provides better dynamic characteristics and superior high‐frequency noise performances, owing to its inherent short‐channel effect immunity, better gate control ability, and lower channel noise. Copyright © 2012 John Wiley & Sons, Ltd.     

Fringing-field-based 2-D analytical model for a gate-underlap double-gate TFET

An analytical model was developed to calculate the potential distribution for a gate-underlap double-gate tunnel FET. The electrostatic potential of the device was derived using the two-dimensional Poisson’s equation, incorporating the fringing electric field in the gate-underlap surface and employing a conformal mapping method. In addition to analytical potential modeling, the electric field and drain current were evaluated to investigate the device performance. Excellent agreement with technology computer-aided design (TCAD) simulation results was observed. The dependence of the ambipolar current on the spacer oxide dielectric constant, spacer length, channel length, and gate material thickness was examined using the proposed model. The effects of the variation of all of these parameters were well predicted, and the model reveals that use of a low-\(\kappa \) spacer dielectric combined with a high-\(\kappa \) gate dielectric results in the minimal ambipolar current for the device.     

Simulation study on deep nanoscale short channel junctionless SOI FinFETs with triple-gate or double-gate structures

In this paper, both the forward and reverse characteristics of junctionless (JL) FinFETs with deep nanoscale design parameters have been studied through TCAD device simulation by considering band-to-band tunneling. Design optimization of the JL TG FinFETs has been performed by investigating the influence of the variations of design parameters such as body doping, channel length, body thickness, fin height and gate oxide thickness. The performance difference between the DG and TG JL FinFETs also has been compared by considering the structure difference. The scheme of device optimization has been proposed.     

Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET)

In this paper we examined the short channel behavior of junction less tunnel field effect transistor (JLTFET) and a comparison was made with the conventional MOSFET on the basis of variability of device parameter. The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. The JLTFET exhibits an improved subthreshold slope (SS) of 24 mV/decade and drain-induced barrier lowering (DIBL) of 38 mV/V as compared to SS of 73 mV/decade and DIBL of 98 mV/V for the conventional MOSFET. The simulation result shows that the impact of length scaling on threshold voltage for JLTFET is very less as compared to MOSFET. Even a JLTFET with gate length of 10 nm has better SS than MOSFET with gate length of 25 nm, which enlightens the superior electrostatic integrity and better scalability of JLTFET over MOSFET.     

Impact of Strain or Ge Content on the Threshold Voltage of Nanoscale Strained-Si/SiGe Bulk MOSFETs

The impact of strain on the threshold voltage of nanoscale strained-Si/SiGe MOSFETs is studied by developing a compact analytical model. Our model includes the effects of strain (Ge mole fraction in SiGe substrate), short-channel length, source/drain junction depths, substrate (body) doping, strained silicon thin-film thickness, gate work function, and other device parameters. The model correctly predicts a decrease in threshold voltage with increasing strain in the silicon thin film, i.e., with increasing Ge concentration in SiGe substrate. The accuracy of the results obtained using our analytical model is verified using two-dimensional device simulations.     

A 3D analytical modeling of tri-gate tunneling field-effect transistors

In this paper, a three-dimensional (3D) analytical solution of the electrostatic potential is derived for the tri-gate tunneling field-effect transistors (TG TFETs) based on the perimeter-weighted-sum approach. The model is derived by separating the device into a symmetric and an asymmetric double-gate (DG) TFETs and then solving the 2D Poisson’s equation for these structures. The subthreshold tunneling current expression is extracted by numerical integrating the band-to-band tunneling generation rate over the volume of the device. It is shown that the potential distributions, the electric field profile, and the tunneling current predicted by the analytical model are in close agreement with the 3D device simulation results without the need of fitting parameters. Additionally, the dependence of the tunneling current on the device parameters in terms of the gate oxide thickness, gate dielectric constant, channel length, and applied drain bias is investigated and also demonstrated its agreement with the device simulations.