Quantum Simulation Study of a New Carbon Nanotube Field-Effect Transistor With Electrically Induced Source/Drain Extension

In this paper, we present the unique features exhibited by a proposed structure of coaxially gated carbon nanotube field-effect transistor (CNTFET) with doped source and drain extensions using the self-consistent and atomistic scale simulations, within the nonequilibrium Green's function formalism. In this novel CNTFET structure, three adjacent metal cylindrical gates are used, where two side metal gates with lower workfunction than the main gate as an extension of the source/drain on either side of the main metal gate are biased, independent of the main gate, to create virtual extensions to the source and the drain and also to provide an effective electrical screen for the channel region from the drain voltage variations. We demonstrate that the proposed structure of CNTFET shows improvement in device performance focusing on leakage current, on–off current ratio, and voltage gain. In addition, the investigation of short-channel effects for the proposed structure shows improved drain-induced barrier lowering, hot-carrier effect, and subthreshold swing, all of which can affect the reliability of CMOS devices.      

Shielded channel double-gate MOSFET: a novel device for reliable nanoscale CMOS applications

In this paper, the unique features exhibited by a novel double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) in which the front gate consists of two side gates to 1) electrically shield the channel region from any drain voltage variation and 2) act as an extremely shallow virtual extension to the source/drain are presented. This structure exhibits significantly reduced short-channel effects (SCEs) when compared with the conventional DG MOSFET. Using two-dimensional (2-D) and two-carrier device simulation, the improvement in device performance focusing on threshold voltage dependence on channel length, electric field in the channel, subthreshold swing, and hot carrier effects, all of which can affect the reliability of complementary metal oxide semiconductor (CMOS) devices, was investigated.     

Physics-based drain current modeling of gate-all-around junctionless nanowire twin-gate transistor (JN-TGT) for digital applications

Vertically stacked dielectric separated independently controlled gates can be used to realize dual-threshold voltage on a single silicon channel MOS device. This approach significantly reduces the effective layout area and is similar to merging two transistors in series. This multiple independent gate device enables the design of new class of compact logic gates with low power and reduced area. In this paper, we present the junctionless concept based twin gate transistor for digital applications. To analyse the appropriate behaviour of device, this paper presents the modeling, simulation and digital overview of novel gate-all-around junctionless nanowire twin-gate transistor for advanced ultra large scale integration technology. This low power single MOS device gives the full functionality of “AND” gate and can be extended to full functionality of 2-input digital “NAND” gate. To predict accurate behaviour, a physics based analytical drain current model has been developed which also includes the impact of gate depleted source/drain regions. The developed model is verified using ATLAS 3D device simulator. This single channel device can function as “NAND” gate even at low operating voltage.     

Investigation of multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) sub‐50 nm MOSFET: A novel design

In this paper, a two‐dimensional (2D) analytical sub‐threshold model for a novel sub‐50 nm multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO₂‐based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain‐induced barrier lowering, sub‐threshold drain current and sub‐threshold swing. Results reveal that MLGEWE‐RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high‐speed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd.     

An analytic drain current model for long‐channel undoped gate stack surrounding‐gate MOSFETs including interface fixed charges

On the basis of the exact solution of Poisson's equation and Pao–Sah double integral for long‐channel bulk MOSFETs, a continuous and analytic drain current model for the undoped gate stack (GS) surrounding‐gate (SRG) metal–oxide–semiconductor field‐effect transistor (MOSFET) including positive or negative interface fixed charges near the drain junction is presented. Considering the effect of the interface fixed charges on the flat‐band voltage and the electron mobility, the model, which is expressed with the surface and body center potentials evaluated at the source and drain ends, describes the drain current from linear region to saturation region through a single continuous expression. It is found that the surface and body center potentials are increased/decreased in the case of positive/negative interface fixed charges, respectively, and the positive/negative interface fixed charges can decrease/increase the drain current. The model agrees well with the 3D numerical simulations and can be efficiently used to explore the effects of interface fixed charges on the drain current of the gate stack surrounding‐gate MOSFETs of the charge‐trapped memory device. Copyright © 2013 John Wiley & Sons, Ltd.     

Study of fluctuations in advanced MOSFETs using a 3D finite element parallel simulator

Two important new sources of fluctuations in nanoscaled MOSFETs are the polysilicon gates and the introduction of high-κ gate dielectrics. Using a 3D parallel drift-diffusion device simulator, we study the influence of the polycrystal grains in polysilicon and in the high-κ dielectric on the device threshold for MOSFETs with gate lengths of 80 and 25 nm. We model the surface potential pinning at the grain boundaries in polysilicon through the inclusion of an interfacial charge between the grains. The grains in the high-κ gate dielectric are distinguished by different dielectric constants. We have found that the largest impact of the polysilicon grain boundary in the 80 nm gate length MOSFET occurs when it is positioned perpendicular to the current flow. At low drain voltage the maximum impact occurs when the grain boundary is close to the middle of the gate. At high drain voltage the impact is stronger when the boundary is moved toward the source end of the channel. Similar behaviour is observed in the 25 nm gate length MOSFET.     

Analysis and modeling of unipolar junction transistor with excellent performance: a novel DG MOSFET with $${N}^{+}{-}{P}^{-}$$ junction

We propose herein a new dual-gate metal–oxide–semiconductor field-effect transistor (MOSFET) with just a unipolar junction (UJ-DG MOSFET) on the source side. The UJ-DG MOSFET structure is constructed from an \({N}^{+}\) region on the source side with the rest consisting of a \({P}^{-}\) region over the gate and drain, forming an auxiliary gate over the drain region with appropriate length and work function (named A-gate), converting the drain to an \({N}^{+}\) region. The new structure behaves as a MOSFET, exhibiting better efficiency than the conventional double-gate MOSFET (C-DG MOSFET) thanks to the modified electric field. The amended electric field offers advantages including improved electrical characteristics, reliability, leakage current, \({I}_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio, gate-induced drain leakage, and electron temperature. Two-dimensional analytical models of the surface potential and electric field over the channel and drain are applied to investigate the drain current in the UJ-DG MOSFET. To confirm their accuracy, the MOSFET characteristics obtained using the 2D Atlas simulator for the UJ-DG and C-DG are analyzed and compared.     

GaN-based double-gate (DG) sub-10-nm MOSFETs: effects of gate work function

Double-gate (DG) metal–oxide–semiconductor field-effect transistors (MOSFETs) with GaN channel material are very promising for use in future high-performance low-power nanoscale device applications. In this work, GaN-based sub-10-nm DG-MOSFETs with different gate work function, \(\varPhi \), were designed and their performance evaluated. Short-channel effects (SCEs) were significantly reduced by introduction of gates made of dual metals. Use of gold at the source side, having higher \(\varPhi \) (\(\varPhi _{\mathrm{Au}}=5.11\,\hbox {eV}\)) compared with aluminum (\(\varPhi _{\mathrm{Al}}=4.53\,\hbox {eV}\)), at the drain side enhanced the gate control over the channel and screened the effect of the drain on the channel. Dual-metal (DM) DG-MOSFETs showed better results in the nanoscale regime and were more robust to SCEs. Therefore, GaN-based sub-10-nm DM DG-MOSFETs are suitable candidates for use in future complementary metal–oxide–semiconductor (CMOS) technology.     

A compact interband tunneling current model for Gate-on-Source/Channel SOI-TFETs

A tunneling probability-based drain current model for tunnel field-effect transistors (FETs) is presented. First, an analytical model for the surface potential and the potential at the channel–buried oxide interface is derived for a Gate-on-Source/Channel silicon on insulator (SOI)-tunnel FET (TFET), considering the effect of the back-gate voltage. Next, a drain current model is derived for the same device by using the tunneling probability at the source–channel junction. The proposed model includes physical parameters such as the gate oxide thickness, buried oxide thickness, channel thickness, and front-gate oxide dielectric constant. The proposed model is used to investigate the effects of variation of the front-gate voltage, drain voltage, back-gate voltage, and front-gate dielectric thickness. Moreover, a threshold voltage model is developed and the drain-induced barrier lowering (DIBL) is calculated for the proposed device. The effect of bandgap narrowing is considered in the model. The model is validated by comparison with Technology Computer-Aided Design (TCAD) simulation results.     

Performance optimization of BiCMOS circuits under reduced supply voltage

As the supply voltage is reduced, the speed superiority of BiCMOS over CMOS may be diminished, but BiCMOS still has the advantage of inducing relatively smaller characteristic degradation in nMOS transistors by suppressing the drain voltage in the gate. Introducing a new quantitative methodology to evaluate hot electron-induced degradation of nMOS transistor characteristics, this report finds that both BiNMOS gates and CBiMOS gates will have a considerable superiority over CMOS gates in the voltage range from 2.5 V to 3.3 V, even with the same nMOS transistor characteristics. BiNMOS is 30% faster than CMOS owing to amplification of the pMOS drain current by an npn transistor. CBiCMOS is 40% faster and has a sevenfold longer life than CMOS. The speed improvement comes from amplification of both pMOS and nMOS drain currents by npn and pnp transistors, respectively, and the lifetime improvement is due to the effect of the voltage drop through the pnp transistors on the drain terminal of the nMOS transistors. The analytical methodology was also utilized to choose an optimum drain structure, although CMOS necessitates the LDD (lightly doped drain), SD (single drain) structure. Thus, the speed of the gates can be further improved, and the speed of CBiCMOS is expected to be 45% faster than that of CMOS gates. Even in the case of SD structure, the lifetime of CBiCMOS was estimated to be two orders of magnitude longer than that of CMOS with LDD structure. © 1998 Scripta Technica. Electr Eng Jpn, 121(4): 56–64, 1997     

Leakage mitigation in NW FET using negative Schottky junction drain and its process variation analysis

Journal of Computational Electronics - In this work, a Schottky junction on the drain side employing low workfunction (WF) metal is proposed as a method to suppress the OFF-state leakage in...     

An analytical model of triple‐material double‐gate metal–oxide–semiconductor field‐effect transistor to suppress short‐channel effects

This paper presents an analytical subthreshold model for surface potential and threshold voltage of a triple‐material double‐gate (DG) metal–oxide–semiconductor field‐effect transistor. The model is developed by using a rectangular Gaussian box in the channel depletion region with the required boundary conditions at the source and drain end. The model is used to study the effect of triple‐material gate structure on the electrical performance of the device in terms of changes in potential and electric field. The device immunity against short‐channel effects is evaluated by comparing the relative performance parameters such as drain‐induced barrier lowering, threshold voltage roll‐off, and subthreshold swing with its counterparts in the single‐material DG and double‐material DG metal–oxide–semiconductor field‐effect transistors. The developed surface potential model not only provides device physics insight but is also computationally efficient because of its simple compact form that can be utilized to study and characterize the gate‐engineered devices. Furthermore, the effects of quantum confinement are analyzed with the development of a quantum‐mechanical correction term for threshold voltage. The results obtained from the model are in close agreement with the data extracted from numerical Technology Computer Aided Design device simulation. Copyright © 2015 John Wiley & Sons, Ltd.     

Full Quantum Mechanical Simulation of Ultra-Small Silicon Devices in Three-Dimensions: Physics and Issues

The combination of the need for alternative devices and the improvement in process technology has led to the examination of silicon quantum wires for future MOS technology. However, in order to properly model these devices, a full three-dimensional quantum mechanical treatment is required. In this paper, we present the results of a three-dimensional, fully quantum mechanical, self-consistent simulation of a silicon quantum wire MOSFET (Metal Oxide Field Effect Transistor) with a narrow channel (8 nm). A quasi-standing wave is formed in the narrow channel at certain gate voltages as the electron density is trapped in narrow channel. These effects are the result of two competing effects: (1) the interaction of the propagating electrons with the channel dopants, as well as with the dopants in the source and drain of the device. (2) the reflections from the boundaries that form the narrow channel both on the source side and the drain side.     

Threshold voltage modeling for dual‐metal quadruple‐gate (DMQG) MOSFETs

In this paper, a three‐dimensional (3D) model of threshold voltage is presented for dual‐metal quadruple‐gate metal‐oxide‐semiconductor field effect transistors. The 3D channel potential is obtained by solving 3D Laplace's equation using an isomorphic polynomial function. Threshold voltage is defined as the gate voltage, at which the integrated charge (Q_inv) at the ‘virtual‐cathode’ reaches to a critical charge Q_th. The potential distribution and the threshold voltage are studied with varying the device parameters like gate metal work functions, channel cross‐section, oxide thickness, and gate length ratio. Further, the drain‐induced barrier lowering has also been analyzed for different gate length ratios. The model results are compared with the numerical simulation results obtained from 3D ATLAS device simulation results. Copyright © 2015 John Wiley & Sons, Ltd.     

The effect of ITO and Mo electrodes on the properties and stability of In-Ga-Zn-O thin film transistors

The effect of ITO and Mo electrodes on the electrical properties and stability of In-Ga-Zn-O (IGZO) thin film transistors (TFTs) are investigated. While the field effect mobility values of the devices employing ITO and Mo electrodes are similar, the former exhibit smaller threshold voltage (V_th) and subthreshold swing (SS). It is suggested that the relatively large workfunction of Mo (4.7 eV) compared to that of ITO (4.4?~?4.5 eV) induces a large Schottky barrier at the Mo/IGZO junction, which prohibits the effective injection of electrons from the metal into the IGZO semiconductor. The workfunction of IGZO is usually reported to be approximately 4.5 eV. The device stability of the two types of TFTs under negative bias stress (NBS) and positive bias stress (PBS) is similar, which implies that the degradation of the devices under bias stress is mainly affected by the trapping of carriers at the IGZO/gate insulator interface. In the presence of illumination, the devices using optically transparent ITO electrodes allow the penetration of a more abundant concentration of photons into the IGZO active layer, and thus undergo larger V_th shifts under negative bias illumination stress (NBIS). However, under positive bias illumination stress (PBIS), the TFTs using ITO exhibit smaller positive V_th shifts. The latter phenomenon is suggested to result from the excess photo-induced electrons in the bulk that counter the effect of electron trapping near the IGZO/gate insulator boundary.     

Silicene field effect transistor with high on/off current ratio and good current saturation

We investigate theoretically the possibility of exploiting the electrically tunable band gap property of silicene to achieve field effect transistor with improved characteristics. We find that the silicene field effect transistor where a band gap is introduced through a perpendicular electric field shows a subthreshold swing smaller than 60 mV/decade and a switching effect with high on/off current ratio exceeding \(10^{5}\). We find also that the device output characteristic displays a very good saturation due to improved pinch-off of the channel, stemming from the electrically induced band gap.     

寄生电感对于功率MOSFET开关特性的影响

分散在MOSFET栅极、源极、漏极的寄生电感由于封装以及印制电路板（PCB）走线,改变了MOSFET的开关特性。通过仿真分析对比,指出MOSFET寄生电感存在如下特性：源极电感对栅极驱动形成负反馈,导致开关速度变慢,采用开尔文连接,可以将栅极回路与功率回路解耦,提高驱动速度;在米勒效应发生时刻需要合理地降低栅极电感来降低栅极驱动电流;漏极电感通过米勒电容影响MOSFET的开通速度,在关断时刻导致电压应力增加;在并联的回路当中,非对称的布局将导致MOSFET之间的动态不均流;当MOSFET在开关过程中,环路电感与MOSFET自身的结电容产生振荡时,可以在电路增加吸收电容减小环路电感,改变振荡特性。     

Dual material gate junctionless tunnel field effect transistor

This paper proposes a junctionless tunnel field effect transistor (JLTFET) with dual material gate (DMG) structure and the performance was studied on the basis of energy band profile modulation. The two-dimensional simulation was carried out to show the effect of conduction band minima on the abruptness of transition between the ON and OFF states, which results in low subthreshold slope (SS). Appropriate selection of work function for source and drain side gate metal of a double metal gate JLTFET can also significantly reduce the subthreshold slope (SS), OFF state leakage and hence gives improved I _ON/I _OFF.     

MOSFET开关过程的研究及米勒平台振荡的抑制

设计功率MOSFET驱动电路时需重点考虑寄生参数对电路的影响。米勒电容作为MOSFET器件的一项重要参数,在驱动电路的设计时需要重点关注。重点观察了MOSFET的开通和关断过程中栅极电压、漏源极电压和漏源极电流的变化过程,并分析了米勒电容、寄生电感等寄生参数对漏源极电压和漏源极电流的影响。分析了栅极电压在米勒平台附近产生振荡的原因,并提出了抑制措施,对功率MOSFET的驱动设计具有一定的指导意义。     

Numerical simulation of small silicon partially insulated MOSFETs

The scaling of conventional MOS bulk transistors with gate lengths below 100 nm seems to be difficult due to short channel effects. Especially the adjustment of the threshold voltage V _th is difficult because of the rapid drop down at shorter gate lengths. For low power consumption and high speed applications SOI technologies have been developed, but floating body effects, increasing leakage currents, kink phenomena and decreased heat dissipation occur in SOI-FETs. To combine the benefits of conventional and SOI-MOSFETs and to avoid the disadvantages, partially insulated FETs (Pi-FETs) with oxide regions under source and drain are candidates for scaling down the gate length into the deep submicron area [1–3, 5, 6]. We present the results of several numerical simulations to compare conventional bulk transistors, SOI-FETs and Pi-FETs in their static and dynamic behaviour.