共查询到18条相似文献,搜索用时 46 毫秒
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一种双频多层微带天线的设计与分析 总被引:1,自引:2,他引:1
分析并设计了一种双频多层微带天线。该天线采用上下双层贴片、三层介质基板结构和背部探针馈电,并使用电磁仿真软件HFSS 10.0对所设计的天线进行了仿真。分析仿真结果表明,该天线的工作频段为1.31~1.39GHz和1.86—1.94GHz,具有较宽的相对带宽,该天线可作为双频天线工作,并能工作在射频频段。 相似文献
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金属线宽与间距渐变的片上螺旋电感设计规则研究 总被引:1,自引:0,他引:1
在分析片上螺旋电感的磁场分布及射频损耗机制的基础上,研究了电感的金属线宽及线圈间距的变化对电感性能的影响,在大量数值分析基础上提出了金属线宽与间距之和不变,而金属线宽与间距之比从外圈到内圈逐渐减小的渐变型片上螺旋电感,并得到了实验验证,多组样品的测试结果与数值分析结果相吻合,以2.4 GHz频段处为例,在高阻硅衬底上制备的5 nH渐变结构电感的品质因子Q为11,比具有相同外径和电感值的固定金属线宽及间距的传统电感高19.6%. 相似文献
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采用磁控溅射生长磁膜工艺,结合BCB(苯并环丁烯)平坦化技术,首次制作了"金属线圈/磁膜/金属线圈(M/F/M)"和"磁膜/金属线圈/磁膜/金属线圈(F/M/F/M)"两种结构的多层磁膜电感,整个工艺与标准MMIC工艺兼容.在2 GHz处,"金属线圈/磁膜/金属线圈"结构电感的电感量为7.5 nH,品质因数为7.17,... 相似文献
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《电子元件与材料》2015,(11):73-77
提出了一种微带馈电式圆形微带天线设计方案,通过在辐射贴片表面加载月牙型缝隙,改变电流有效路径,实现多频特性。通过HFSS仿真分析缝隙形状对天线性能的影响。结果表明,天线工作的三个频段相对带宽分别为4.1%(2.39~2.49 GHz),3.98%(3.92~4.08 GHz)和3.75%(5.51~5.72 GHz)。其中低频和中频段的最高增益达到6.58d B和5.01 d B。天线尺寸为35 mm×52 mm,具有小体积、高增益、全向性良好的特点,能够应用于无线通信系统中,并且这种结构简单、参数少、多频段的设计方法为天线设计提供了新的途径。 相似文献
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为提高13.56 MHz RFID读写器天线的发射效率,并使其天线在实验室易于研发和试制,对13.56 MHz RFID天线系统的工作原理进行了简要介绍,在此基础上,把13.56 MHz RFID读写器天线线圈等效为PCB平面螺旋电感,利用HFSS软件建立模型并仿真得出电感值L、品质因子Q值等参数。其仿真结果得到的电感值与理论计算值相差0.03μH,在可接受的范围内。考虑到实际天线产生的寄生电容,提出了在天线末端加开路补偿线圈的方法,避免因寄生电容产生地电流而使天线线圈的磁场强度降低,仿真结果证实了该方法的可行性。 相似文献
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Dae-Hee Weon Jeong-Il Kim Saeed Mohammadi 《Analog Integrated Circuits and Signal Processing》2007,50(2):89-93
Design of 3-Dimensional micromachined inductors on high-(10 KΩ·cm) and low-resistivity(10 Ω·cm) Si substrate fabricated using stress metal technology we have developed [1, 2] is presented. Using high frequency electromagnetic simulation of 3-Dimensional inductors performed by Ansoft HFSS®, we have investigated the effects of number of turns, effective radius, metal line width, and different substrates on the quality factor, Q and self-resonant frequency, f sr of these inductors. We also have compared the simulated results with the measurement results of 3-D inductors fabricated using this technology. 相似文献
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Rasmus B. Andersen Thomas Jørgensen Søren Laursen Troels E. Kolding 《Analog Integrated Circuits and Signal Processing》2002,30(1):51-58
We used a 2.5D EM-simulator to study planar inductor performance in a submicron CMOS technology. We found good agreement between simulations and measurements using only the nominal process parameters for the layer thicknesses, permittivities, and conductivities. By sweeping the thickness and conductivity of the epitaxial layer we show how these parameters affect inductor performance. The presence of a highly conductive substrate layer is shown to have a detrimental effect on inductor performance whereas the thickness and conductivity of the epitaxial layer is less important. 相似文献
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A method to provide a low power tunable inductor is presented in which the inductance and its equivalent series resistance can be independently tuned. This equivalent series resistance can be also set to negative or zero value that is corresponding to inductor with ideal quality factor. In this method, a varactor is placed in parallel with a passive inductor and then, an active capacitor is placed in series with them. To this end, a low power Tunable Active Capacitor (TAC) is proposed which is capable of generating tunable capacitor and large negative resistance to compensate the loss of tunable inductor circuit. Also, the power consumption is low because of using a diode-connected transistor. A prototype of the proposed circuit is designed and simulated at 4 GHz. The electromagnetic simulation results show the inductance tuning range of 0.48–2.3nH with zero or even negative equivalent series resistance is obtained while the power dissipation is less than 3 mW. Moreover, noise analysis shows that higher inductance translates to lower noise while there is a weak correlation between noise and quality factor of the obtained inductances. 相似文献
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