Digital control of a voltage-mode synchronous buck converter

A digital control algorithm capable of separately specifying the desired output voltage and transient response for a synchronous buck converter operating in voltage mode was developed. This algorithm is based on superimposing a small control signal onto a voltage reference at each switching cycle to cancel out the perturbations. A zero steady-state error in the output voltage can be obtained with the aid of additional dynamics to allow the controller to track a load change and update the reference to a new load state. The specifications of the control algorithm are achieved by pole placement using complete state feedback. The control algorithm was implemented on a digital signal processor (DSP)-controlled synchronous buck converter.     

A miniature high-efficiency fully digital adaptive voltage scaling buck converter

A miniature high-efficiency fully digital adaptive voltage scaling (AVS) buck converter is proposed in this paper. The pulse skip modulation with flexible duty cycle (FD-PSM) is used in the AVS controller, which simplifies the circuit architecture (<170 gates) and greatly saves the die area and the power consumption. The converter is implemented in a 0.13-μm one-poly-eight-metal (1P8 M) complementary metal oxide semiconductor process and the active on-chip area of the controller is only 0.003 mm², which is much smaller. The measurement results show that when the operating frequency of the digital load scales dynamically from 25.6 MHz to 112.6 MHz, the supply voltage of which can be scaled adaptively from 0.84 V to 1.95 V. The controller dissipates only 17.2 μW, while the supply voltage of the load is 1 V and the operating frequency is 40 MHz.     

Reconfigurable digital controller for a buck converter based on FPGA

This paper presents a complete digitally controlled dc–dc buck converter performed by FPGA circuitry. All tasks, analog to digital conversion, control algorithm and pulse width modulation, were implemented in the FPGA. This approach enables high-speed dynamic response and programmability by the controller, without external passive components. In addition, the controller’s structure can be easily changed without external components. The applied algorithm enables a switching frequency of 100 kHz.     

DC-DC降压变换器的滑模控制研究

为更快获得比较理想的直流输出电压,优化Buck变换器的动态性能,本文分析了一种滑模控制器控制的直流-直流降压变换器,推导了描述降压变换器的动态方程,并设计了滑模控制器。通过MATLAB/Simulink进行仿真,仿真结果表明,基于滑模控制的降压转换器对负载变化和输入电压变化的有效性和鲁棒性。     

Wireless PWM control of a parallel DC-DC buck converter

We demonstrate a new concept for wireless pulse-width modulation (PWM) control of a parallel dc-dc buck converter. It eliminates the need for multiple physical connections of gating/PWM signals among the distributed converter modules. The new scheme relies on radio-frequency (RF) based communication of the PWM control signals from a master to the slave modules. We analyze the system stability and demonstrate the experimental effectiveness of the wireless control scheme for a two-module parallel buck converter for 10-kHz and 20-kHz switching frequencies and for channel lengths of 1.5 and 15ft, respectively. The proposed control concept may lead to easier distributed control implementation of parallel dc-dc converters and distributed power systems, and may lead to redundancy that is achievable using droop method. It may also be used as a backup for wire-based control of parallel converters to provide fault tolerance.     

Bifurcation behavior of the buck converter

The DC-DC buck power converter, a widely used chopper circuit, exhibits subharmonics and chaos if current feedback is used. This paper investigates the dependence of the system behavior on its parameters. The bifurcation phenomena and a mapping of the parameter space have been presented. This knowledge is vital for designing practical circuits     

Sliding mode control and stability analysis of buck DC-DC converter

This paper is proposed to deal with the voltage regulation of buck DC-DC converter based on sliding mode control (SMC) technology. A buck DC-DC converter with parasitic resistance is inherently a bilinear system possessing inevitable uncertainties, such as variable resistive load and input disturbance. First, the buck DC-DC converter is modified into an uncertain linear model. Then, SMC technology is adopted to suppress the input disturbance and reduce the effects from the load variation. In addition, the continuous conduction mode (CCM) for normal operation can be guaranteed by the design of sliding function. Finally, experimental results are included for demonstration.     

Dynamic hysteresis band control of the buck converter with fast transient response

A dynamic hysteresis control of the buck converter for achieving high slew-rate response to disturbances is proposed. The hysteresis band is derived from the output capacitor current that predicts the output voltage magnitude after a hypothesized switching action. Four switching criteria are formulated to dictate the state of the main switch. The output voltage can revert to the steady state in two switching actions after a large-signal disturbance. The technique is verified with the experimental results of a 50 W buck converter.     

多相buck转换器的新型电压滞环控制研究

随着处理器技术的发展,电压调节模块面临更高的要求,其主拓扑和控制方式也都有了很大的发展.交错技术能够以较低的开关频率实现高频输出电压波动、具有纹波互消、相间分流等优点,而电压滞环控制具有电路简单、无需反馈环路补偿、负载瞬态响应以及不限制开关导通时间等优点,因此二者的结合成为一种发展趋势.本文首先介绍了交错并联buck拓扑和电压滞环控制的工作原理,并进一步给出单纯电压滞环控制的buck转换器的仿真,阐述了其优缺点,此基础上提出了新型电压滞环控制方式,并对其工作原理进行了分析,最后通过仿真及实验验证了这种新型控制方式的优越性.     

Pseudo-V2 control with adaptive compensation for fast-transient current-mode buck converter

A type of pseudo-V² control, with on-chip adaptive compensation to achieve fast transient (FT) response for current mode DC–DC buck converter, has been proposed and simulated using 0.18 μm CMOS technology in this paper. Based on a new on-chip capacitor multiplier, adaptive compensation is achieved by making the compensation capacitance to track the load current. The proposed pseudo-V² control utilizes the output ripple to determine the duty cycle during load transient. Thus the overshoot/undershoot voltage and the transient recovery time are effectively reduced. Simulation results demonstrate the transient ripple is smaller than 50 mV and the transient recovery time is shorter than 10 μs for a 450 mA load current step. The maximum power conversion efficiency is 94.6% at 1 MHz switching frequency when input and output voltages are 5 V and 1.8 V, respectively.     

卫星电源控制系统结构和降压变换器仿真研究

对卫星电源系统控制结构进行介绍,比较了传统电源功率控制结构和改进结构的特点,并简要说明其控制方法,研究卫星电源系统中直流母线与负载间的降压变换器参数和控制策略设计过程,给出参数计算方法,通过Matlab软件仿真验证了所采用方法的正确性。     

Synthetic-ripple modulator for synchronous buck converter

Comprising a hysteretic comparator and a ripple synthesizer, the synthetic-ripple modulator (SRM) allows voltage-hysteretic modulation to be realized in low-voltage buck converters where the natural voltage ripple is too small for reliable hysteretic operation. Circuit implementation, steady-state operation, and design equations are described for an SRM controlling a buck dc-dc converter. The basics are verified experimentally by a buck converter switched at 420 kHz and delivering 10 A at 1.8 V.     

A buck converter with adaptive on-time PFM control and adjustable output voltage

This letter proposes a new adaptive on-time pulse-frequency modulation (PFM) circuit that operates at a wide range of supply voltage levels and that can generate various output voltage levels compared to conventional circuits. The circuit’s peak inductor current is well-controlled; the magnitude of the output ripple voltage is constant, even when the supply and output voltage levels are significantly different. Since the ripple voltage is a noise component, constant ripple voltage is important for predictable noise of a power management system.     

A high-efficiency fully digital synchronous buck converter power delivery system based on a finite-state machine

A fully digital, self-adjusting, and high-efficiency power supply system has been developed based on a finite-state machine (FSM) control scheme. The system dynamically monitors circuit performance with a delay line and provides a substantially constant minimum supply voltage for digital processors to properly operate at a given frequency. In addition, the system adjusts the supply voltage to the required minimum under different process, voltage, and temperature and load conditions. The design issues of the fully digital power delivery system are discussed and addressed. This digital FSM scheme significantly reduces the complexity of control-loop implementation (<1800 gates) and power consumption (< 100 /spl mu/W at 1.2 V) compared to other approaches based on proportional-integral-differential control. The power delivery control system is fabricated in a 0.13-/spl mu/m CMOS process and its core die size is 160 /spl times/ 110 /spl mu/m/sup 2/.     

一种新型软开关BUCK变换器

根据传统硬开关电源引起的不良影响,提出了一种新型软开关BUCK变换器,使得高低桥MOSFET管都能在不管是轻负载或者重负载情况下达到ZVS状态.在连续导电模式（CCM）和高负载电流情况下,上桥MOSFET管开通,下桥MOSFET管侧的二极管在死区时间内导电,这样就造成了上桥MOSFET管的开关损耗.新型软开关BUCK变换器在传统BUCK变换器的基础上加入了电感和电容,在外加电感电容的情况下,在CCM下的死区时间内的电感电流可以有效地从下桥二极管整流到上桥二极管中.根据仿真结果和工作模式分析验证其性能.     

Optimum buck converter with a single switch

A new DC-DC power converter with only one active switch operating at a constant switching frequency and with low-current and voltage stress is proposed. The conduction losses are minimized because of the ability to use a minimum number of elements in the path of direct energy transfer from the input to the load. Furthermore, because only one switch is used, the design of the control circuit is greatly simplified. The new power converter achieves soft switching for the diodes and zero-current switching (ZCS) at turn on for the active switch     

Tapped-inductor buck converter for high-step-down DC-DC conversion

The narrow duty cycle in the buck converter limits its application for high-step-down dc-dc conversion. With a simple structure, the tapped-inductor buck converter shows promise for extending the duty cycle. However, the leakage inductance causes a huge turn-off voltage spike across the top switch. Also, the gate drive for the top switch is not simple due to its floating source connection. This paper solves all these problems by modifying the tapped-inductor structure. A simple lossless clamp circuit can effectively clamp the switch turn-off voltage spike and totally recover the leakage energy. Experimental results for 12V-to-1.5V and 48V-to-6V dc-dc conversions show significant improvements in efficiency.     

A quadratic buck converter with lossless commutation

High switching frequency associated with soft commutation techniques is a new trend in switching converters. Following this trend, the authors present a buck pulsewidth modulation converter, where the DC voltage conversion ratio has a quadratic dependence on duty cycle, providing a large step-down. By introducing two resonant networks, soft switching is attained, providing highly efficient operating conditions for a wide load range at high switching frequency. Contrary to most of the converters that apply soft-switching techniques, the switches presented are not subjected to high switch voltage or current stresses and, consequently, present low conduction losses. The authors present, for this converter, the principle of operation, theoretical analysis, relevant equations and simulation and experimental results     

同步降压式DC-DC转换器的稳定性设计

DC-DC转换器因其相比于传统的线性稳压器具有较高的电源转换效率,而被广泛地应用到各种现代电子设备中。同时随着电源整流技术的不断进步,DC-DC转换器也正在从以肖特基二极管作为续流二极管的异步整流模式向同步整流模式转变。同步整流式DC-DC转换器具有极高的电源转换效率(可超过95%),是各种手持设备电源设计的首选。本文从分析同步降压式DC-DC转换器的闭环增益和相位曲线入手,研究了多种条件下如何实现同步降压式DC-DC转换器的稳定性设计。