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提出一种具有埋层低掺杂漏(BLD)SOI高压器件新结构。其机理是埋层附加电场调制耐压层电场,使漂移区电荷共享效应增强,降低沟道边缘电场,在漂移区中部产生新的电场峰。埋层电中性作用增加漂移区优化掺杂浓度,导通电阻降低;低掺杂漏区在漏极附近形成缓冲层,改善漏极击穿特性。借助二维半导体仿真器MEDICI,研究漂移区浓度和厚度对击穿电压的影响,获得改善击穿电压和导通电阻折中关系的途径。在器件参数优化理论的指导下,成功研制了700V的SOI高压器件。结果表明:BLD SOI结构击穿电压由均匀漂移区器件的204V提高到275V,比导通电阻下降25%。 相似文献
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为了降低绝缘体上硅(SOI)功率器件的比导通电阻,同时提高击穿电压,利用场板(FP)技术,提出了一种具有L型栅极场板的双槽双栅SOI器件新结构.在双槽结构的基础上,在氧化槽中形成第二栅极,并延伸形成L型栅极场板.漂移区引入的氧化槽折叠了漂移区长度,提高了击穿电压;对称的双栅结构形成双导电沟道,加宽了电流纵向传输面积,使比导通电阻显著降低;L型场板对漂移区电场进行重塑,使漂移区浓度大幅度增加,比导通电阻进一步降低.仿真结果表明:在保证最高优值条件下,相比传统SOI结构,器件尺寸相同时,新结构的击穿电压提高了123%,比导通电阻降低了32%;击穿电压相同时,新结构的比导通电阻降低了87.5%;相比双槽SOI结构,器件尺寸相同时,新结构不仅保持了双槽结构的高压特性,而且比导通电阻降低了46%. 相似文献
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提出了一种具有超低比导通电阻的L型栅漏极LDMOS器件。该器件在两个氧化槽中分别制作L型多晶硅槽栅。漏极n型重掺杂区向下延伸,与衬底表面重掺杂的n型埋层相接形成L型漏极。L型栅极不仅可以降低导通电阻,还具有纵向栅场板的特性,可有效改善表面电场分布,提高击穿电压。L型漏极为电流提供了低阻通路,降低了导通电阻。另外,氧化槽折叠漂移区使得在相同耐压下元胞尺寸及导通电阻减小。二维数值模拟软件分析表明,在漂移区长度为0.9 μm时,器件耐压达到83 V,比导通电阻仅为0.13 mΩ·cm2。 相似文献
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提出一种带p埋层的表面注入硅基LDMOS高压器件新结构,称为BSI LDMOS(surface implanted LDMOS with p buried layer).通过表面注入n 薄层降低导通电阻,p埋层不但改善横向表面电场分布,提高击穿电压,而且增大漂移区优化浓度.求解电势的二维Poisson方程,获得表面电场和击穿电压的解析式,研究结构参数对表面电场和击穿电压的影响,数值与解析结果吻合较好.结果表明:与常规结构相比较,BSI LDMOS大大改善了击穿电压和导通电阻的折衷关系. 相似文献
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A new BPSOI (buried layer partial SOI) structure is developed, in which the P-type buried layer is implanted into the P− substrate by silicon window underneath the source of the conventional PSOI. The mechanism of breakdown is that the additional electric field produced by P-type buried layer charges modulates surface electric field, which decreases drastically the electric field peaks near the drain and source junctions. Moreover, the on-resistance of BPSOI is decreased as a result of increasing drift region doping due to neutralism of P-type buried layer. The results indicate that the breakdown voltage of BPSOI is increased by 52–58% and the on-resistance is decreased by 45–48% in comparison to conventional PSOI in virtue of 2-D numerical simulations using MEDICI. 相似文献
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具有补偿埋层的槽型埋氧层SOI高压器件新结构 总被引:3,自引:3,他引:0
A new silicon-on-insulator(SOI) high-voltage MOSFET structure with a compensation layer on the trenched buried oxide layer(CL T-LDMOS) is proposed.The high density inverse interface charges at the top surface of the buried oxide layer(BOX) enhance the electric field in the BOX and a uniform surface electric field profile is obtained,which results in the enhancement of the breakdown voltage(BV).The compensation layer can provide additional P-type charges,and the optimal drift region concentration is increased in order to satisfy the reduced surface electric field(RESURF) condition.The numerical simulation results indicate that the vertical electric field in the BOX increases to 6 MV/cm and the B V of the proposed device increases by 300%in comparison to a conventional SOI LDMOS,while maintaining low on-resistance. 相似文献
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提出了一种具有n^+浮空层的横向superjunction结构,此结构通过磷或砷离子注入在高阻衬底上形成n^+浮空层来消除传统横向superjunction结构中的衬底辅助耗尽效应.这种效应来源于P型的衬底辅助耗尽了superjunction区的n型层,使P与n之间的电荷不能平衡,n^+层的REBULF效应通过使漏端电场减小,体电场重新分布而使新结构中的衬底承担了更多的电压,结果表明这种结构具有高的击穿电压、低的导通电阻和漂移区中电荷平衡的特点。 相似文献
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提出与CMOS工艺兼容的薄型双漂移区(TD)高压器件新结构.通过表面注入掺杂浓度较高的N-薄层,形成不同电阻率的双漂移区结构,改变漂移区电流线分布,降低导通电阻;沟道区下方采用P离子注入埋层来减小沟道区等位线曲率,在表面引入新的电场峰,改善横向表面电场分布,提高器件击穿电压.结果表明:TD LDMOS较常规结构击穿电压提高16%,导通电阻下降31%. 相似文献
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1200V MR D-RESURF LDMOS与BCD兼容工艺研究 总被引:1,自引:0,他引:1
提出具有p埋层的1200V多区双RESURF(MR D-RESURF) LDMOS, 在单RESURF(S-RESURF)结构的n漂移区表面引入多个p掺杂区,并在源区下引入p埋层,二者的附加场调制器件原来的场,以改善其场分布;同时由于电荷补偿,提高了漂移区n型杂质的浓度,降低了导通电阻.开发1200V高压BCD(BJT,CMOS,DMOS)兼容工艺,在标准CMOS工艺的基础上增加pn结对通隔离,用于形成DMOS器件D-RESURF的p-top注入两步工序,实现了BJT,CMOS与高压DMOS器件的单片集成.应用此工艺研制出一种BCD单片集成的功率半桥驱动电路,其中LDMOS,nMOS,pMOS,npn的耐压分别为1210,43.8,-27和76V.结果表明,此兼容工艺适用于高压领域的电路设计中. 相似文献
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A new high-voltage LDMOS with folded drift region(FDR LDMOS) is proposed. The drift region is folded by introducing the interdigital oxide layer in the Si active layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance. 相似文献
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