Radiation Effects Characterization of the SBP9900A 16-Bit Microprocessor

Characterization of the Texas Instruments SBP9900A 16-bit microprocessor has been performed in radiation environments. The test results indicate that the devices will remain functional at reduced electrical performance following exposures to ionizing radiation levels of 3×106rads(Si) or neutron fluences of 3×1013n/cm2. Transient logic upset was not observed at ionizing radiation dose rates of less than 1×109rads(Si)/sec. The primary failure mode in the neutron and total ionizing dose environments was found to be a reduction in up-gain of the npn portion of the I2L cell. Methods of enhancing the radiation hardness of the SBP9900A are discussed.     

Transient Radiation Response of Hardened CMOS/SOS Microprocessor and Memory Devices

Transient tests on rad-hard microprocessor and memory devices of CMOS/SOS design were carried out with the Boeing Linac as the electron pulse source of 40 ns duration. Mean temporary and permanent upset levels were determined to be 1.1×1010 and 1.3×1010 rads (Si)/s for the microprocessor, and 1.3×1010 and 5.1×1010 rads (Si)/s for the memory, respectively. All of these values correspond to the worst case exposure conditions which were found to be static rather than dynamic (i.e., a transition state). Storage pattern sensitivity for both device types during exposure was also determined to be a dominant-zero pattern, that is, a few ones in a field of zeroes in the case of the microprocessor, and a single one in a field of zeroes for the memory. Transient annealing measurements on the microprocessor indicated a recovery time of 20 ?s to 87% of VOH following a 27 kilorad dose/pulse for a 1.8 ?s electron pulse.     

Radiation Hardened Registers

The requirement for radiation hardened registers has been identified for use with existing digital equipment to assure system survivability in nuclear radiation environments. The major problem has been that all semiconductor registers cannot be guaranteed to maintain their information after ionizing radiation transients above 5×109 rads (Si)/sec. Two approaches are shown for designing microelectronic register circuits for increased transient immunity based on the use of temporary storage media: a magnetic circuit and a capacitor circuit. The operation of the circuits are described as well as the features which impart hardness to them. They are compatible with +5V, IC families of saturated logic and are proposed for use with these circuits for specific function hardening. The results of transient tests show the magnetic circuit to work through 107 rads(Si)/sec to 8 × 1010 rads(Si)/sec. The capacitor circuit tests went up as high as 5 × 1010 rads (Si)/sec. Laboratory simulation on the capacitor circuit (using shunting transistors to approximate the effect of the circuit's transistors storage times caused by radiation) indicates hardness to levels in excess of 5 x 1011 rads(Si)/sec.     

离子辐照GaAs的光致发光和拉曼散射研究

利用250 keV质子和4.5 MeV氪离子(Kr17+)辐照未掺杂GaAs,注量分别为1×10~(12)-3×10~(14) cm~(-2)和3×10~(11)-3×10~(14) cm~(-2),使用光致发光谱和拉曼散射谱分析表征。发光谱的结果表明,随着剂量增大,质子辐照后的CAs峰及其声子伴线逐渐减弱,913 nm处的复合缺陷峰则先增大后减小,此峰与材料制备时的Cu掺杂无关。Kr离子辐照后本征发光峰则完全消失。拉曼散射谱的结果表明,相比于质子辐照,Kr离子辐照后LO声子峰峰位向低频方向移动,出现非对称性展宽,晶体结构发生明显改变。质子和Kr离子辐照效应的差异是由于移位损伤相差至少三个量级造成的。最后采用多级损伤累积(Multi-step damage accumulation,MSDA)模型得到了材料内缺陷的演化过程,并很好地解释了随损伤剂量增大GaAs光学性能及晶体结构的变化趋势。     

Ionizing Radiation Effects on the Sperry Rand Nonvolatile 256-Bit MNOS Ram Array (SR2256)

Ionizing dose-rate and total dose tests have been performed on the Sperry Rand 256-MNOS (SR 2256) RAM array. Results from these tests have shown that the devices can survive dose-rate levels as high as 1.0 × 1012 Rad(Si)/sec (in a 2 MeV electron-beam environment) with no loss of memory data or permanent degradation in device operation. However, under certain test conditions, the "Read" and "Write" modes of the arrays can be temporarily interrupted. In the Read mode, this interruption can be induced at dose-rate levels of 4 × 108 Rads(Si)/sec and higher if the radiation burst is applied approximately 1 microsecond in time before the start of the "Data Output" signals. In the Write mode, disturb mechanism can be generated in a 2 MeV electron beam at dose-rate levels of 2.4 × 1011 Rad(Si)/sec and higher if the burst is applied at the start of the "Memory Enable" signal. Also, the total dose tests have shown that the memory arrays (while cycling through its operational modes at the maximum rates) can accumulate a total dose of gamma radiation in excess of 1 × 105 Rad(Si) and survive. At reduced cycle rates, the arrays can operate and survive up to 3 × 105 Rad(Si).     

Prevention of Radiation Induced Latchup in Commercially Available CMOS Devices

Commercially available bulk CMOS devices have been found susceptible to transient radiation induced latchup particularly when there is little or no current limiting in the power supply. A resistor in the power supply line of sufficient size to prevent latchup may cause excessive voltage drop when the device is operating dynamically. A series inductor in the power supply line does not have this drawback. An inductor-resistor-capacitor (LRC) network was developed to prevent latchup in HM-6551, 256×4 bit bulk CMOS random access memories (RAMs). The LRC network was successfully tested with single and multiple RAMs using a Febetron 705 in the x-ray mode at 1×1010 rad(Si)/s. The parametric values of the LRC network should be experimentally determined at the highest gamma dose rate required for system survivability. The technique should be cost effective even with this restriction.     

Dose and Dose Rate Dependence of 8080a Microprocessor Failures

The occurrence of transient upset and catastrophic failure in 8080A microprocessors was investigated over a dose-rate range of 6 × 10-4 to 3 × 10+10 rads/sec. The transient upset and catastrophic failure levels depended on both dose and dose-rate. For example, the dose at which catastrophic failure occurs is 10 times greater at the highest dose-rates investigated than at the lowest. Irradiation was performed using both low energy (45 kV x-ray tube, 200 kV flash x-ray source) and high energy (Co 60, Linac) sources. The observed transient upset and catastrophic failure levels were significantly higher for low energy irradiation than for high energy irradiation. These results have important implications for models of ionizing radiation effects in MOS devices.     

Effect of Ionizing Radiation on Gunn Diode Amplifiers

X-band Gunn diode amplifiers have been tested while exposed to pulsed ionizing radiation. Peak photo currents induced vary as the .65 power of the dose rate, as had been found for oscillator diodes. The principal effect is a transient loss of gain, with the recovery time less than 400 ns for dose rates up to 5×1010 rad (Si)/s. The dependence of gain on dose rate agrees very well with a calculation based on the change in electric field distribution caused by radiation-induced excess carriers. A permanent failure mode was also observed at the maximum operating voltage and dose rate.     

空间单粒子翻转甄别与定位系统原理样机的设计及试验

单粒子翻转（SEU）是影响空间电子设备可靠性的重要因素,本文提出了一种SEU甄别与定位技术方法,研制了原理样机。硅探测器与辐照敏感器件在垂直方向相互临近安装,粒子入射到硅探测器的位置区域与目标辐照器件单粒子翻转的物理位置相对应。采用波形数字化技术实现了多道粒子甄别与能量信号测量,通过数据回读比较法实现了SRAM器件翻转逻辑定位检测。根据实验室测试和单粒子辐照试验结果,可探测高能粒子的LET≥6?06×10-3 MeV·cm2/mg,入射粒子的位置分辨率优于5 mm,最大计数率≥10 000 s-1,SRAM器件的SEU巡检周期时间分辨率为13?76 ms。通过掌握大容量SRAM型器件的SEU甄别与定位及其辐射环境感知能力,有助于提升空间电子设备的在轨工作性能。     

稳态总剂量效应(TID)试验剂量率选择的研究

通过调研分析,发现ESA/SCC 22900和MIL-STD-883G方法1019.7在剂量率的选择等方面存在较大差异。针对美国宇航局NASA发布的TID试验报告中总剂量及其对应的剂量率值进行统计分析,了解到不同工艺器件进行TID试验时采取多步骤辐射,辐射过程中所选择的剂量率几乎均小于1rad(Si)/s,且剂量率随总剂量不断改变。当总剂量低于30krad(Si)时,曲线分布没有规律,随机性较大;当总剂量大于30krad(Si)时,剂量率随总剂量的增加而增加,但不满足线性关系。针对不同剂量率辐射后器件失效机理的分析研究,得出器件在低剂量率辐射下失效的主要原因是界面态,而在高剂量率辐射失效的主要原因是辐射感生氧化物陷阱电荷。     

Effect of 14 MeV Neutrons on Space-Charge-Limited Current of Electrons in High Purity Silicon

Alloyed and symmetrical n+?n+ devices made of nominally 75k?cm ?-type Si are analyzed before and after irradiation with 14MeV neutrons at room temperature and doses of 1.2×1011, 5.5×1011 and 4.0×1012n/cm2. Immediately after the application of a large turn-on voltage step at t ? O, the flow of electrons through these devices is by pure, trap free, space-charge-limited current (sclc). From an analysis of this sclc, it is established that the drift velocity-field relationship of electrons in Si is affected by the radiation only at low temperatures in the low field range. For t>0, the current after irradiation decays below its initial trap free sclc value, thus revealing the presence of traps. Two categories are identified: fast traps with energy levels at about ?Etf ? 0.13eV below the conduction band and slow traps with energy levels at roughly ?Ets?005eV. Cross sections are also obtained. Introduction rates are about equal for both (llcm-l for fast traps and 8cm-1 for slow traps). These results demonstrate the sensitivity of sclc as a tool to detect traps and changes in the drift velocityfield relationship caused by radiation. Some implications of these results are discussed and additional experiments are suggested.     

A Simple and Efficient Switched-Mode Approach to Hardened Power Amplification

A radiation-hardened power amplifier using switchedmode techniques to effect linear amplification is described. The amplifier--consisting of a modulator, saturating switches, and a demodulator--is capable of delivering more than 50 watts peak output at an efficiency exceeding 60 percent, before and after exposure to 3.5 × 1014 n/cm2 (l-MeV equiv.) and 2.0 × 106 rads(Si). The amplifier is immune to catastrophic effects of a pulsed ionizing-radiation environment of short duration through peak dose rates exceeding 1 × 1011 rads(Si)/s. The magnitude of the output response at this level is less than 9 percent of the maximum output voltage, and recovery from transient ionization takes place within one cycle of the amplifier's 3-db cutoff frequency.     

Recently Demonstrated Radiation Immunity of Symmetrical Cell I2L

A significant degree of radiation hardness has been achieved for I2L devices using symmetrical cell topologies. MSI complexity functions have been implemented with no degradation in device hardness from individual gate performance. Short pulse upset thresholds of 2×1010 Rad (Si)/sec and 1x1014 neutrons/cm2 fluence immunity have been demonstrated.     

Radiation Hardened CMOS/SOS

This paper reports the results of experiments designed to optimize the total dose ionizing radiation hardness of CMOS/SOS devices. Type 4007 inverter circuits were fabricated with variations in the process, including wet versus dry gate oxidation. Tolerable values (e. g. < l?A per mil of channel width) of post-radiation n-channel back leakage were obtained only with wet oxides. Threshold shifts of ?1V for the n-channel devices and ?2V for the p-channel devices were obtained after 106 rads (Si) on the best devices fabricated.     

A Comparison of Linac and 60Co Response of the CD4007UBE CMOS Inverter

The n-channel saturated threshold voltage shift of a complementary metal-oxide semiconductor (CMOS) inverter was measured as a function of average and peak dose rate irradiation derived from an electron linear accelerator (LINAC). At peak dose rates below 108 rad(Si)/s, the results are dose-rate-independent and comparable to those obtained using a steady-state 60Co source; at higher peak dose rates, less damage per unit dose was observed.     

The Damage Susceptibility of Integrated Circuits to a Simulated IEMP Transient

Recent investigations have been directed toward gaining insight into the effect of electrical pulse overstressing in integrated circuits, especially simple gates and bipolar LSI arrays. In order to determine the effect of ionizing radiation on the pulse-power failure susceptibility levels of small scale, monolithic, junction-isolated integrated circuits (simple gates), an experimental study was undertaken such that device failures could be induced in a simulated EMP or IEMP environment. The device types investigated included low- and high-power, quadruple, dual-input, positive NAND TTL gates. Permanent damage levels for these devices were determined for both positive and negative-polarity sub-microsecond pulses, introduced into the input, output and bias terminals of active devices, some of which were simultaneously irradiated by gamma radiation. The radiation dose rates ranged from 1 × 1010 to 5 × 1010 rads(Si)/sec. The failure susceptibility level of a device was found to depend uniquely upon the ionizing radiation, the device terminal subjected to the electrical stress pulse, and the polarity of the pulse. The data for device failures in the simulated EMP environment agree with the existing thermal-failure models characterized by P = Atm, where P is the power required to induce failure and t is the time to failure. In a radiation environment it was observed that initial ionization tends to reduce the magnitude of the constant A and shifts the time to failure t from the constant-energy regime (m = -1) to another.     

Investigation of Radiation Effects and Hardening Procedures for CMOS/SOS

Ionizing radiation effects and hardening procedures have been investigated using simple CMOS/SOS circuits fabricated with SiO2 gate insulators. A modified gate oxidation process using steam and HCl has resulted in improved gate oxide hardness -- with threshold voltage shifts of less than two volts up to a total dose of 106 rads(Si). Radiation-induced n-channel leakage currents were reduced by more than two orders of magnitude by using a deep boron ion implant and appropriate process ing techniques. Post-irradiation values of less than 0.5?A/mil have been obtained using this procedure. Studies of charge buildup at the silicon-sapphire interface indicate an effective positive charge in the range of 1011 cm-2 to 1012 cm-2 - peaking at a total dose of about 105 rads (Si). This effective charge decreases for increasing doses above 5×105 rads(Si). The decrease is attributed to radiation-induced interface states.     

Upset Events in Josephson Digital Devices under Alpha Particle Irradiation

Preliminary results on the effects of 5 MeV alpha particle irradiation on the electrical characteristics of large area (approximately 60 ?m2) Josephson Nb-amorphous Si-Nb tunnel devices indicate that these particles are effective in producing upset events when the device is operated in a switching mode. For bias currents very close to the critical current, IC, upset rates are near 0.1 per alpha. At a reduced bias current of 0.65 IC the upset rate is decreased but is still finite (0.002 per alpha). In addition, an hysteretic effect was observed for the critical current of the device under alpha irradiation. A simple heating model does not appear adequate to explain the observed upset rate as a function of bias current and the hysteretic effect.     

重离子和脉冲激光模拟单粒子翻转阈值等效性研究

根据重离子和脉冲激发诱发单粒子翻转机理,分析了重离子和脉冲激光模拟单粒子翻转阈值（激光能量与重离子线性能量转移（LET））等效方法，得出脉冲激光与重离子单粒子翻转阈值等效计算公式。应用实验室的激光模拟单粒子效应试验系统，开展了几种器件和集成电路的单粒子翻转实验研究。利用获得的计算公式计算激光等效LET阈值，并与国内外重离子实测数据进行比较。结果表明，脉冲激光能量等效LET阈值与重离子试验LET阈值较为一致。     

Single Event Upsets in NMOS Microprocessors

Three advanced 16-bit NMOS microprocessors have been observed to suffer single event upset at a rate varying between one upset for every 8 × 1010 to one for every 2 × 1012 n/cm2-upset for cyclotron-produced neutrons with an average energy of 14 MeV. These rates are expected to vary, probably upward, with different types of programs. The errors are inferred to occur in memory-like components of the microprocessors. Many of the errors caused the microcomputer to cease normal operations. This is the first direct experimental verification of logic upsets in microprocessors from neutrons.