适于硬件实现的快速HUFFMAN解码算法

HUFFMAN算法是一种被广泛应用的压缩算法,由于它是一种变长熵编码,因此解码效率不高,不便于硬件实现.本文提出一种新的HUFFMAN解码算法,针对JPEG标准采用一种新的查找表分组结构,在进一步节省内存空间的基础上,解码速度也有较大提高.同时,本文还给出了基于新算法、针对FPGA器件的硬件结构设计,用VHDL语言进行了描述,整个解码系统在QUARTUSII软件上编译仿真.结果表明,解码器的核心模块设计在速度和资源两方面均达到了较优的状态,可满足实时HUFFMAN解码要求.     

高效存储的Huffman硬件解码器的设计和应用

本文研究了Huffman解码器在集成电路上的实现问题,在研究解码码表的特点以及简化解码算法的基础上设计出高速Huffman解码电路。这种Huffman解码技术在数字通信领域将会有很大的使用价值。     

彩电色解码电路疑难故障两例

彩电色解码电路疑难故障两例王强例１幸福牌ＨＣ２２７Ｄ型彩电故障现象图像无彩色，调节色饱和度旋钮不起作用，但黑白图像和伴音都正常。分析检修从故障现象看，故障发生在色解码电路。该机采用ＴＡ７６９８ＡＰ担任彩色解码，测量消色识别脚脚电压为６．３Ｖ（正常为８...     

隔行色度信号及其应用研究

本文对隔行色度信号在ＰＡＬＤ制解码电路中的应用作了详细分析，表明隔行色度信号在同等条件下，具有相位分辨力高于其它测试信号的特点，可以在解码电路物输出端，直接调整延时分离电路，有益于解码电路的测量和调整。     

基于JPEG图像解码的高速Huffman解码电路

研究JPEG图像的Huffman解码器在集成电路上的实现问题,以范式Huffman编码为研究对象,在研究范式Huffman编码特点及快速算法的基础上设计出高速Huffman解码电路。此解码电路已经在Altera的FPGA上通过测试,系统能稳定运行在140 MHz,输出数据平均达到约1.2 Gb/s的带宽。     

ST高清电视解码器适用最新视频压缩技术

意法半导体发布了世界上第一个支持H．264／AVC和VCI高清标准的单芯片机顶盒(STB)解决方案。新产品的集成水平非常高，在一个单片上集成了STB的所有功能和多标准解码电路，STB7100可以同时解码多个HD视频流，并把合成的视频流输出到两个电视机，或以画中画的形式显示任屏幕上。高性能的300MHz ST40是新器件的CPU核心。     

高速8位流水线电流导引数模转换器的实现

本文介绍了笔者使用cadence设计的0．35um CMOS高速8位流水线电流导引数模转换器。电路采用了高速解码电路、双路并行处理、流水线等技术，使系统处理速度从传统的500M采样／秒达到1.5G采样／秒，输出差分电压在2个50欧姆的电阻上达到3．1V，电压精度达到1．55＊2^-1V。在国外同类设计中处于领先水平。     

通用遥控解码电路

通用遥控解码电路蔡轶本文介绍一种用硬件实现对一般彩电遥控信息解码的电路。此电路是作者在工作实践中设计开发的实用电路，适用于各种智能型遥控电子产品。一、解码电路的设计思想一般的彩电遥控系统是由红外遥控信号发送器、红外遥控信号接收器和微控制器及其外围电路...     

双制式单片解码ICTA8690在彩电中的应用

介绍双制式解码ＩＣ首次在出口南美彩电机芯上的应用情况，并阐述了该机芯的电路组成，原理功能和制式转换接口电路的设计。     

收录机故障检修技巧（10）

由分立元件立体声解码电路可看出：开关式立体声解码电路主要由两部分构成，即副载波再生器和开关解调器。且必须要保证解调器的开关和发射端调制器的开关同步．否则将全导致分离度的降低。因此，如何在接收端产生出与发射端同频同相的高质量38kHz开关信号，就成为提高解调质量的关键。     

量子稳定子码的概率译码

为了提高量子稳定子码的译码速率,提出了一种基于校验矩阵的量子概率译码算法。通过选择具有最小量子权重的算子作为差错算子来减少译码出错概率,通过预先构造量子标准阵列来缩短译码时间。与已有的量子最大似然译码算法相比,该算法对简并码和非简并码采用统一的译码方式,从而提高了简并码的译码可靠性。此外,算法不需要预先寻找差错算子对应的向量空间的基,因此算法复杂度更小。     

On algebraic soft-decision decoding algorithms for BCH codes

Three algebraic soft-decision decoding algorithms are presented for binary Bose-Chaudhuri-Hocquengham (BCH) codes. Two of these algorithms are based on the bounded distance (BD)+1 generalized minimum-distance (GMD) decoding presented by Berlekamp (1984), and the other is based on Chase (1972) decoding. A simple algebraic algorithm is first introduced, and it forms a common basis for the decoding algorithms presented. Next, efficient BD+1 GMD and BD+2 GMD decoding algorithms are presented. It is shown that, for binary BCH codes with odd designed-minimum-distance d and length n, both the BD+1 GMD and the BD+2 GMD decoding algorithms can be performed with complexity O(nd). The error performance of these decoding algorithms is shown to be significantly superior to that of conventional GMD decoding by computer simulation. Finally, an efficient algorithm is presented for Chase decoding of binary BCH codes. Like a one-pass GMD decoding algorithm, this algorithm produces all necessary error-locator polynomials for Chase decoding in one run     

Linear programming decoding: The ultimate decoding technique for low density parity check codes

Linear programming (LP) decoding is an alternative to iterative algorithms for decoding low density parity check (LDPC) codes. Although the practical performance of LP decoding is comparable to message-passing decoding, a significant advantage is its relative amenability to nonasymptotic analysis. Moreover, there turn out to be a number of important theoretical connections between the LP decoding and standard forms of iterative decoding. These connections allow theoretical insight from the LP decoding perspective to be transferred to iterative decoding algorithms. These advantages encouraged many researchers to work in this recent decoding technique for LDPC codes. In this paper, LP decoding for LDPC code is extensively reviewed and is discussed in different segmented areas.     

A novel BTC decoding algorithm based on the genetic algorithm in optical communication systems

Combining the advantages of both the genetic algorithm （GA） and the chase decoding algorithm, a novel improved decoding algorithm of the block turbo code （BTC） with lower computation complexity and more rapid decoding speed is proposed in order to meet the developing demands of optical communication systems. Compared with the traditional chase decoding algorithm, the computation complexity can be reduced and the decoding speed can be accelerated by applying the novel algorithm. The simulation results show that the net coding gain （NCG） of the novel BTC decoding algorithm is 1.1 dB more than that of the traditional chase decoding algorithm at the bit error rate （BER） of 10^-6. Therefore, the novel decoding algorithm has better decoding correction-error performance and is suitable for the BTC in optical communication systems.     

一种带辅助译码比特的Polar码译码方法

在传统的Polar码译码的基础上,引入辅助译码比特,构造了一个辅助的Polar码字以提高译码性能。辅助比特由信道选择辅助窗口内的信息位决定。接收端如译码失败,将进行二次译码尝试。译码方案分两阶段进行：基于相同结构的扩展生成矩阵,将辅助译码比特译出;结合译出的辅助比特,对原码字进行译码,提高译码成功率。仿真结果显示,使用所提方法进行译码,其译码性能明显优于普通串行抵消译码方法;与两种传统的自动重传请求方案相比,能分别获得1 dB和1.9 dB的性能增益。     

Gear-Shift Decoding

This paper considers a class of iterative message-passing decoders for low-density parity-check codes in which the decoder can choose its decoding rule from a set of decoding algorithms at each iteration. Each available decoding algorithm may have different per-iteration computation time and performance. With an appropriate choice of algorithm at each iteration, overall decoding latency can be reduced significantly, compared with standard decoding methods. Such a decoder is called a gear-shift decoder because it changes its decoding rule (shifts gears) in order to guarantee both convergence and maximum decoding speed (minimum decoding latency). Using extrinsic information transfer charts, the problem of finding the optimum (minimum decoding latency) gear-shift decoder is formulated as a computationally tractable dynamic program. The optimum gear-shift decoder is proved to have a decoding threshold equal to or better than the best decoding threshold among those of the available algorithms. In addition to speeding up software decoder implementations, gear-shift decoding can be applied to optimize a pipelined hardware decoder, minimizing hardware cost for a given decoder throughput.     

Hybrid Iterative Decoding for Low-Density Parity-Check Codes Based on Finite Geometries

In this letter, a two-stage hybrid iterative decoding algorithm which combines two iterative decoding algorithms is proposed to reduce the computational complexity of finite geometry low-density parity-check (FG-LDPC) codes. We introduce a fast weighted bit-flipping (WBF) decoding algorithm for the first stage decoding. If the first stage decoding fails, the decoding is continued by the powerful belief propagation (BP) algorithm. The proposed hybrid decoding algorithm greatly reduces the computational complexity while maintains the same performance compared to that of using the BP algorithm only.     

极化码的分布式CRC辅助低复杂度逐次抵消翻转译码

为提高极化码的译码效率,文中提出了一种新颖的逐次抵消翻转(SCF)译码。与传统的SCF译码相比,其可以使用分布式CRC比特来降低计算复杂度。该译码通过提前终止对第一次SC译码的失败帧的译码,来减少信息比特的估计数量,同时尝试最小化附加的排序操作。仿真结果表明,与传统的SCF译码相比,该SCF译码将重复SC译码的计算复杂度至少降低了27%。     

Replica horizontal-shuffled iterative decoding of low-density parity-check codes

For practical considerations, it is essential to accelerate the convergence speed of the decoding algorithm used in an iterative decoding system. In this paper, replica versions of horizontal-shuffled decoding algorithms for low-density parity-check (LDPC) codes are proposed to improve the convergence speed of the original versions. The extrinsic information transfer (EXIT) chart technique is extended to the proposed algorithms to predict their convergence behavior. Both EXIT chart analysis and numerical results show that replica plain horizontal-shuffled (RPHS) decoding converges much faster than both plain horizontal-shuffled (PHS) decoding and the standard belief-propagation (BP) decoding. Furthermore, it is also revealed that replica group horizontal-shuffled (RGHS) decoding can increase the parallelism of RPHS decoding as well as preserve its high convergence speed if an equivalence condition is satisfied, and is thus suitable for hardware implementation.     

An improved AS-SCLF decoding algorithm of polar codes based on the assigned set

An improved successive cancellation list bit-flip based on assigned set (AS-SCLF) decoding algorithm is proposed to solve the problems that the successive decoding of the successive cancellation (SC) decoder has error propagation and the path extension of the successive cancellation list (SCL) decoder has the decision errors in the traditional cyclic redundancy check aided successive cancellation list (CA-SCL) decoding algorithm. The proposed algorithm constructs the AS firstly. The construction criterion is to use the Gaussian approximation principle to estimate the reliabilities of the polar subchannel and the error probabilities of the bits under SC decoding, and the normalized beliefs of the bits in actual decoding are obtained through the path metric under CA-SCL decoding, thus the error bits containing the SC state are identified and sorted in ascending order of the reliability. Then the SCLF decoding is performed. When the CA-SCL decoding fails for the first time, the decision results on the path of the SC state in the AS are exchanged. The simulation results show that compared with the CA-SCL decoding algorithm, the SCLF decoding algorithm based on the critical set and the decision post-processing decoding algorithm, the improved AS-SCLF decoding algorithm can improve the gain of about 0.29 dB, 0.22 dB and 0.1 dB respectively at the block error rate (BLER) of 10-4 and reduce the number of decoding at the low signal-to-noise ratio (SNR), thus the computational complexity is also reduced.