A fully integrated, untrimmed CMOS instrumentation amplifier withsubmicrovolt offset

A low-noise CMOS instrumentation amplifier intended for low-frequency thermoelectric microsensor applications is presented that achieves submicrovolt offset and noise. Key to its performance is the chopper modulation technique combined with a bandpass filter and a matching on-chip oscillator. No external components or trimming are required. The achievable offset performance depends on the bandpass filter Q and the oscillator-to-bandpass filter matching accuracy. Constraints are derived for an optimum Q and a given matching accuracy. The improvement of common-mode rejection ratio (CMRR) in chopper amplifiers is discussed. The amplifier features a total gain of 77±0.3 dB and a bandwidth of approximately 600 Hz. The measured low-frequency input noise is 8.5 nV/√Hz and the input offset is 600 nV. The measured low-frequency CMRR is better than 150 dB. The circuit has been implemented in a standard 1-μm single-poly CMOS process     

Fully integrated CMOS power amplifier design using the distributedactive-transformer architecture

A novel on-chip impedance matching and power-combining method, the distributed active transformer is presented. It combines several low-voltage push-pull amplifiers efficiently with their outputs in series to produce a larger output power while maintaining a 50-Ω match. It also uses virtual ac grounds and magnetic couplings extensively to eliminate the need for any off-chip component, such as tuned bonding wires or external inductors. Furthermore, it desensitizes the operation of the amplifier to the inductance of bonding wires making the design more reproducible. To demonstrate the feasibility of this concept, a 2.4-GHz 2-W 2-V truly fully integrated power amplifier with 50-Ω input and output matching has been fabricated using 0.35-μm CMOS transistors. It achieves a power added efficiency (PAE) of 41 % at this power level. It can also produce 450 mW using a 1-V supply. Harmonic suppression is 64 dBc or better. This new topology makes possible a truly fully integrated watt-level gigahertz range low-voltage CMOS power amplifier for the first time     

低功耗CMOS限幅放大器设计

利用0.18μm CMOS工艺设计了应用于光接收机中的10Gb/s限幅放大器.此限幅放大器由输入缓冲,4级放大单元,一级用于驱动50Ω传输线的输出缓冲和失调电压补偿回路构成.输入动态范围为38dB(10mV～800mV),负载上的输出限幅在400mV,在3.3V电源电压下,功耗仅为99mW.整个芯片面积为0.8×1.3mm2.     

A CMOS nested-chopper instrumentation amplifier with 100-nV offset

A CMOS nested-chopper instrumentation amplifier is presented with a typical offset of 100 nV. This performance is obtained by nesting an additional low-frequency chopper pair around a conventional chopper amplifier. The inner chopper pair removes the 1/f noise, while the outer chopper pair reduces the residual offset. The test chip is free from 1/f noise and has a thermal noise of 27 nV/√Hz consuming a total supply current of 200 μA     

1.8 V–3 GHz CMOS limiting amplifier with efficient frequency compensation

A compact robust CMOS limiting amplifier (LA) for high data traffic optical links is presented in this work. The core considers two different blocks. First, four common-source inverter amplifiers are included, which optimize the gain-bandwidth product of the structure. And second, two additional compensation stages are placed strategically between the gain stages alleviating the pernicious load effect. These stages develop two different compensation techniques simultaneously thus increasing the bandwidth. The proposed design consumes 113 mW with a single 1.8 V supply. It achieves a cut-off frequency up to 3 GHz and provides a gain of 21 dB. The circuit is packaged in a QFN24 and mounted on a commercial FR4 PCB.     

An integrated NMOS operational amplifier with internal compensation

An internally compensated differential operational amplifier is described which has been fabricated using n-channel Al-gate MOS technology. Only enhancement mode devices are used, and the circuit has been designed so that its performance is insensitive to process parameters.     

Fully integrated 10 GHz CMOS VCO

A differential voltage-controlled oscillator has been designed to operate in the 10 GHz band using a 0.25 μm CMOS process and low Q integrated inductors. The low gain and low Q problems of the components are overcome by the deployment of the cascode configuration with negative conductance generation to enhance the loop gain and Q value. PMOS varactors are used for varying the oscillating frequency from 9.7 to 11.4 GHz. The phase noise at 400 kHz offset is from -101 dB/Hz at the low frequency end to -87 dB/Hz at the high frequency end     

Fully integrated CMOS UWB pulse generator

The design of a fully integrated CMOS ultra-wideband (UWB) pulse generator for the 3.1-10.6 GHz frequency band is presented. The pulse generation is based on the filter impulse response technique. With such a technique, the pulse matches the FCC mask with no need for an expensive external filter. The layout of this circuit in a 0.13 mum CMOS technology shows a surface area of less than 0.57 mm² and a power consumption of around 20 mW     

带温度补偿的Ka波段CMOS堆叠功率放大器设计

介绍了一款基于55 nm CMOS工艺,带温度补偿电路的Ka波段堆叠高效功率放大器（power amplifier,PA）.采用了一种新型的针对晶体管堆叠结构的温度补偿电路,该补偿电路由两个二极管和四个电阻组成,结构简单,易于实现.通过调整堆叠放大器各个栅极偏置电路中的电压,使得PA随温度变化的增益和输出功率得到有效补偿,增强了电路的可靠性和热稳定性.基于Agilent ADS软件的版图仿真结果显示:电路的最大输出功率为20.1 dBm,频带内功率附加效率（power additional efficiency,PAE）为20%~30%,大信号功率-1 dB带宽为15 GHz（46%）.在-40℃到125℃的温度范围内,采用新型温补偏置电路与传统偏置电路相比,小信号增益的温度波动从2.2 dB改善到0.1 dB,显著提高了功放的热稳定性,证明了所提出的温度补偿电路对于在宽温度范围内校正功率放大器增益变化的有效性.     

CMOS limiting amplifier for SDH STM-16 optical receiver

A 2.5 Gbit/s limiting amplifier is realised in a 0.35 μm CMOS technology. At a supply voltage of 5 V, the power dissipation is 225 mW. The input dynamic range is about 40 dB at a constant output voltage swing (400 mVp-p). The chip area is 1×1.1 mm²     

A CMOS low noise amplifier with integrated front-side micromachined inductor

The paper presents the design and characterization of a low noise amplifier (LNA) in a 0.18 μm CMOS process with a novel micromachined integrated stacked inductor. The inductor is released from the silicon substrate by a low-cost CMOS compatible dry front-side micromachining process that enables higher inductor quality factor and self-resonance frequency. The post-processed micromachined inductor is used in the matching network of a single stage cascode 4 GHz LNA to improve its RF performance. This study compares performance of the fabricated LNA prior to and after post-processing of the inductor. The measurement results show a 0.5 dB improvement in the minimum noise figure and a 1 dB increase in gain, while good input matching is maintained. These results show that the novel low-cost CMOS compatible front-side dry micromachining process reported here significantly improves performance and is very promising for System-On-Chip (SOC) applications.     

A 2-V 10.7-MHz CMOS limiting amplifier/RSSI

This paper presents low-voltage low-power CMOS circuit design techniques for an intermediate frequency (IF) limiting amplifier and received signal strength indicator (RSSI). The architecture of the limiting amplifier and RSSI employed is determined by the optimal power consumption for a specified speed, overall gain, and accuracy. Each gain cell of the limiting amplifier employs folded diode load for low-voltage operation. Offset is reduced by a cross-connected source-coupled pair offset subtractor that is along the signal path. Full-wave current rectification and summation are employed in the RSSI circuit to achieve high precision while maintaining low voltage and low power. Using a single 2-V supply voltage, measured results demonstrate the input dynamic range is larger than 75 dB for 10.7-MHz IF application. The prototype occupies an active area of 0.4 mm² using a 0.6-μm digital CMOS technology. The power dissipation is 6.2 mW     

A 3.125 Gb/s limit amplifier in CMOS with 42 dB gain and 1 /spl mu/s offset compensation

A fast offset compensation method for high-gain amplifiers is presented that leverages a novel peak detector design and a dynamic, multi-tap feedback system to achieve roughly three orders of magnitude improvement in settling time over traditional compensation methods. Design tradeoffs between gain, bandwidth, power dissipation, and noise performance of the limit amplifier are discussed. Measured results of a custom 3.125 Gb/s limit amplifier in 0.18 /spl mu/m CMOS employing the proposed compensation technique demonstrate a sub-1-ms settling time while still achieving less than 4 ps rms output jitter with a 2.5 mV peak-to-peak input at 2.5 Gb/s.     

Fully integrated 5.35-GHz CMOS VCOs and prescalers

Two 5.35-GHz monolithic voltage-controlled oscillators (VCOs) and two prescalers have been fabricated in a digital 0.25-μm CMOS process. One VCO uses p⁺/n-well diodes, while the other uses MOS varactors, Q of 57 at 5.5 GHz and 0 V bias (low-Q condition) for a p ⁺/n-well varactor has been achieved. For an MOS varactor, it is possible to achieve a quality factor of 140 at 5.5 GHz. The tuning ranges of the VCOs are >310 MHz, and their phase noise is <-116.5 dBc/Hz at a 1-MHz offset while consuming ~7 mW power at V_DD=1.5 V. The low phase noise is achieved by using only PMOS transistors in the VCO core and by optimizing the resonator layout. The prescalers utilize a variation of the source-coupled logic. The power consumption is 4.1 mW at 1.5-V V_DD and 5.4 GHz. By widening the transistors in the first three divide-by-two stages, the maximum operating frequency is increased to 9.96 GHz at V_DD=2.5 V     

Fully integrated CMOS nano-particle assembly circuit for biological detections

Recently, along with the booming of research and production of CMOS Integrated Bio-sensing System, selective assembly of organic nano-particles on the on-chip electrodes, which serves for specific bio-sensing and detection purposes, is in high demand in areas like biological analysis and detection, DNA probing and surveying systems and etc. In this paper, a fully integrated bio-circuit targeting at electrical selective assembly of charged nano-particles is proposed and designed in SMIC 0.18 μm CMOS mixed signal process. The proposed circuit integrates the 16 pixels of 19 μm × 19 μm electrode array, counter electrode, potentiostat circuit, digital decoding circuit, as well as control logics on a single chip, and provides a rail-to-rail range of assembling voltage, a potential resolution of 8 bit, and a maximal assembling current up to 459 μA, biased at a current of 1 μA. Meanwhile, a novel electrode-reuse scheme is also proposed to further simplify the architecture and save chip area as well, without degrading the functionalities. Experimental results from on-chip selective assembly of 50 nm polystyrene nano-particles are included and discussed to verify the feasibility of the proposed circuits.     

Fully CMOS integrated low voltage 100 MHz MEMS resonator

The development of a novel fully integrated microelectromechanical system (MEMS) for RF purposes is presented. It is composed of a paddle polysilicon micro-resonator electrostatically excited and a capacitive CMOS read-out amplifier. The micro-resonator is fabricated directly on a commercial CMOS technology, only requiring a wet etching process for the release of the resonant structure after the full CMOS integration. Electrical characterisation of the on-chip resonant device has been performed showing a resonance frequency near 100 MHz.     

Fully integrated 0.25 μm CMOS VCSEL driver with current peaking

A vertical-cavity-surface-emitting laser (VCSEL) driver chip based on a novel circuit concept for current peaking has been designed and fabricated in a 0.25 μm complementary metal-oxide-semiconductor (CMOS) process. This concept allows the easy integration of a peaking driving scheme in CMOS. Experimental results show speed extension from 500 Mbit/s for current on-off to 3.9 Gbit/s for current peaking driving     

基于斩波技术的CMOS运算放大器失调电压的消除设计

实现传感器系统的高分辨率,要求其内部运算放大器具有低失调电压和低噪声的性能,为此介绍了一种可减少运算放大器的失调电压和低频噪声的斩波技术,并基于该技术进行温度传感器中CMOS运算放大电路失调电压的消除设计,最后通过SPICE仿真分析来权衡电路各参数的设定。     

A fully integrated 0.5-5.5 GHz CMOS distributed amplifier

A fully integrated 0.5-5.5-GHz CMOS-distributed amplifier is presented. The amplifier is a four stage design fabricated in a standard 0.6-μm three-layer metal digital-CMOS process. The amplifier has a unity-gain cutoff frequency of 5.5 GHz, and a gain of 6.5 dB, with a gain flatness of ±1.2 dB over the 0.5-4 GHz band. Input and output are matched to 50 Ω, with worst-case return losses on the input and output of -7 and -10 dB, respectively. Power dissipation is 83.4 mW from a 3.0 V supply, input-referred 1-dB compression point varies from +6 dBm at 1 GHz to 8.8 dBm at 5 GHz. From a circuit standpoint, the fully integrated nature of the amplifier on the given substrate results in a heavily parasitic-laden design. Discussion emphasis is therefore placed on the practical design, modeling, and CAD optimization techniques used in the design process     

A CMOS low-distortion fully differential power amplifier withdouble nested Miller compensation

A four-stage fully differential power amplifier using a double-nested Miller compensated structure is presented. The multiple-loop configuration used results in a lower harmonic distortion, at least in the audio band, compared to conventional three-stage amplifiers with nested Miller compensation. Design criteria and stability conditions for good stability of amplifiers using a multiple- (greater than two) loop topology are presented. The amplifier operates with a single power supply which has a minimum value of 3 V. With a 5-V supply, power dissipation is 10 mW and total harmonic distortion (THD) is -83 dB for a -V_p-p differential output signal at 10 kHz and a load of 50 Ω. With an 8 Ω load and for a 10-kHz, 4-V _p-p output signal, THD is -68 dB. The chip area is 0.625 mm ² in a 1.5-μm single-poly, double-metal, n-well CMOS technology