一种基于跨导电流比-反型系数-过驱动电压的设计方法

提出了一种基于MOSFET反型系数(Inversion Coefficient)且适合于MOSFET工作在任何反型区的模拟集成电路的设计方法.对于一定工艺的深亚微米模拟集成电路,结合查表法进行的手工估算值与仿真值的误差可控制在±10%左右.该方法尤其适用于低压、低功耗设计.     

超深亚微米工艺下模拟IC仿真的MOSFET模型

对MOSFET器件特性、MOSFET建模方法和建模发展历程进行了回顾,分析了在模拟集成电路低功耗设计中比较流行的模型(BSIM3和EKV模型),对它们进行了比较,分析其各自的优点和缺点。结果表明获得能够精确地预测高性能模拟系统的模型是很困难的,而EKV模型在模拟集成电路的低功耗设计中具有一定的优势。     

模拟集成电路仿真中的UDSM MOSFET建模

对MOSFET器件特性、MOSFET建模方法和建模发展历程进行了回顾,重点分析了在模拟集成电路设计中较为流行的几种模型:BSIM3、EKV和SP2001模型,对其各自的优缺点进行了比较。结果表明,获得能够精确地预测高性能模拟系统的模型是很困难的;几种模型中,EKV模型在模拟集成电路的低功耗设计中具有一定的优势。     

30 V沟槽MOSFET优化设计

借助半导体专业模拟软件Tsuprem-4 和Medici,模拟得到一组最佳的30 V 沟槽MOSFET结构和工艺参数;给出了特性模拟曲线.在此基础上,详细讨论了沟槽的宽度和深度变化对沟槽 MOSFET的阈值电压、击穿电压、漏电流及导通电阻等特性的影响.最后,根据模拟得到的最佳参数进行了流片实验.结果表明,所设计器件的击穿电压大于35 V,Vgs为10 V下的导通电阻为21 mΩ* mm2.     

杂质非完全离化对SiC n-MOSFET电特性的影响

文章研究了SiC中杂质非完全离化对器件性能的影响.通过考虑场致离化效应,分析了空间电荷区电荷密度与表面势的关系,得出在SiC MOSFET反型条件下,可近似认为杂质完全离化.在此基础上,模拟了4H-SiC MOSFET的漏电流-栅压曲线和迁移率-栅压曲线.模拟结果与实验数据非常吻合.     

非掺杂对称双栅的基于完整表面电势的核心模型

通过求解Poisson方程自洽地得到了表面电势随沟道电压的变化关系,从而推出了非掺杂对称双栅MOSFET的一个基于表面势的模型.通过Pao-Sah积分得到了漏电流的表达式.该模型由一组表面势方程组成,解析形式的漏电流可以通过源端和漏端的电势得到.结果标明该模型在双栅MOSFET的所有工作区域都成立,而且不需要任何简化(如应用薄层电荷近似)和辅助拟合函数.对不同工作条件和不同尺寸器件的二维数值模拟与模型的比较进一步验证了提出模型的精度.     

非掺杂对称双栅的基于完整表面电势的核心模型

通过求解Poisson方程自洽地得到了表面电势随沟道电压的变化关系,从而推出了非掺杂对称双栅MOSFET的一个基于表面势的模型. 通过Pao-Sah积分得到了漏电流的表达式. 该模型由一组表面势方程组成,解析形式的漏电流可以通过源端和漏端的电势得到. 结果标明该模型在双栅MOSFET的所有工作区域都成立,而且不需要任何简化(如应用薄层电荷近似)和辅助拟合函数. 对不同工作条件和不同尺寸器件的二维数值模拟与模型的比较进一步验证了提出模型的精度.     

高k栅介质MOSFET电特性的模拟分析

对高k栅介质MOSFET栅极漏电进行研究 ,确定栅介质的厚度 ,然后使用PISCES Ⅱ模拟器对高k栅介质MOSFET的阈值电压、亚阈斜率和Idsat/Ioff进行了详细的分析研究。通过对不同k值的MOSFET栅极漏电、阈值电压、亚阈斜率和Idsat/Ioff的综合考虑 ,得出选用k <5 0且Tk/L≤ 0 .2的栅介质能获得优良的小尺寸MOSFET电性能。     

德州仪器收购电源管理初创公司Ciclon

德州仪器为了扩大其模拟电源管理生产线，近日以未披露的价格收购了Ciclon半导体器件公司。有了Ciclon的加入，德州仪器将迅速打入功率MOSFET和其他模拟集成电路业务。Ciclon主要从事功率MOSFET和基于射频的LDMOS功率晶体管业务。根据该交易条款，Ciclon将整体并入德州仪器。Granahan将成为电源功率级业务部门的总经理此项交易也是德州仪器最近一次在模拟领域的收购活动。     

主动“ORing”方案降低了功率损耗和设备尺寸

主动"ORing"方案包括一个功率MOSFET和一个集成电路控制器.MOSFET的导通电阻RDS(on)会在其内部产生功率损耗(通过器件的电流的平方与电阻的乘积).     

MOSFET失配的研究现状与进展

特定工艺条件下的器件失配程度限制了射频／模拟集成电路的设计精度和成品率。电路设计者需要精确的MOSFET失配模型来约束电路优化设计,版图设计者需要相应的设计规则来减小芯片失配。本文介绍了MOSFET失配的基本概念;回顾了MOSFET模型的研究进展及相关的版图设计技术、计算机仿真方法;总结了MOSFET失酉己对电路性能的影响及消除技术。最后探讨了MOSFET失配的研究趋势。     

Understanding MOSFET mismatch for analog design

Despite the significance of matched devices in analog circuit design, mismatch modeling for design application has been lacking. This paper addresses misconceptions about MOSFET mismatch for analog design. V/sub t/ mismatch does not follow a simplistic 1/(/spl radic/area) law, especially for wide/short and narrow/long devices, which are common geometries in analog circuits. Further, V/sub t/ and gain factor are not appropriate parameters for modeling mismatch. A physically based mismatch model can be used to obtain dramatic improvements in prediction of mismatch. This model is applied to MOSFET current mirrors to show some nonobvious effects over bias, geometry, and multiple-unit devices.     

低失配CMOS差分放大器的后端版图设计研究

器件尺寸的缩小提高了晶体管的原始速度,但是集成电路不同模块间有害的相互干扰和版图的非理想性都限制了系统的工作速度和精度。理想的差分放大器电路参数是完全对称的,但实际电路中,由于制造工艺每道工序的不确定性,标称相同的器件都存在有限的不匹配。本文在设计差分电路的版图时通过讨论制造工艺和版图结构对电路性能的影响,设计了失配较小,寄生效应小的单管版图结构,并在全局布局时充分考虑了对称性对电路性能的影响得到了比较理想的差分放大器版图。     

Effect of hot-electron stress on low frequency MOSFET noise

Hot-electron reliability problems are of great importance in small geometry n-channel field-effect transistors. Accumulation of negative charge within the gate insulator and creation of interface states represent the two dominant degradation mechanisms. Since MOSFET noise is ascribed to Si-SiO2interface states, one might reasonably expect this noise to increase after hot-electron stress. We verify this expectation and show how the noise increase depends on gate voltage during stress. MOSFET noise is important for analog circuit performance and, hence, consideration of the long-term stability of noise, as well as threshold voltage and transconductance, should be included in analog circuit/process design.     

A floating-gate analog memory device for neural networks

A floating-gate MOSFET device that can be used as a precision analog memory for neural network LSIs is described. This device has two floating gates. One is a charge-injection gate with a Fowler-Nordheim tunnel junction, and the other is a charge-storage gate that operates as a MOSFET floating gate. The gates are connected by high resistance, and the charge-injection gate is small so that its capacitance is much less than that of the charge-storage gate. By applying control pulses to the charge-injection gate, it is possible to charge and discharge the MOSFET floating gate in order to modify the MOSFET current with high resolution over 10 b. The charge injection can be carried out without disturbing the MOSFET output current with high voltage control pulses. This device is useful for on-chip learning in analog neural network LSIs     

Reliability issues in submicron MOSFETs with oxynitride gate dielectrics

A review of critical reliability issues in submicron MOSFETs with oxynitride gate dielectrics is presented. We have focussed our attention on: substrate and gate currents in short channel MOSFETs, hot carrier induced MOSFET degradation under DC and AC stress, gate-induced drain leakage current and its enhancement due to stress, neutral trap generation due to electrical stress and degradation of analog MOSFET parameters. We have also discussed the problems of radiation induced neutral trap generation and boron penetration through the gate dielectric, which arise due to the advanced processing techniques utilized in submicron MOSFET processing. It is concluded that the use of oxynitride gate dielectrics can effectively solve several reliability issues encountered in scaling down MOSFETs to submicron dimensions.     

Current mismatch due to local dopant fluctuations in MOSFET channel

A microscopic multitransistor model is developed to analyze the impact of local dopant fluctuation on the intrinsic mismatch of long-channel MOSFET. A closed analytical formula for current mismatch is derived to show a nonscaled and self-consistent form /spl sim/[4+Log(L/L/sub min/)]/WL. This is in contrast to the global fluctuation model, in which the current mismatch has a universal scaling form /spl sim/1/WL but is not self-consistent if a MOSFET is modeled as an equivalent two-transistor system. The weak violation of scaling law results from the local fluctuation that has more impact on longer channel devices than on shorter ones. Our new model is consistent with recent experimental observation and can explain the discrepancies between the experimental data and the existing models. The analysis indicates that the local dopant fluctuation is the major cause and accounts for about 60% to 80% of total current mismatch when operated at lower gate voltage, a usual regime for higher output impedance.     

Switched-current circuit design issues

Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI circuits require only a standard digital CMOS process. SI circuits use MOS transistors as the storage elements to provide analog memory capability. Similar to the operation of dynamic logic circuits, a voltage is sampled onto the gate of a MOSFET and held on its noncritical gate capacitance. The held voltage signal on the gate causes a corresponding held current signal in the drain, usually proportional to the square of the gate-to-source voltage. Design issues related to the implementation and performance of SI circuits are presented. SI filters show comparable performance to SC filters except in terms of passband accuracy. The major source of error is nonunity current gain in the SI integrator due to device mismatch and clock-feedthrough effects. For the initial CMOS prototypes, the current track and hold (T/H) gain error was about 2.5%     

The Localized-SOI MOSFET as a Candidate for Analog/RF Applications

In this paper, the characteristics of a localized-SOI (L-SOI) MOSFET are investigated for analog/RF applications. In the L-SOI device, the source/drain regions are quasi-surrounded by L-type oxide layers to reduce junction capacitance and avoid source/drain punchthrough, while the channel is directly connected with the substrate to alleviate the self-heating effect. Such structures can combine the advantages of both bulk and SOI MOSFETs and avoid their issues. Due to the unique structure of this novel device, the L-SOI MOSFET can exhibit excellent analog/RF behaviors. Higher g _m / I _ds ratio and intrinsic gain (g _m / g _ds)can be received compared with the conventional SOI structure, particularly at low gate bias. Higher and , which are due to higher g _m and reduced gate capacitance, can be observed in the L-SOI MOSFET. In addition, better noise performance can be achieved resulting from reduced lattice temperature and improved g _m . Thus, the L-SOI MOSFET can be considered as one of the potential candidates for analog/RF applications.