Pattern density and deposition profile effects on oxide chemical-mechanical polishing and chip-level modeling

Test masks for characterizing pattern-dependent variation of the remained thickness after chemical-mechanical polishing (CMP) were designed by taking the experimentally obtained interaction distance into consideration. Polishing behaviors were characterized by taking into consideration layout pattern density and pitch variations using these masks. Deposition profile effects were also compared between plasma-enhanced tetra ethyl ortho silicate (PETEOS) and high-density plasma (HDP) oxide. Both the measured post-CMP thickness and the expected oxide pattern density after the consideration of deposition profile effects showed a good correlation with respect to the pitch variation for a constant layout pattern density. Also, the relationship between remained thickness and true layout pattern density was deduced. Chip-level CMP modeling was investigated to obtain the post-CMP thickness distributions across a die from its design layout and a few oxide film and CMP parameters. The experimental CMP results agreed well with the modeling results. The effective dummy filling results were shown to achieve a smaller pattern density variation, which resulted in better post-CMP thickness uniformity. Whether the resulting oxide thickness could be predicted for any location on a die for an arbitrary layout, if the effective pattern density distributions are calculated, was discussed.     

Characterization and modeling of oxide chemical-mechanicalpolishing using planarization length and pattern density concepts

Chemical-mechanical polishing (CMP) has emerged as the dominant dielectric planarization method due to its ability to reduce topography over longer lateral distances than earlier techniques. However, CMP still suffers from pattern dependencies that result in large variation in polished oxide thickness across typical chips, which can impact circuit performance and yield. A comprehensive semiphysical pattern dependent model of the CMP process, integrated with a parameter extraction and process characterization methodology, has been developed to enable accurate and efficient prediction of post-CMP oxide thickness across patterned chips. In the characterization phase, test wafers are polished to obtain model parameters for the desired CMP process. Standard test layouts have been defined which consist of regions with different feature density and pitch; a new contribution is the inclusion of "step density" structures which provide large abrupt post-CMP thickness variations to improve parameter extraction. The key extracted parameter which characterizes the particular CMP process is the planarization length     

Characteristics of polysilicon oxides combining N2Onitridation and CMP processes

This paper present a high-quality polysilicon oxide combining N ₂O nitridation and chemical mechanical polishing (CMP) processes. Experimental results indicate that polyoxide grown on the CMP sample exhibits a lower leakage current, higher dielectric breakdown field, higher electron barrier height, less electron trapping rate, higher charge-to-breakdown (Q_bd), and lower density of trapping charge than those of non-CMP samples. In addition, the CMP process enhances nitrogen incorporation at the interface by the N₂ O nitridation, ultimately improving the polyoxide quality. However, the CMP process smooths the surface of polysilicon and this planar surface reduces the out-diffusion of the phosphorous during thermal oxidation     

Chemical mechanical polishing with fixed abrasives using different subpads to optimize wafer uniformity

Chemical mechanical polishing (CMP) processes are widely used in the semiconductor industry and are conventionally carried out using abrasive slurry and a polishing pad. In an alternative procedure, called ‘slurry free CMP’, the abrasive particles are embedded in the pad material (‘fixed abrasives’). A microreplicated resin layer of pyramids filled with the abrasives is placed on top of a rigid polycarbonate layer and a resilient foam sublayer. Instead of slurry, only DI-water or a basic solution is applied. Drying in of the slurry and glazing of the pad is not possible and pad conditioning is not required. Experiments were carried out for slurry free CMP to optimize the with-in-wafer non-uniformity (WIW-NU), removal rate and planarization of oxide ILD. Results of this optimization are compared with our best slurry process.

It is shown that the fixed abrasives process is superior to the slurry process with regard to planarization: the rate of planarization is almost three times faster for the slurry free process. This enables further process optimization, such as the use of a thinner pre-CMP oxide layer.

Besides higher planarization rates, better with-in-die non-uniformity (WID-NU) can be obtained by adjusting the subpad construction of these ‘slurry free’ pads. The flexibility of the pad construction makes it possible to optimize the WID-NU and WIW-NU. Stiffer pads give lower WID-NU, but for the stiffest pad the WIW-NU will slightly increase. However, compared to the slurry process both WID-NU and WIW-NU are better.     

Effects of pattern characteristics on copper CMP

Copper chemical mechanical polishing(CMP)is influenced by geometric characteristics such as line width and pattern density,as well as by the more obvious parameters such as slurry chemistry,pad type,polishing pressure and rotational speed.Variadons in the copper thickness across each die and across the wafer Can impact the circuit performance and reduce the yield.In this paper,we propose a modeling method to simulate the polishing behavior as a function of layout pattern factors.Under the same process conditions,the pattern density,the line width and the line spacing have a strong influence on copper dishing,dielectric erosion and topography.The test results showed:the wider the copper line or the spacing,the higher the copper dishing;the higher the density,the higher the dielectric erosion;the dishing and erosion increase slowly as a function of increasing density and go into saturation when the density is more than 0.7.     

A Novel Approach to Analyze and Model Feature Size Effects in CMP

In order to characterize and model the pitch dependency of the step-height decay in a typical oxide CMP process, we measured surface profiles for line-space patterns at 50% density but different pitches. The profiles are analyzed in the spatial frequency domain. For long polishing times, we find a linear dependency between the exponential decay rate and the spatial frequency. From this observation, we derive a simple mathematical model to calculate the post-CMP topography based on the layout density. Application to a typical DRAM metalization layer shows remarkably good qualitative agreement with an error in the predicted heights of ${pm 15}~{hbox{nm}}$ .      

Finite element analysis on von Mises stress distributions of Si DSP

In this paper, we describe a 2D axisymmetric quasi-static finite element model based on 300 mm wafer and double-side polishing (DSP) using a COMSOL Multiphysics software. Afterwards, the effects of Young's modulus and Poisson's ratio of polishing pad and the thickness ratio of upper and lower pads on the von Mises stress distribution are observed and chemical mechanical polishing (CMP) experiments are carried out to verify the above numerical calculations. The results show that a harder polishing pad results in a less edge roll-off, where a sharp variation in removal rate is observed near the edge of the wafer, but Poisson's ratio of pad has a less effect on the von Mises stress distribution on the wafer edge. A larger thickness ratio of upper and lower pads leads to a better wafer planarization.     

An analytical dishing and step height reduction model for chemical mechanical planarization (CMP)

An analytical model for dishing and step height reduction in chemical mechanical planarization (CMP) is presented. The model is based on the assumption that at the feature scale, high areas on the wafer experience higher pressure than low areas. A Prestonian material removal model is assumed. The model delineates how dishing and step height reduction depend on slurry properties (selectivity and Preston's constants), pad characteristics (stiffness and bending ability), polishing conditions (pressure, relative velocity and overpolishing) and wafer surface geometry (linewidth, pitch and pattern density). Model predictions are in good agreement with existing experimental observations. The present model facilitates understanding of the CMP process at the feature scale. Based on the proposed model, design avenues for decreasing dishing and increasing the speed of step height reduction may be explored through modification of appropriate parameters for slurry, pad and polishing conditions. The proposed model may also be used as a design tool for pattern layout to optimize the performance of the CMP process.     

Chemical mechanical polishing of polymer films

Strategies to reduce capacitance effects associated with shrinking integrated circuit (IC) design rules include incorporating low resistivity metals and insulators with low dielectric values, or “low-κ” materials. Using such materials in current IC fabrication schemes necessitates the development of reliable chemical mechanical polishing (CMP) processes and process consumables tailored for them. Here we present results of CMP experiments performed on FLARE™ 2.0 using a specialized zirconium oxide (ZrO₂) polishing slurry. FLARE™ 2.0 is a poly(arylene) ether from AlliedSignal, Inc. with a nominal dielectric constant of 2.8. In addition, we provide insight into possible removal mechanisms during the CMP of organic polymers by examining the performance of numerous abrasive slurries. Although specific to a limited number of polymers, the authors suggest that the information presented in this paper is relevant to the CMP performance of many polymer dielectric materials.     

The physical and electrical effects of metal-fill patterningpractices for oxide chemical-mechanical polishing processes

In oxide chemical-mechanical polishing (CMP) processes, layout pattern dependent variation in the interlevel dielectric (ILD) thickness can reduce yield and impact circuit performance. Metal-fill patterning practices have emerged as a technique for substantially reducing layout pattern dependent ILD thickness variation. We present a generalizable methodology for selecting an optimal metal-fill patterning practice with the goal of satisfying a given dielectric thickness variation specification while minimizing the added interconnect capacitance associated with metal-fill patterning. Data from two industrial-based experiments demonstrate the beneficial impact of metal-fill on dielectric thickness variation, a 20% improvement in uniformity in one case and a 60% improvement in the other case, and illustrate that pattern density is the key mechanism involved. The pros and cons of two different metal-fill patterning practices-grounded versus floating metal-are explored. Criteria for minimizing the effect of floating or grounded metal-fill patterns on delay or crosstalk parameters are also developed based on canonical metal-fill structures. Finally, this methodology is illustrated using a case study which demonstrates an 82% reduction in ILD thickness variation     

版图图形特征对铜化学研磨的影响

Copper chemical mechanical polishing （CMP） is influenced by geometric characteristics such as line width and pattern density, as well as by the more obvious parameters such as slurry chemistry, pad type, polishing pressure and rotational speed. Variations in the copper thickness across each die and across the wafer can impact the circuit performance and reduce the yield. In this paper, we propose a modeling method to simulate the polishing behavior as a function of layout pattern factors. Under the same process conditions, the pattern density, the line width and the line spacing have a strong influence on copper dishing, dielectric erosion and topography. The test results showed： the wider the copper line or the spacing, the higher the copper dishing; the higher the density, the higher the dielectric erosion; the dishing and erosion increase slowly as a function of increasing density and go into saturation when the density is more than 0.7.     

Statistical and Experimental Analysis of Correlated Time-Varying Process Variables for Conditions Diagnosis in Chemical–Mechanical Planarization

During chemical–mechanical planarization (CMP) of semiconductor wafers, chemical and mechanical process variables are strongly correlated and jointly affect polishing performance. The correlation among these process variables could potentially be utilized to characterize process conditions for the purpose of diagnosis. However, process variables measured during CMP, such as the temperature distribution and coefficient of friction between wafer and pad, vary with time and present in a functional form. This significantly increases the complexity of analyzing correlation patterns and relating them with process conditions. The focus of this paper is therefore twofold: 1) experimental investigation of the correlation between sensing process variables and the implication of correlation pattern changes on process conditions and 2) statistical analysis of correlation patterns between process variables in functional form. In the designed CMP experiment, we investigated two failure modes during CMP process: pad failure and slurry failure. Slurry failure was generated by reducing the percentage of oxidizer to investigate its effects on polishing performance and heat generation on the pad. Pad failure was due to variation of diamond abrasive sizes in the conditioner. The post-CMP study of nonuniformity and defects such as scratches on the wafer was conducted to characterize process conditions. The experimental and statistical results support the investigation of correlation among process variables for condition diagnosis.      

Pad Conditioning Density Distribution in CMP Process With Diamond Dresser

In the chemical-mechanical polishing (CMP) process, the pad conditioning density distribution plays a crucial role in the pad wear. A precise model and detailed analysis of a conditioning density function are required. To this end, at first we construct the mathematical model of polishing trajectories on the pad, then under the assumptions that the diamond grains are uniformly distributed and a slow sweeping motion is applied during dressing, the conditioning density distribution for a pad in CMP process is determined. This conditioning density function is verified through numerous numerical examples. In the mean time, it was also observed that to have a flat distribution of pad wear rate we have to make the ratio of disk-radius to pad-radius small, and the effect of the pattern of grain distribution on conditioning density function is insignificant, which agrees with known results from literature.     

Effect of alkaline slurry on the electric character of the pattern Cu wafer

For process integration considerations,we will investigate the impact of chemical mechanical polishing (CMP) on the electrical characteristics of the pattern Cu wafer.In this paper,we investigate the impacts of the CMP process with two kinds of slurry,one of which is acid slurry of SVTC and the other is FA/O alkaline slurry purchased from Tianjin Jingling Microelectronic Material Limited.Three aspects were investigated:resistance,capacitance and leakage current.The result shows that after polishing by the slurry of FA/O,the resistance is lower than the SVTC.After polishing by the acid slurry and FA/O alkaline slurry,the difference in capacitance is not very large. The values are 0.1 nF and 0.12 nF,respectively.The leakage current of the film polished by the slurry of FA/O is 0.01 nA,which is lower than the slurry of SVTC.The results show that the slurry of FA/O produced less dishing and oxide loss than the slurry of SVTC.     

Modeling of chemical-mechanical polishing considering thermal coupling effects

The removal of surface material in the conventional chemical-mechanical polishing (CMP) process is the result of synergetic effects of two dominant mechanisms: a mechanical process due to the abrasion of particles in the slurry, and a chemical process due to the reactions between the wafer and the chemicals in the slurry. In the overall material removal mechanism, in particular for metal layers, the mechanical and chemical effects are not independent, but are strongly coupled. Many models do not account for these coupling effects and cannot explain the non-Prestonian behavior that occurs when the material removal rate is a nonlinear function of the input areal power density. To address this deficiency and coupling effects, we propose a new integrated thermo-chemical-mechanical model that considers the synergistic effects of both the mechanical and chemical removal processes using the heat transfer mechanism as a bridge between them. In the modeling process, the material removal model is developed based on elastic and plastic contact mechanics and the dominant chemical reactions at the wafer surface. The temperature variation of the CMP system is treated as the coupling factor. The mechanical abrasion by the abrasive particles causes friction, which generates frictional heat on the contacting interfacial area. This heat plays a key role in accelerating the overall chemical reaction for the material removal. We performed a computer simulation with the proposed model using known parameters, and compared the results with other data to ensure its validity.     

Investigation of polishing characteristics of shallow trench isolation chemical mechanical planarization with different types of slurries

Ceria-based high selectivity slurry (HSS), which shows high polishing selectivity of silicon oxide to silicon nitride, was applied to the shallow trench isolation (STI) chemical mechanical planarization (CMP) process for giga-bit scale memory fabrication. While the wafer-to-wafer non-uniformity (WTWNU) and within-wafer non-uniformity (WIWNU) are superior to conventional silica-based slurry, the level of slurry induced scratches is too high for the ceria-based slurry to be used in present CMP processes. By optimizing the CMP process and filtering method, however, the number and depth of these scratches were reduced considerably to the level where the yield of gate oxide was sufficient to meet the requirement of manufacturing. In this paper, the authors discussed the possible causes of scratches when using ceria-based slurry and how these scratches affect to lower the breakdown yield of gate oxides. In addition, the authors investigated the relationship between within wafer non-uniformity and cell threshold voltage (V_t) variation and probe test 1 (PT1) yield variation.     

在集成电路量产中减少氧化膜CMP(化学机械研磨)的缺陷(英文)

在超大规模集成电路的生产中,减少氧化膜CMP中的各种缺陷一直是工程师们的工作焦点之一。实际上这些缺陷的尺寸、形状、深度等能为我们寻找它们的根源提供许多有益的信息。例如:在肉眼下可见的长、直、深的划伤可能与研磨垫修整器有关;只有在先进的检测设备下才可见的轻微、连续的划伤与与研磨剂有关。对常见缺陷进行分类,并提供一些可见的缺陷产生机制,同时也讨论了如何通过日常检测来监视真正产品上的缺陷。     

An analytical model of multiple ILD thickness variation induced byinteraction of layout pattern and CMP process

In this paper, an analytical model for chemical mechanical polishing (CMP) is described. This model relates the physical parameters of the CMP process to the in-die variation of interlayer dielectric (ILD) in multilevel metal processes. The physical parameters considered in this model include the deposited ILD profile, deformation of the polishing pad and the hydrodynamic pressure of slurry flow. Model parameters are adjusted based on the first ILD layer and then applied to the upper ILD layers. Comparison of simulated results with sample data is performed at the die level of a state-of-the-art microprocessor     

Device dependent control of chemical-mechanical polishing ofdielectric films

This paper presents a control scheme for run-to-run control of chemical-mechanical polishing (CMP). The control scheme tracks both device pattern dependent and equipment induced disturbances. The structure of the controller is such that sensitivity to qual (unpatterned blanket oxide) wafer frequency is minimized. Additionally, prethickness variation and metrology delay are accounted for in the design. Results from applying this scheme in volume production are presented     

Electrical characterization of the copper CMP process and derivation of metal layout rules

Design rules were developed for the layout of copper Damascene interconnect layers to minimize the within-die resistance variation. The impact of various layout configurations on the metal sheet resistance was characterized using two different test vehicles. An increase in resistance was observed on wide lines and high pattern densities due to dishing and dielectric erosion, respectively. In addition to the above, narrow lines were severely impacted by the presence of wide adjacent features in close proximity. The pattern interaction distance for copper chemical-mechanical planarization (CMP) was calculated by analyzing the resistance variation at the edge of a density or width transition. In this work, the interaction distance was found to be on the order of 25 /spl mu/m (as opposed to a few millimeters for oxide CMP). From these results, a window of about 50 to 60 /spl mu/m was found to be necessary to obtain the effective pattern density for copper CMP. The resistance of the upper metal level was a strong function of the underlying layer density. Hence, multilevel pattern dependencies have to be considered when modeling and predicting the line resistance on a real design. However, unlike oxide polish, pattern density alone is insufficient to predict the final copper thickness. Width-dependent spacing rules are necessary to prevent clustering of features (narrow lines very close to wide buses) and avoid regions of very low density.