宽带低副瓣微带反射阵列天线

为了实现便携式雷达设备的轻小型化,系统采用微带反射阵列天线替代传统的抛物反射面天线.该天线设计的难点是如何实现雷达工作频带内的天线低副瓣特性.采用微带延迟线的移相方案,并提出微带贴片与延迟线满足线性相移关系的匹配原则,实现了反射阵列天线的宽带低副瓣特性.实测结果表明,在X频段3.2%的带宽内,天线副瓣电平低于-25 dB,并且天线效率不低于50%.     

悬置微带线的过渡设计

设计了一种新型微带-悬置微带线和波导-悬置微带线的过渡结构。此过渡模型工艺简单、尺寸紧凑、加工精度不高,在较宽的频带范围内实现了较好的过渡特性。这种过渡设计可以改善悬置微带电路的应用范围,同其它电路或系统可以更好地综合应用。通过仿真设计和样品测试,在整个Ka频段,波导-悬置微带线过渡结构插入损耗小于0.75 dB。     

微带反射阵天线的分析与设计

介绍了微带反射阵天线的基本原理,分析了天线设计中阵元单元尺寸和间隔的计算、相位延迟线的选择、基片厚度的选取、误差分析、仿真验证等,根据分析结果提出了低副瓣微带反射阵天线的设计方法。实例测试结果表明,反射阵天线的总体性能接近抛物面天线的性能,易于折叠、携带方便。     

基于CSMRC的WR-3全频段三倍频器设计

给出了覆盖WR-3波导全频段的基于石英基片的高效率全频段平衡式三次倍频器的设计方法.采用紧凑悬置微带谐振器(Compact Suspended Microstrip Resonator Cell(CSMRC))作为倍频器的输入端滤波及匹配电路,不但提高了带外抑制,还有效地降低了电路尺寸和所需的腔体宽度.倍频器电路包括两个波导/悬置微带转换电路,一个反向并联二极管对、一个SCMRC和两段匹配传输线构成.通过仿真和测试结果的比对可以看出,设计及仿真方法是准确有效的.在225~330 GHz范围内,两套样品的测试输出功率为45~95μW,平均功率约为60μW.倍频器的最佳倍频效率对应的输入功率约为+5 d Bm,全频段范围内倍频效率为1.5%~3%.     

一种新型悬置微带滤波器的设计

本文给出一种新型的悬置微带滤波器结构，这种结构比常用的交指滤波器和发夹滤波器体积小。本文给出这种滤波器的设计公式。并设计了一个S波段窄带滤波器，试验结果和理论吻合很好。     

悬置微带与倒置微带微波滤波器及双工器

本文介绍了一种利用 Richards 频率交换近似设计悬置微带及倒置微带宽频带微波滤波器及双工器的方法。试验制作了2GHz 和4GHz 的低、高通滤波器及双工器。理论与实际比较相吻合。     

Ku波段高性能声体波微波延迟线的设计与优化

通过优化换能器拓扑结构、腔体结构和可调的微带匹配网络设计,研制出中心频率14 000 MHz、带宽1 500 MHz及延迟时间0.5 μs的Ku波段声体微波延迟线.该产品的插入损耗为-56 dB,直通抑制大于45 dB,三次渡越抑制大于55 dB,产品综合性能指标优异.     

新型高压脉冲体声波延迟线的设计

该文通过对换能器和延迟介质的优化设计,实现了一种新型高压脉冲体声波延迟线的研制。相比传统的声波延迟线,设计的延迟线具有高脉冲耐压性能,耐压高达2 kV;同时,其延迟线插损小,输出功率较大（瞬态可达2 W）,可充当新型无源功率MOS管驱动器,无需额外能量供给。试验表明设计的延迟线在大电流放电干扰情况下具有高延迟稳定性。     

微带线鳍线设计数据册

本书发表了用谱域中的Galerken全波方法计算的微带线、悬置微带线、槽线和单侧鳍线的归一化波导波长的色散特性和阻抗特性数据。全书共有44种表格,表1—14是微带线和耦合微带线,表15—26是悬置微带和耦合悬置微带线,表27—30是槽线和耦合槽线,表31—44是单侧鳍线和耦合单侧鳍线。这些表格基本上给出了常用结构尺寸、基片介电系数和使用频率范围的特性数据。本书可供从事高频、厘米波、毫米波技术的工程设计者、上述专业的专科生、本科生及研究生和教师设计时参考。     

二维电磁带隙结构研究的新方法

应用悬置微带线方法(SMM)对二维EBG结构进行了测量和计算。对二维电小EBG(UC—EBG和PV—EBG)的特性用SMM法进行了统一的实验和仿真分析。与其他方法对比，由于采用了“强耦合”结构，更能显现出二维电磁带隙结构的特性。同时提出了新型的悬置微带贴片的EBG天线，该天线结构紧凑，更利于EBG的实际应用。     

Microwave systems design for high-performance moving targetindicators in radars

Clutter cancellation of 65 dB and better is directly proportional to good radar stability, and since many hardware areas produce instabilities at various levels, the architecture of a radar requires special design considerations to support this high stability. The noise character and generation methods of these instabilities in the various hardware areas are described, and design solutions are given to eliminate them. Microwave delay line, a reliable, accurate method of measuring radar stability in L- and S-band radars, is described. The longest microwave delay line available for use at L -band and S-band frequencies is a 15-μs sapphire bulk acoustic wave (BAW) delay line. For higher-frequency radars, smaller delays must be used to keep the insertion loss down to a usable level. The question is raised as to the adequacy of this delay time to provide sufficient visibility for stability measurements of the stable noise. For transmitter measurements, it is adequate for the more common pulse widths, which are less than 15 μs. For LO measurements, the analysis shows that this delay does provide sufficient decorrelation for accurate LO noise measurements     

基于光传输的精密标准延时模块设计

该文在分析了基于光传输的延时系统原理的基础上,介绍了精密标准延时模块的组成。对模块的发射、传输、接收和放大等组成部分进行了理论分析和实际设计,重点讲述了光纤链路及逻辑控制的设计和实现。介绍了该模块时延特性测试系统的组成和搭建,并通过矢量网络分析仪对设计完成的光延时模块实物进行标准延时测试,分析对比测试结果,得出测量误差,并分析误差原因。该模块的实现为某系统的自校准提供了标准延时参考,同时可作为便捷有效的溯源手段。     

Design of PLL-based clock generation circuits

The design of clock generation circuitry being used as a part of a high-performance microprocessor chip set is described. A self-calibrating tapped delay line is used to generate four nonoverlapping clock phases of a system clock. A charge-pump phase-locked loop (PLL) calibrates the delay per stage of the delay line. Using this technique, it is possible to obtain an accurate phase relationship between the off-chip reference clock and the internal clock signals. Experimental results show that required timing relations can be obtained with less than 2-ns clock skew for frequencies from 1 to 18 MHz.     

An X-band acousto-optic variable delay line for radar targetsimulation

The design and characterization of a 54-μs, continuously-variable, acousto-optic (AO) delay line developed for radar testing applications is presented. Design goals for the delay line include over 10 MHz of instantaneous bandwidth, 1.2 GHz of tunable bandwidth operating at X-band, 45 dB of dynamic range, and electronically-controllable delay selection to simulate dynamic radar targets with radial range rates up to 500 m/s. In addition, the device was designed to have phase noise and spurious signal levels compatible with high performance radars. To achieve these goals, a 33-MHz center frequency variable delay line was constructed and coherent frequency translation was used to provide operation at S-band. Operating principles for this new intermediate frequency (IF) delay line are presented, and key component issues are discussed. A computer design and analysis tool is described that predicts delay line performance. Experimental results are presented at both the IF and at X-band     

相控阵雷达天线延时技术的发展

介绍了相控阵雷达天线在大扫描角及大瞬时带宽应用场景下延时补偿技术的发展概况。对天线阵列的波束色散现象以及延时补偿技术对天线方向图的影响进行了分析,并介绍了国内外的一些延时方案。依据延时实现架构,将其分为微波延时、表面声波延时、光延时以及数字延时四类。重点对微波延时的几种不同类型的实现形式进行了描述,并根据微波延时线实现载体的不同,分为GaAs 芯片、射频电缆、印制板和微同轴四种。另外,针对延时拓扑电路进行理论推导分析,说明单延时路径在电路设计上的优势,并分析了基态链路对延时路径的幅度、相位补偿和介质材料对延时量的误差引入。对相控阵雷达天线在大扫描角及大瞬时带宽应用场景下的延时补偿技术研究有一定参考价值。     

Shielding effect of on-chip interconnect inductance

Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an RLC load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall delay to drive an RLC load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, reducing dynamic power dissipation. Average reductions in power of 17% and area of 29% are achieved for example circuits. An accurate model for a CMOS inverter and an RLC load is used to characterize the propagation delay. The accuracy of the delay model is within an average error of less than 9% as compared to SPICE.     

声表面波延迟线

声表面波延迟线是在雷达和通信系统中应用非常广泛的器件.文中结合实用声表面波延迟线器件的设计实例,介绍了折叠式固定延迟线结构原理和设计计算,克服了传统延迟线受基片材料长度和器件尺寸的限制,满足了雷达、通信等电子设备中对电信号的长延迟需求;同时还讨论了为满足超高频的应用需求和增加相对带宽,所采用的谐波和倒相换能器的设计方法.     

Effects of inductance on the propagation delay and repeaterinsertion in VLSI circuits

A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale     

High-speed ultrasonic digital delay line design: A restatement of some basic considerations

In the past, ultrasonic delay lines in digital storage applications tended to be designed for a maximum storage capacity compatible with losses in the delay medium in order to minimize the cost of access circuitry. This approach yielded capacities upward of 20 000 bits per delay line but necessitated complicated arrangements to fold up the relatively long delay path in an acceptable space. It also required delay materials with a low ultrasonic propagation loss and accurate temperature stabilization, and resulted in comparatively long average access times to a given bit of information in the store. The emergence of inexpensive access and retiming circuits, however, suggests that delay line stores may be made at lower expense by subdividing them into modules of smaller capacity, and regenerating and retiming the bit stream it each module. This approach leads to design considerations different from the previous approaches and causes requirements of mechanical precision and temperature stability to be lowered. The design procedure described predicts that with presently available materials delay lines can be built which store about 1000 bits at bit rates in excess of 100 MHz, with insertion losses at band center of less than 20 dB and spurious signal suppression of at least 20 dB. Such lines have a storage density of more than 10⁵bits per inch³.     

Heuristic performance model of optical buffers for variable length packets

Optical switching (optical packet switching, optical burst switching, and others) provides alternatives to the current switching in backbone networks. To switch optically, also packet buffering is to be done optically, by means of fiber delay lines (FDLs). Characteristic of the resulting optical buffer is the quantization of possible delays: Only delays equal to the length of one of the FDLs can be realized. An important design challenge is the optimization of the delay line lengths for minimal packet loss. To this end, we propose a heuristic based on two existing queueing models: one with quantization and one with impatience. Combined, these models yield an accurate performance modeling heuristic. A key advantage of this heuristic is that it translates the optical buffer problem into two well-known queueing problems, with accurate performance expressions available in the literature. This paper presents the heuristic in detail, together with several figures, comparing the heuristic’s output to existing approaches, validating its high accuracy.