A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$ 98 dB THD, and 79 dB SNDR

This paper describes a wideband high-linearity $Delta Sigma $ ADC. It uses noise coupling combined with time interleaving. Two versions of a two-channel time-interleaved noise-coupled $Delta Sigma $ ADC were realized in a 0.18- $mu{hbox {m}}$ CMOS technology. Noise coupling between the channels increases the effective order of the noise-shaping loops, provides dithering, and prevents tone generation in all loops. Time interleaving enhances the effects of noise coupling. Using a 1.5 V supply, the device achieved excellent linearity (${rm SFDR} > {hbox {100~dB}}$, ${rm THD}= -{hbox {98~dB}}$) and an SNDR of 79 dB in a 4.2 MHz signal band.      

A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS

This paper describes a digitally calibrated pipeline analog-to-digital converter (ADC) implemented in 90 nm CMOS technology with a 1.2 V supply voltage. A digital background calibration algorithm reduces the linearity requirements in the first stage of the pipeline chain. Range scaling in the first pipeline stage enables a maximal 1.6$ {rm V}_{rm pp}$ input signal swing, and a charge-reset switch eliminates ISI-induced distortion. The 14b ADC achieves 73 $~$dB SNR and 90 dB SFDR at 100 MS/s sampling rate and 250$~$mW power consumption. The 73 dB SNDR performance is maintained within 3 dB up to a Nyquist input frequency and the FOM is 0.68 $~$pJ per conversion-step.      

A 0.55 V 60 dB-DR Fourth-Order Analog Baseband Filter

A 0.55 V supply voltage fourth-order low-pass continuous-time filter is presented. The low-voltage operating point is achieved by an improved bias circuit that uses different opamp input and output common-mode voltages. The fourth-order filter architecture is composed by two Active- ${rm G}_{rm m}{-}{rm RC}$ biquadratic cells, which use a single opamp per-cell with a unity-gain-bandwidth comparable to the filter cut-off frequency. The $-$ 3 dB filter frequency is 12 MHz and this is higher than any other low-voltage continuous-time filter cut-off frequency. The $-$3 dB frequency can be adjusted by means of a digitally-controlled capacitance array. In a standard 0.13 $mu{rm m}$ CMOS technology with ${V}_{THN}approx 0.25 {rm V}$ and ${V}_{THP}approx 0.3 {rm V}$, the filter operates with a supply voltage as low as 0.55 V. The filter $({rm total} {rm area}=0.47 {rm mm}^{2})$ consumes 3.4 mW. A 8 dBm-in-band IIP3 and a 13.3 dBm-out-of-band IIP3 demonstrate the validity of the proposal.      

A 1.2-V 12-b 120-MS/s SHA-Free Dual-Channel Nyquist ADC Based on Midcode Calibration

This paper describes a 12-b 120-MS/s dual-channel pipeline analog-to-digital converter (ADC) for high-speed video signal processing. A simple digital midcode calibration technique is proposed to eliminate an offset mismatch between two channels. The proposed sample-and-hold-amplifier-free architecture with correlated input sampling networks enables wideband signal sampling while effectively reducing a gain mismatch between channels. The prototype ADC implemented in a 0.13-$mu{hbox {m}}$ CMOS technology achieves a peak signal-to-noise-and-distortion ratio of 61.1 dB and a peak spurious-free dynamic range of 74.7 dB for input frequencies up to 60 MHz at 120 MS/s. The measured differential and integral nonlinearities are within $pm 0.30$ LSB and $pm 0.95$ LSB, respectively. The ADC occupies an active die area of $0.56~{hbox {mm}}^{2}$ and consumes 51.6 mW at a 1.2 V power supply.      

A Biphase Modulator Circuit for Impulse Radio-UWB Applications

This letter presents a circuit to provide binary phase shift keying to ultra-wideband (UWB) impulse transmitters. The circuit is based on a Gilbert-cell multiplier and uses active on-chip balun and unbalanced-to-balanced converters for single-ended to single-ended operation. Detailed measurements of the circuit show a gain ripple of $pm 1~{rm dB}$ at an overall gain of $-2~{rm dB}$, an input reflection below $-12~{rm dB}$, an output reflection below $-18~{rm dB}$, a group delay variation below 6 ps and a $-1~{rm dB}$ input compression point of more than 1 dBm in both switching states over the full 3.1–10.6 GHz UWB frequency range. A time domain measurement verifies the switching operation using an FCC-compliant impulse generator. The circuit is fabricated in a $0.8~mu {rm m}$ Si/SiGe HBT technology, consumes 31.4 mA at a 3.2 V supply and has a size of $510 times 490~mu{rm m}^{2}$ , including pads. It can be used in UWB systems using pulse correlation reception or spectral spreading.      

A 100 MS/s 4 MHz Bandwidth 70 dB SNR $Delta Sigma$ ADC in 90 nm CMOS

This paper describes the results of an implementation of a high speed $Delta Sigma$ ADC in 90 nm CMOS process, which is developed for a direct-conversion digital TV receiver. The $Delta Sigma$ ADC is based on a switched-capacitor fourth-order single-loop $Delta Sigma$ modulator with a 4-bit quantizer. The ADC uses a triple sampling technique and a two-step summation scheme for low power and high speed operation. Also, a digital signal processing block, including a decimation filter, a channel selection filter and a digital programmable gain amplifier (PGA), is implemented in the same process. The decimation filter is based on a polyphase IIR filter with a decimation ratio of 5, while the channel selection filter is based on two path lattice wave digital IIR filter. The ADC achieves 69.95 dB SNR and 66.85 dB SNDR over a 4 MHz bandwidth with a sampling frequency of 100 MHz. The fabricated $Delta Sigma$ ADC and the digital signal processing block occupy 0.53$~$mm$^2$ and 0.09 mm$^{2}$, and consume 11.76 mW per channel.      

W-Band Active Down-Conversion Mixer in Bulk CMOS

A W-band (76–77 GHz) active down-conversion mixer has been demonstrated using low leakage (higher ${rm V}_{{rm T}}$) NMOS transistors of a 65-nm digital CMOS process with 6 metal levels. It achieves conversion gain of ${-}8$ dB at 76 GHz with a local oscillation power of 4 dBm (${sim-}2$ dBm after de-embedding the on-chip balun loss), and 3 dB bandwidth of 3 GHz. The SSB noise figures are 17.8–20 dB (11.3–13.5 dB after de-embedding on-chip input balun loss) between 76 and 77 GHz. ${rm IP}_{1{rm dB}}$ is ${-}6.5$ dBm and IIP3 is 2.5 dBm (${sim-}13$ and ${sim}-4$ dBm after de-embedding the on-chip balun loss). The mixer consumes 5 mA from a 1.2 V supply.      

A 10-bit 50 MS/s Pipelined ADC With Capacitor-Sharing and Variable-$g_{m}$ Opamp

A pipelined analog-to-digital converter (ADC) architecture which is suitable for low power and small area is presented. The prototype ADC achieves 10-bit resolution with only two opamps by removing a front-end sample-and-hold amplifier (SHA) and sharing an opamp between two successive pipeline stages. The errors from the absence of SHA and opamp-sharing are greatly reduced by the proposed techniques and circuits. Further reduction of power and area is achieved by using a capacitor-sharing technique and variable- $g_{m}$ opamp. The ADC is implemented in 0.18 $muhbox{m}$ CMOS technology and occupies a die area of 0.86 ${hbox{mm}}^{2}$. The differential and integral nonlinearity of the ADC are less than 0.39 LSB and 0.81 LSB, respectively, at full sampling rate. The ADC achieves 56.2 dB signal-to-noise plus distortion ratio, 72.7 dB spurious free dynamic range, ${-}$66.2 $~$dB total harmonic distortion, 9.03 effective number of bits for a Nyquist input at full sampling rate, and consumes 12 mW from a 1.8 V supply.      

A 3–10 GHz CMOS UWB Low-Noise Amplifier With ESD Protection Circuits

A low-power fully integrated low-noise amplifier (LNA) with an on-chip electrostatic-static discharge (ESD) protection circuit for ultra-wide band (UWB) applications is presented. With the use of a common-gate scheme with a ${rm g}_{rm m}$ -boosted technique, a simple input matching network, low noise figure (NF), and low power consumption can be achieved. Through the combination of an input matching network, an ESD clamp circuit has been designed for the proposed LNA circuit to enhance system robustness. The measured results show that the fabricated LNA can be operated over the full UWB bandwidth of 3.0 to 10.35 GHz. The input return loss $({rm S}_{11})$ and output return loss $({rm S}_{22})$ are less than ${-}8.3$ dB and ${-}9$ dB, respectively. The measured power gain $({rm S}_{21})$ is $11 pm 1.5$ dB, and the measured minimum NF is 3.3 dB at 4 GHz. The dc power dissipation is 7.2 mW from a 1.2 V supply. The chip area, including testing pads, is 1.05 mm$,times,$ 0.73 mm.      

A K-Band CMOS Quadrature Frequency Tripler Using Sub-Harmonic Mixer

A low-power frequency tripler is designed by using the sub-harmonic mixer configuration for K-band applications. The proposed circuit features quadrature signal generation, applicable to LO signal synthesis in millimeter-wave wireless transceivers. It achieves conversion gain of $-$5.7 dB at the output frequency of 21 GHz. Implemented in a 0.18 $mu{rm m}$ CMOS technology, the circuit consumes power of 7.5 mW with 1.5 V supply voltage. The entire die occupies an area of $1000times 1050 mu{rm m}^{2}$.      

A 10 MS/s 11-bit 0.19 mm $^{2}$ Algorithmic ADC With Improved Clocking Scheme

A 10 MS/s 11-bit algorithmic ADC with an active area of 0.19$~{hbox{mm}}^{2}$ is presented. Using an improved clocking scheme, this design overcomes the speed limit of algorithmic ADCs. The proposed ADC employs amplifier sharing, DC offset cancellation, and input memory effect suppression, resulting in reduced area and power, and high linearity. The ADC implemented in a 0.13$~mu{hbox{m}}$ thick gate-oxide CMOS process achieves 69 dB SFDR, 58 dB SNR, and 56 dB SNDR, while consuming 3.5 mA from a 3 V supply.      

Q-Band pHEMT and mHEMT Subharmonic Gilbert Upconversion Mixers

This letter makes a comparison between Q-band 0.15 $mu{rm m}$ pseudomorphic high electron mobility transistor (pHEMT) and metamorphic high electron mobility transistor (mHEMT) stacked-LO subharmonic upconversion mixers in terms of gain, isolation and linearity. In general, a 0.15 $mu{rm m}$ mHEMT device has a higher transconductance and cutoff frequency than a 0.15 $mu{rm m}$ pHEMT does. Thus, the conversion gain of the mHEMT is higher than that of the pHEMT in the active Gilbert mixer design. The Q-band stacked-LO subharmonic upconversion mixers using the pHEMT and mHEMT technologies have conversion gain of $-$7.1 dB and $-$0.2 dB, respectively. The pHEMT upconversion mixer has an ${rm OIP}_{3}$ of $-$12 dBm and an ${rm OP}_{1 {rm dB}}$ of $-$24 dBm, while the mHEMT one shows a 4 dB improvement on linearity for the difference between the ${rm OIP}_{3}$ and ${rm OP}_{1 {rm dB}}$. Both the chip sizes are the same at 1.3 mm $times$ 0.9 mm.      

Oversampling A/D Converters With Reduced Sensitivity to DAC Nonlinearities

To alleviate the image-rejection requirements of the front-end filters and the feedback digital-to-analog converter (DAC) matching requirements, an oversampling complex discrete-time (DT) $DeltaSigma$ analog-to-digital converter (ADC) with a signal-transfer function that achieves significant filtering of interfering signals is proposed. With a filtering signal transfer function (STF) and stopband attenuation greater than 30 dB, the $DeltaSigma$ modulator reduces the intermodulation of the desired signal and the interfering signals at the input of a quantizer, and also avoids feedback of high-frequency interfering signals at the input of the modulator. This filtering of the interfering signals reduces sensitivity to DAC nonlinearities. The reported DT complex $DeltaSigma$ ADC is intended for digital television (DTV) receiver applications. With a maximum intended sampling frequency of 128 MHz and an oversampling ratio of 16, the ADC has been designed to support a maximum DTV signal bandwidth of 8 MHz. The IC achieved a 70.9-dB signal-to-noise-and-distortion ratio over a 6-MHz band centered around 3 MHz. The image-rejection ratio of the $DeltaSigma$ ADC was measured to be greater than 65 dB. The fabricated chip consumes 122.4 mW and occupies a silicon area of 2.15 $hbox{mm}^{2}$.      

A 108 dB SNR, 1.1 mW Oversampling Audio DAC With A Three-level DEM Technique

A low power audio oversampling $Sigma Delta $ digital-to-analog converter (DAC) with a three-level $(+1,~0,-1)$ dynamic-element-matching (DEM) technique and an inter-symbol interference-free (ISI) output stage is presented. Solutions for design challenges such as ISI, clock jitter sensitivity, and out-of-band noise are presented. The converter is fabricated in a 0.18 $mu{hbox {m}}$ CMOS process, occupies 0.55 ${hbox {mm}}^{2}$, achieves 108 dB dynamic range, $-98~{rm dB ~THD}+{rm N}$ while consumes a total of 1.1 mW per channel at 1.8 V supply.      

A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification

A low-power pipelined ADC featuring dynamic source follower amplifiers is presented in this paper. The proposed dynamic source follower-based architecture provides a low-power alternative to the traditional opamp-based MDAC circuits. This new type of circuit dynamically charges its load capacitance without a large bias current, leading to significant power savings. The presented ADC includes a low-power comparator with offset calibration and uses digital calibration for gain correction. Measured results indicate that the 9.4-bit, 50-MS/s prototype ADC achieves an SNDR of 49.2 dB (7.9 ENOB) and consumes 1.44$~$mW from a 1.2-V supply, resulting in a figure of merit of 119 $~$fJ/conversion-step. The converter's input capacitance is 90 fF and the total active area is 0.123 $ {hbox {mm}}^{2}$ in a 90 $~$nm CMOS process.      

A 0.7-V 870-$mu$ W Digital-Audio CMOS Sigma-Delta Modulator

This paper introduces a power-efficient, chopper-stabilized switched-capacitor sigma-delta $(SigmaDelta)$ modulator that combines delayed input feedforward and single-comparator tracking multi-bit quantization to achieve high-precision, low-voltage analog-to-digital (A/D) conversion. An experimental prototype of the proposed architecture has been integrated in a 0.18-$mu{hbox {m}}$ CMOS technology. The prototype operates from a 0.7-V supply voltage with a sampling rate of 5 MSamples/sec and consumes only 870$ muhbox{W}$ of total power. The converter achieves a dynamic range of 100 dB, a peak signal-to-noise ratio (SNR) of 100 dB and a peak signal-to-noise and distortion ratio (SNDR) of 95 dB for a 25-kHz signal bandwidth.      

A Linearization Technique for RF Receiver Front-End Using Second-Order-Intermodulation Injection

A linearization technique is proposed in which low-frequency second-order-intermodulation $({rm IM}_{2})$ is generated and injected to suppress the third-order intermodulation $({rm IM}_{3})$. The proposed linearization technique is applied to both a low-noise amplifier (LNA) and a down-conversion mixer in an RF receiver front-end (RFE) working at 900 MHz. Fabricated in a 0.18$ mu{hbox{m}}$ CMOS process and operated at 1.5 V supply with a total current of 13.1 mA, the RFE delivers 22 dB gain with 5.3 dB noise figure (NF). The linearization technique achieves around 20 dB ${rm IM}_{3}$ suppression and improves the RFE's ${rm IIP}_{3}$ from $-$ 10.4 dBm to 0.2 dBm without gain reduction and noise penalty while requiring only an extra current of 0.1 mA.      

A Fully Integrated 5 GHz Low-Voltage LNA Using Forward Body Bias Technology

A fully integrated 5 GHz low-voltage and low-power low noise amplifier (LNA) using forward body bias technology, implemented through a 0.18 $mu{rm m}$ RF CMOS technology, is demonstrated. By employing the current-reused and forward body bias technique, the proposed LNA can operate at a reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 10.23 dB with a noise figure of 4.1 dB at 5 GHz, while consuming only 0.8 mW dc power with a low supply voltage of 0.6 V. The power consumption figure of merit $(FOM_{1})$ and the tuning-range figure of merit $(FOM_{2})$ are optimal at 12.79 dB/mW and 2.6 ${rm mW}^{-1}$, respectively. The chip area is 0.89 $,times,$0.89 ${rm mm}^{2}$.      

A Single-Ended Fully Integrated SiGe 77/79 GHz Receiver for Automotive Radar

A single-ended 77/79 GHz monolithic microwave integrated circuit (MMIC) receiver has been developed in SiGe HBT technology for frequency-modulated continuous-wave (FMCW) automotive radars. The single-ended receiver chip consists of the first reported SiGe 77/79 GHz single-ended cascode low noise amplifier (LNA), the improved single-ended RF double-balanced down-conversion 77/79 GHz micromixer, and the modified differential Colpitts 77/79 GHz voltage controlled oscillator (VCO). The LNA presents 20/21.7 dB gain and mixer has 13.4/7 dB gain at 77/79 GHz, and the VCO oscillates from 79 to 82 GHz before it is tuned by cutting the transmission line ladder, and it centres around 77 GHz with a tuning range of 3.8 GHz for the whole ambient temperature variation range from $- hbox{40},^{circ}{hbox{C}}$ to $+ hbox{125},^{circ}{hbox{C}}$ after we cut the lines by tungsten-carbide needles. Phase noise is $-$90 dBc/Hz@1 MHz offset. Differential output power delivered by the VCO is 5 dBm, which is an optimum level to drive the mixer. The receiver occupies 0.5 ${hbox{mm}}^{2}$ without pads and 1.26 ${hbox{mm}}^{2}$ with pads, and consumes 595 mW. The measurement of the whole receiver at 79 GHz shows 20–26 dB gain in the linear region with stable IF output signal. The input ${rm P}_{rm 1dB}$ of the receiver is $-$35 dBm.      

Tunable Linear MOS Resistors Using Quasi-Floating-Gate Techniques

A family of tunable MOS resistors based on quasi-floating-gate (QFG) transistors biased in the triode region is analyzed in this paper. From the study results, a new device that outperforms previous implementations, is presented. By means of a capacitive divider, the ac component of the drain-to-source voltage scaled with a factor $alphaleq 1$ is added to the gate-to-source voltage leading to a cancellation of the nonlinear terms. The effect of $alpha$ on resistor linearity is analytically studied. Simulation results are also provided for different technologies. Finally, a complete transconductor has been built which preserves the linearity of the MOS resistor. Three versions of the transconductor have been fabricated for different values of $alpha$ ($alpha=$ 0, 0.5, and 1) in a 0.5 $mu{hbox {m}}$ CMOS technology with $pm$1.65-V supply voltage. Experimental results show (for $alpha=1$ ) a THD of $-$ 57 dB $({rm HD}2=-70 {hbox {dB}})$ at 1 MHz for 2-V peak-to-peak differential input signal with a nominal ac-transconductance of 200 $muhbox{A/V}$ and a power consumption of 3.2 mW.