基于神经网络方法的半导体生产工艺优化

以提高生产成品率为目标,利用神经网络的非线性和容错性,对半导体芯片生产过程进行了分析和优化,具体内容如下：（１）使用神经网络方法建立模型,确定生产线上工艺参数和成品率之间的映射关系,构造以工艺参数为输入,成品率为输出的多维函数曲面．（２）对上述多维函数曲面进行搜索,搜索成品率最高的最优点,以该最优点的工艺参数值为依据确定工艺参数的规范值．（３）对工艺参数规范进行优化,在实际生产工艺中反复实践,直至达到提高成品率的目的．生产实践证明,神经网络的分析结果是合理的．根据神经网络分析提出的优化建议,有效地提高了工     

Relationship between wafer edge design and its ultimate mechanical strength

Due to its brittle nature, high stress-induced in manufacturing process, silicon wafer breakage has become a major concern for all semiconductor fabrication line. Furthermore, the production cost had increased in advanced technology day by day. Even a some-percent breakage loss drives device costs up significantly if wafers are broken near completion. Consequently, wafer breakage even near the beginning of the process is significant. In short words, silicon wafer breakage has become a major concern for all semiconductor fabrication lines, and so high stresses are easily induced in its manufacture process. The production cost is increasing even breakage loss of a few percent significantly drives device costs up, if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength employing a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.A physical model would also be proposed to explain the results. This model demonstrates that the fracture rate of wafers can be reduced by controlling the uniformity of the difference between the front and rear bevel lengths during the wafer manufacturing process.     

Control of MMST RTP: repeatability, uniformity, and integration forflexible manufacturing [ICs]

A real-time multivariable strategy is used to control the uniformity and repeatability of wafer temperature in rapid thermal processing (RTP) semiconductor device manufacturing equipment. This strategy is based on a physical model of the process where the model parameters are estimated using an experimental design procedure. The internal model control (IMC) law design methodology is used to automatically compute the lamp powers to a multizone array of concentric heating zones to achieve wafer temperature uniformity. Control actions are made in response to real-time feedback information provided by temperature sensing, via pyrometry, at multiple points across the wafer. Several modules, including model-scheduling and antiovershoot, are coordinated with IMC to achieve temperature control specifications. The control strategy, originally developed for prototype equipment at Stanford University, is analyzed via the customization, integration, and performance on eight RTP reactors at Texas Instruments conducting thirteen different thermal fabrication operations of two sub-half-micron CMOS process technologies used in the the Microelectronics Manufacturing Science and Technology (MMST) program     

A Novel Virtual Metrology Scheme for Predicting CVD Thickness in Semiconductor Manufacturing

In an advanced semiconductor fab, online quality monitoring of wafers is required for maintaining high stability and yield of production equipment. The current practice of only measuring monitor wafers may not be able to timely detect the equipment-performance drift happening in-between the scheduled measurements. This may cause defects of production wafers and, thereby, raise the production cost. In this paper, a novel virtual metrology scheme (VMS) is proposed for overcoming this problem. The proposed VMS is capable of predicting the quality of each production wafer using parameters data from production equipment. Consequently, equipment-performance drift can be detected promptly. A radial basis function neural network is adopted to construct the virtual metrology model. Also, a model parameter coordinator is developed to effectively increase the prediction accuracy of the VMS. The chemical vapor deposition (CVD) process in semiconductor manufacturing is used to test and verify the effectiveness of the proposed VMS. Test results show that the proposed VMS demonstrates several advantages over the one based on back-propagation neural network and can achieve high prediction accuracy with mean absolute percentage error being 0.34% and maximum error being 1.15%. The proposed VMS is simple yet effective, and can be practically applied to construct the prediction models of semiconductor CVD processes.     

Minimum inventory variability schedule with applications insemiconductor fabrication

A typical semiconductor wafer fab contains many different products and processes, some with small quantities, competing for resources. Each product row can contain hundreds of processing steps demanding production time of the same resource many times during the row. When this re-entry requirement is compounded with multiple product flows, short interval scheduling becomes important. Scheduling to reduce variations and to balance the whole wafer production line becomes a very complex issue. We investigate in this paper a new scheduling policy called minimum inventory variability scheduling (MIVS). This scheduling policy can significantly reduce the mean and variance of cycle-time in semiconductor fabs. The conclusions are based on the real world implementation in two major semiconductor fabs since 1990, and a simulation study of a much simplified hypothetical re-entrant network to capture the nature of semiconductor manufacturing. A discrete event simulation model was used to compare MIVS with five different popular dispatching policies (FIFO, SNQ, LNQ, RAN, and CYC) practised in wafer fabrication environments. The results gained on two factory floors and the simulation model indicate that dispatching policies have a significant impact on performance. The simulation results show that the MIVS dispatching policy demonstrated a percentage improvement over all other tested dispatching policies     

Simultaneous control of multiple measures of nonuniformity usingsite models and monitor wafer control

Present day semiconductor manufacturing processes are subject to tight specifications. High yields with tight process specifications require drive to target process control. As the size of the wafer in the semiconductor industry increases, nonuniformity across the wafer becomes a crucial yield limiting issue. Modeling nonuniformity in terms of the equipment settings permits calculation of recipes required to achieve the desired nonuniformity. However, models for single measures of nonuniformity, such as standard deviation, or range, do not capture all aspects of the nonuniformity and often do not model well in terms of the equipment settings. This paper describes the use of spatial models to simultaneously quantify multiple measures of nonuniformity, and a controller to keep the nonuniformities within specifications, Use of spatial models in conjunction with a monitor wafer controller (MWC) enables the simultaneous control of multiple nonuniformity measures. The paper presents the results of applying the MWC with spatial models to a plasma enhanced TEOS (PETEOS) deposition process on an Applied Materials Precision 5000 (AMT5000). The controller has been keeping the PETEOS process within specifications for over two years     

Modeling and performance analysis of cluster tools using Petri nets

The performance of cluster tools is gaining ever-increasing importance as the semiconductor industry migrates to larger wafer sizes, and smaller device geometries. Customers demand higher throughput-to-footprint ratios for semiconductor equipment. Cluster tool throughput is the outcome of complex interactions of various subsystems, and there is a critical need for appropriate tools that aid in understanding these interactions, and their effects on throughput. Current methods for throughput analysis are not very well oriented toward understanding the dynamics in cluster tool processing. In this paper we present a procedure to model cluster tools using Petri nets. These models help designers to comprehend the flow of wafers during processing. While Petri nets have been used extensively in the modeling and analysis of diverse manufacturing processes/systems, this to the best of our knowledge is the first attempt to specifically model cluster tools. A state cycle analysis is discussed next; this method enables equipment designers to extract steady state throughput information, as well as understand the interplay of subsystems during the wafer Row. Two example configurations are used to illustrate Petri net-based model building and analysts. These two examples encompass a variety of design features found in the industry today, e.g., sequential and parallel processing, single and dual end effector robots, anticipatory and simple scheduling     

Systematic defect improvement integration of dual damascene processes development on nano semiconductor fabrication

Process defects of semiconductor wafer nanotechnology manufacturing process can often impact product yields, depending on the type, size, and location of the defect, as well as the design and yield sensitivity of the respective semiconductor product devices. Manufacturing process-induced defects prevention should begin with an assessment of the critical risks associated with the wafer fabrications. Systematic identification and classification approaches have been introduced to improve the process yield by defects sampling and images reviewing. This study presents comprehensive investigation of a process defects monitor and integration on semiconductor copper manufacturing process and technology, and module process integration of the problem of defects reduction on semiconductor manufacturing processes. Experiments on electrical devices were performed to identify the defect source and determine the mechanism of defect formation, and integrated manufacturing processes implemented to eliminate defect issues are also investigated.     

An optimal residency-aware scheduling technique for cluster tools with buffer module

Cluster tools provide a flexible, reconfigurable, and efficient environment for several manufacturing processes (e.g., semiconductor manufacturing). A new timing constraint (distinct from a simple deadline), referred to as residency constraint, puts a timing limit on the time that a wafer can stay in a processing module in a cluster tool. The authors demonstrate that a solution that does not address residency constraints can be found easily. However, when residency constraints are added to the model, the problem becomes complex and a scheduling technique may spend a long time searching for a good solution. Also, in some cases, one may need to decrease throughput to satisfy residency constraints. The authors introduce a new technique to address cluster tool scheduling in the presence of residency constraints. The proposed technique uses a buffer resource for temporarily holding wafers to release other resources such as the robot arm. This resource is usually available in the tool for maintenance reasons. A tradeoff is discussed in using the buffer resource and a scheduling algorithm is presented that will use this resource when it can help to increase throughput under residency constraints. The experiments show that in many cases that are common in semiconductor manufacturing, use of their proposed technique can improve throughput.     

Relationship between wafer fracture reduction and controlling during the edge manufacturing process

Given the trend towards wafers of a larger diameter, microelectronics circuits are driven by modern IC manufacturing technology. Silicon wafer breakage has become a major concern of all semiconductor fabrication lines because silicon wafer is brittle and high stresses are induced in the manufacturing process. Additionally, the production cost is increasing. Even a breakage loss of a few per cent drives up device costs significantly if wafers are broken near completion, but wafer breakage even near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength empolying a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.This work presents an approach for characterizing silicon wafer failure strength using a simple drop test, to improve our understanding of the stress accumulated in wafer bulk before failure. However, this work will describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unknown reasons. According to an analysis based on the material mechanical theory for the bevel lengths (A1, A2), the edge length and the bevel angle (θ) are optimized to design the edge profile of the produced wafer, to prevent wafer breakage. Restated, when proper material and process control techniques are utilized, silicon wafer breakage should be prevented. This work is the first to demonstrate the importance of understanding wafer strength using a simple mechanical approach.     

Quantifying the benefits of cycle time reduction in semiconductorwafer fabrication

In recent years, semiconductor manufacturing has become increasingly complex due to device size reduction. Hence the manufacturing cycle time, also called turn around time (TAT), which is defined as the time required from wafer input through probing test, becomes longer year by year. This renders the delay between the occurrence of process defects and their detection a significant problem. On the other hand, customer demands for faster delivery are increasing as product life cycles are getting shorter. Hence, TAT reduction is important for semiconductor manufacturers not only to satisfy customer requirements, but also to remain competitive in their market. This paper examines the financial benefits of TAT reduction in ramping up a new process using stochastic simulation. Results indicate that reducing TAT in the ramp-up phase is important, and that even small reductions can have significant effects over the life cycle of a process     

半导体晶圆制造车间层控制的内容及方法

半导体晶圆制造企业是资本密集、技术密集型产业,晶圆制造厂也是公认生产最为复杂的工厂之一。产品更新换代快、市场竞争激烈等特点使得投资者对设备产能和设备利用率高度重视。这已不仅仅是技术问题,而是生产制造过程管理的问题。本文介绍了半导体晶圆制造车间层控制的内容及方法。     

CMP系统中抛光头与抛光台运动关系分析

目前半导体制造技术已经进入0.13μm、300mm时代,随着硅片尺寸的增大以及特征线宽的减小,作为目前硅片超精密平坦化加工的主要手段-化学机械平坦化,已经成为IC制造技术中不可缺少的技术。介绍了在化学机械抛光过程中,可以通过抛光头与抛光台运动速度关系优化配置,降低晶片表面不均匀度,从而更好地实现晶片局部和全局平坦化。     

A queueing network model for semiconductor manufacturing

We develop an open queueing network model for rapid performance analysis of semiconductor manufacturing facilities. While the use of queueing models for performance evaluation of manufacturing systems is not new, our approach differs from others in the detailed ways in which we model the different tool groups found in semiconductor wafer fabrication, as well as the way in which we characterize the effect of rework and scrap on wafer lot sizes. As an application of the model, we describe a method for performing tool planning for semiconductor lines. The method is based on a marginal allocation procedure which uses performance estimates from the queueing network model to determine the number of tools needed to achieve a target cycle time, with the objective being to minimize overall equipment cost     

半导体生产线建模方法与调度策略研究进展

半导体生产线是典型多重入复杂的制造系统，具有可重入性、复杂性、不确定性、多目标和多约束等特点，其优化调度问题是近年来控制领域的一个重要研究方向．本文根据近些年来这一研究方向上的主要研究成果，系统评述了国内外半导体生产线调度的建模方法和调度策略的研究进展，分析和讨论它们各自的主要优缺点和适用范围，简要介绍了重调度判定依据及所采用的方法，并指出半导体制造领域中值得进一步研究的一些问题和可能发展的方向．     

溅射工艺对晶片碎片的影响

介绍了半导体晶片制造设备溅射机和溅射工艺对晶片碎片的影响,给出了如何减少晶片应力以达到少碎片的目的.     

In Situ and Real-Time Monitoring of Plasma Process Chamber Component Qualities and Predictive Controlling of Wafer Yields

Plasma interactions with chamber components and wafers in semiconductor manufacturing processes have been monitored with a fault detection technique. Not only can this diagnostic technique monitor the wafer and process chamber components qualities, but it also has potential in saving tremendous amounts of manufacturing costs and improving equipment productivity. We have discovered that the abnormality in certain plasma processing parameters detected in the early stages of a manufacturing line can have a strong correlation with the product yield. Possible reasons for the observed correlations are explained     

Run-to-run overlay control of steppers in semiconductor manufacturing systems based on history data analysis and neural network modeling

This paper presents a new run-to-run control scheme to reduce overlay misalignment errors in steppers and demonstrates the feasibility of the scheme by real-time experimental tests. The overlay misalignment error mainly depends on two factors: one is the internal dynamics of photo processes and steppers and the other is the process history of lots, such as base equipment and reticles. Based on these observations, a new control scheme was designed to find the stepper inputs minimizing the misalignment errors based on history data analysis and neural network models. Moreover, we demonstrated that the proposed control scheme reduces the spec-out ratios as well as the number of engagements of the send-ahead wafer process, which thereby results in the increase of product yield in semiconductor manufacturing.     

电子表格模型在半导体晶圆制造产能规划中的应用

半导体晶圆厂的设备非常昂贵,对设备利用率的要求较高,设计一套简单实用的办法进行产能规划是十分必要的.本文提出了产能规划的三大模块,在前两个模块中将建立半导体晶圆制造产能规划的电子表格模型(Spreadsheet),在第三个模块中利用产能规划模型的数据结果进行分析,总结出一些改进方法.通过在某半导体晶圆厂的实际应用,该产能规划模型有效地解决了投料不均,设备负荷率波动过大等问题.     

单晶硅生产工艺中的关键技术

电子技术已经成为一个国家的技术发展状况的重要指针。在半导体芯片中,单晶硅材料占据了整个芯片体积的约99%。单晶硅的生产技术和产量体现了一个国家在半导体行业中的发展水平。通过对单晶硅原材料制造工艺的细致分析,把制程工艺中的关键控制参数分类为"静态"控制参数和"动态"控制参数,提出了运用科学实验,建立数学模型和编制控制程序的生产控制方法,以取得品质、成本的双重控制。