A dynamic synchronization method to realize soft defect localization applied on digital and mixed-mode analog ICs in failure analysis

Failure analysis on advanced logic and mixed-mode analog ICs more and more has to deal with so called ‘soft defects’. In this paper, a dynamic synchronization method is proposed to perform soft defect localization (SDL) technique by Optical Beam Induced Resistance Change (OBIRCH). It is a new and low-cost way to achieve SDL technique by OBIRCH equipment if there is no normal SDL equipment on hand. It extends the application of OBIRCH equipment to a more advanced failure analysis realm. The methodology and system configuration are presented. The experimental results show this dynamic synchronization method is accurate enough to locate a soft defect. Two real cases are studied on a digital IC and a mixed-mode analog IC respectively using this method.     

Effect of physical defect on shmoos in CMOS DSM technologies

Dynamic laser stimulation (DLS) techniques based on operating integrated circuits (ICs) become a standard failure analysis technique for soft defect localization. This type of defect is getting more and more common with advanced technology; therefore, DLS is becoming a key technique for defect localization. To perform this technique, the determination of a pass–fail border in shmoo plot is necessary. It is essential to know the impact of the defect on the shmoo plot shape with different defects. This paper presents shmoos plots simulation for common defects encountered in ICs failure analysis. Ability of DLS to detect defects according to their resistances and capacitances values are clearly established. In the second part of this paper, case studies which validate simulations results are presented.     

Spectral and dynamical study of III–V triple junction solar cells and the application to multiflash I–V measurement

This paper presents a method to predict the I–V characteristic of triple junction InGaP/GaAs/Ge solar cells when different illumination spectra are used, and it is based on the measurement of a set of commercial isotype cells together with numerical simulations. The study includes the utilization of continuous and pulsed light sources. Several spectra were considered for the continuous light sources, where different subcells limit the current of the tandem cell. For pulsed light sources, a dynamical analysis was carried out by simulating a triple junction cell through PSpice software. For the simulations, the subcell capacitances were estimated and introduced into an electrical model of the triple junction. When a fast pulse in the multiflash I–V measurement technique is used, dynamical effects associated with this kind of source were observed and accounted for by the simulations. It was established that the dynamical effects did not affect the I–V characteristics measured with this technique. Finally, the proposed method and analysis were successfully applied to the electrical characterization of the Aquarius/SAC‐D Argentine satellite solar array modules. Copyright © 2014 John Wiley & Sons, Ltd.     

Defect electrical conduction in SIMOX buried oxides

It is pointed out that the buried oxide (BOX) layers in SIMOX structures exhibit localized defect conduction superimposed on the background (bulk) conduction. Type I defects show a pre-breakdown quasi-linear I-V characteristic with 10^-7<I<10^-3 A in the voltage range of 0.01-10 V. Type II defects exhibit a superlinear I-V behavior above 5 V and breakdown, usually occurs at 10-50 V. A large number of samples prepared in various manners has been studied with automatic test equipment by which the number of Type I defects has been determined from several hundreds of capacitors on a given wafer. For annealed samples the calculated defect density values range from 0.01 to 10 defects/cm², while for un-annealed samples the range is 40-120 defects/cm². Type I defects are very probably Si pipes in the BOX which result from particulate contamination during implantation. Statistical analysis revealed that the sample preparation technique has improved significantly in 1992. The situation regarding the Type II defects is more complicated as these defects appear to be closely related to some fundamental aspects of bulk conduction of the BOX layer in which electron traps play an important role     

Facing the defect characterization and localization challenges of bridge defects on a submicronic technology (45 nm and below)

For very deep submicron technologies, 45 nm and less, bridge defects are getting more and more complex and critical. In order to find the exact root cause, accurate defect localization, precise understanding on the nature of the defect and its impact on the fine electrical behaviour of the device are mandatory. At these ultimate technologic nodes, failure analysis techniques show a real lack of efficiency on bridge defect localization while this precise location is one of the keys to find the defect root cause that allows correct implementation of corrective actions to improve yield and reliability.To face this challenge we have built a complete set of signatures related to advance Eldo simulations, performed measurement with ultimate failure analysis tools, fully characterized a microelectronic structure in advanced technology presenting a bridge defect and established a complete link between all these data and the failure location.     

Correlation between predicted cause of SRAM failures and in-line defect data

A correlation has been made between the bitmap data from an SRAM and the in-line defect data as measured on a KLA2122 and Tencor7700. The SRAM was a dedicated design for yield enhancement in a 0.35 μm technology. Extra design features were added to encourage the change of having defect on particular places and discourage it on safe designed places. From the failure signature of a memory cell (0 or 1) and its failure extent (single cell, double cell, bitline, wordline (WL), …) one can predict the process-related cause of the failure. A special test program has been written which translates the electrical data from the failing cells into its process defect.The failing bits from the SRAM have been transferred into a KLA results file and added as an extra inspection to the defect database. With a defect source analysis it was possible to find out if the electrical failing bits were seen as a defect in the line and at which steps. With this analysis it is possible to find out if the predicted cause of the process defects from the test program is confirmed by the performed in-line inspections. With an intensive inspection plan about half of the electrical defects were seen in the line. For a large amount of these defects their predicted cause are indeed matching with the inspected layer. Moreover, quite some unknown failures can be explained by the in-line inspections. This correlation work makes it possible to prioritize in tackling the most killing defect sources.     

Backside failure analysis case study: Implementation of innovative Local Backside Deprocessing technique

This paper describes a failure analysis case study where innovative Local Backside Physical characterization technique was performed on an automotive custom Mix-Mode device.The full analysis flow is presented, starting with backside sample preparation in order to perform a backside electrical localization of the defect. Then the multiple challenges of that approach were discussed. The continuous need of decreasing the analysis cycle time was addressed without affecting the success ratio of such analysis flow. The part mechanical degradation was avoided with a local removal of the Silicon. That highly localized technique granted a direct access to the fault site.The tools and process used for this case are fully described underlining the main advantages of this technique in comparison to the global backside deprocessing or to other characterization techniques.That successful development was achieved while determining the failure mechanism, in correlation with the failure mode of the qualification reject.     

Foundry workflow for dynamic-EFA-based yield ramp

The increasing demand for electrical failure analysis (EFA) in yield enhancement [1] has created new challenges for foundries and their clients. Dynamic EFA techniques, more in demand with the smaller technology nodes, have largely been the domain of the design-house failure analysis (FA) lab. In 2010 on 40 nm packaged parts, a new laser-based technology, laser voltage imaging (LVI) was applied to shift debug and drove physical failure analysis (PFA) success rate to >90%. This is still the case in 2011 on 28 nm ICs. The methodology was validated at the foundry on 32 nm wafers and again drove the PFA success rate to >90%. This paper offers a foundry-friendly methodology made possible by LVI and its fast track to the wafer level.     

Laser decapsulation of plastic packages for failure analysis: Process control and artefact investigations

Laser ablation is a recent pre-decapsulation technique, which is used for sample preparation in failure analysis. This process works with speed and accuracy. These are key parameters for getting successful observation and defect localization. This can be used to have a precise opening on the die. However, this technique can create thermal stresses to the device. In order to minimize this stress, we have investigated methods for controlling the thermal effect of the laser on the component. This paper presents the experimental setup and the study of an electrical artefact that influences the interpretation of our thermal data.     

Mechanism of breakdown voltage wavering in power MOSFET induced by silicon crystalline defect

This paper presents the impact of silicon crystalline defects generating mechanism of breakdown voltage degradation on low voltage vertical Power N-MOSFETs, functioning in avalanche mode. The physical defect determination is presented through a full failure analysis: it includes specific sample preparation, electrical characterization using EMMI techniques and physical characterizations using Scanning Electron Microscope, Transmission Electron Microscope and chemical delineation etches. Silicon crystal defects (edge dislocation and stacking fault) are found to be at the origin of the failure. Then, a discussion presents how the failure mechanism impacts the device structure and some possible root cause at the origin of the defect.     

28 nm低功耗工艺SRAM失效分析

在28 nm低功耗工艺平台开发过程中,对1.26 V测试条件下出现的SRAM双比特失效问题进行了电性能失效模式分析及物性平面和物性断面分析.指出失效比特右侧位线接触孔底部空洞为SRAM制程上的缺陷所导致.并通过元素成分分析确定接触孔底部钨(W)的缺失,接触孔底部外围粘结阻挡层的氮化钛(TiN)填充完整.结合SRAM写操作的原理从电阻分压的机理上解释了较高压下双比特失效,1.05 V常压下单比特不稳定失效,0.84 V低电压下失效比特却通过测试的原因.1.26 V电压下容易发生的双比特失效是一种很特殊的SRAM失效,其分析过程及结论在集成电路制造行业尤其是对先进工艺制程研发过程具有较好的参考价值.     

The device characteristics of missing LDD implantation via nanoprobing techniques for localized failure analysis

In the recent years, localization of subtle defects has required device electrical data. Nanoprobing systems based on scanning electron microscopy (SEM) or atomic force microscopy (AFM) have become a significant tool for device measurement in failure analysis (FA) Labs. Failure Analysts can use electrical characteristics to isolate failure location in the metal–oxide–semiconductor field-effect-transistor (MOSFET). The missing lightly doped drain (LDD) implant is an example of a critical failure mechanism for the MOSFET and cell in the SRAM which is localized using nanoprobing. In this article, device data analysis and theoretical deductions are discussed related to missing LDD doping. Device data is used to propose a full set of characteristic for missing LDD. The simulation from a mature tool is able to support the electrical characteristics. The capability and challenge of the following physical FA to reveal the defect are also discussed.     

New application of laser beam to failure analysis of LSI with multi-metal layers

A new technique for failure analysis of LSI with multi metal layers is described. There is a fabrication technique to form a big and optional window on upper layers using Nd-YAG laser without destroying any electrical function, and to approach the failure point through this window. The failure analysis procedure based on logical flow is presented. Fabrication technique is located in part of this procedure which consists of four steps. Two difficult reasons for approaching the failure point without fabrication technique are described. This difficulty results from line composition and line width. The fabrication procedure using Nd-YAG laser is reported. This procedure is to cover the chip surface with photo resist, and form a big and optional size window on upper layer with laser beam, and finally expose the purposed layer. Three failure analysis examples using this technique are introduced: unformed contact falure mode, Si-noduled failure mode, and isolation destroying failure mode.     

ESD laboratory simulations and signature analysis of a CMOS programmable logic product

It is well established in the semiconductor I/C industry that the proportion of customer field returns attributed to damage resulting from electrical over-stress (EOS) and electro-static discharge (ESD) can amount to 40% to 50% (Cook C, Daniel S. Characteristics and failure analysis of advanced CMOS submicron ESD protection structures. EOS/ESD symposium proceedings ?14, Dallas, TX, 1992. p. 147; Denson WK, Green TJ. A review of EOS/ESD field failures in military equipment. EOS/ESO symposium proceedings-10, 1988. p. 7. Straub RJ. Automotive Electronics IC Reliability. CICC Proceedings, 1990; Euzent BL, Maloney TJ, Donner II R. Reducing field failure rate within proven EOS/ESO design. EOS/ESO Symposium Proceedings ?13, Los Vegas, NV, 1991. p. 59). ESD events are the subset of EOS events caused by high voltages that are associated with electrostatic charge. Although additional hard and soft failures can occur in the factory, these are normally screened by effective test programs. It is therefore necessary to determine the probable cause of failure before cost effective corrective action can be initiated.Distinguishing between EOS and ESD failures and differentiating the subtle differences between damage due to the several distinct ESD models continues to challenge failure analysis capabilities as dimensions shrink and critical defect sizes are reduced. Many of the damage sites are not visible with optical microscopy. De-processing together with very high magnification examination using the scanning electron microscope (SEM) is most often necessary. However, the use of test model simulators to replicate the ESD events can most often replicate a failure signature, i.e. a unique die location and morphology associated with the specific model (Morgan IH. ESO Failure Analysis Signatures. Proceedings of the 3rd ESO Forum, Grain, Germany, 1993. p. 275).This paper summarizes the evaluation performed on a standard programmable logic complimentary metal-oxide silican (CMOS) product to ascertain the ESD immunity. The study entailed ESD simulation using a variety of ESD models, conducting detailed physical failure analysis and then comparing the results with documented analyses performed on customer field returns and factory failures. As a result of the differences in current stress magnitude and over-stress time domain, the location, type and severity of damage at the failure site is known to show considerable variation (Morgan IH. A Handbook of ESO models. AMD Internal Publication, 1992 (available from AMD literature department upon request)). The purpose of the study was to develop a catalogue of failure signatures, and to determine to what extent this catalogue could be used to relate a signature to electrical failure for a particular die and pin function.     

Evaluation of subcell power conversion efficiencies of radiation‐damaged triple‐junction solar cells using photoluminescence decays

We characterize the radiation‐induced damage of InGaP/GaAs/Ge solar cells for various proton irradiation energies and fluences using conventional current‐voltage (I‐V) measurements, external quantum efficiency, and a noncontact time‐resolved photoluminescence (PL) technique. From the I‐V curves, we obtain the conversion efficiency of the entire device. The external quantum efficiency showed that the short‐circuit current is only determined by the top InGaP subcell. To obtain accurate information about the point of maximum power, a new PL technique is introduced. The PL time decays of the InGaP and GaAs subcells are measured to obtain the characteristic decay time constants of carrier separation and recombination. We empirically verify that the time‐resolved PL method can be used to predict the electrical conversion efficiency of the subcells. We find that the limiting subcell at the point of maximum power is different from that for short‐circuit current. Radiation damage in unexpected regions of the device is revealed using this optical method.     

PLL soft functional failure analysis in advanced logic product using fault based analogue simulation and soft defect localization

Soft defect localization (SDL) is an analysis technique where changes in the pass/fail condition of a test are monitored while a laser is scanned across the device under test (DUT). This technique has proven its usefulness for quickly locating defects that are temperature, frequency, and/or voltage dependant, for example, scan logic soft fault. However, due to high sensibility at analogue circuits SDL meets great challenges. This work gives a new flow to analyze soft functional failure in advanced logic products using fault based analogue simulation and SDL. The paper will present one case study illustrating the application of analogue simulation based soft defect localization flow as an effective means to achieve fault isolation.     

Light emission as an analysis tool for GaAs ICs

As GaAs IC integration continues, device characterization and failure analysis get more difficult to perform. Standard visual and electrical inspections are becoming less adequate to evaluate devices and determine root cause of failures. A relatively new technique, used for several years on silicon devices, is light emission microscopy. The properties of light emission on silicon devices have been known for several decades. The light-producing properties of GaAs, a direct bandgap material, make it a natural for light emission study. This overview is intended to discuss the methodology and results of GaAs MESFET light emission.     

Static fault localization of subtle metallization defects using near infrared photon emission microscopy

In this paper, two electroluminescence phenomena, which enabled the static electrical fault localization of subtle back-end-of-line metallization defects using near-infrared photon emission microscopy in the logic circuitry and the memory array, are described. In the logic circuitry, through the study of the defect-induced hot carrier emissions from the combinational logic gates, distinctive differences in emission characteristic between open and short defects are identified. Using this defect induced emission characterization approach, together with layout trace and analysis, the type of defect can be predicted. The defect physical location, which yielded no detectable hotspot signal, can also be narrowed down along the long failure net. This allows for the selection of the most appropriate physical failure analysis approach for defect viewing and thus achieving significant reduction in failure analysis cycle time. In the memory array, the weak emission from partially turned-on pass gate transistor is leveraged to localize marginal opens and shorts on the wordline node of the pass-gate transistor. These approaches are applied with great success in the foundry environment to localize yield limiting defects that resulted in SCAN and memory build-in self-test failure, without memory bitmap, diagnostic support or measurable I_DD leakage, on advanced technology nodes devices. A discussion on the factors that influence the success rate of this approach is also provided.     

The effect of the number of defect mechanisms on fault clusteringand its detection using yield model parameters

The superposition principle is used to analyze faults of different mechanisms. The sum of the individual cluster coefficients of each mechanism is approximately equal to the cluster coefficient for all mechanisms combined. This technique is used on defect density test structures as well as bit failures from SRAM chips. A regression analysis of empirical data is used to demonstrate this concept for the defect density test chips. The actual and, the model fault densities are compared and show excellent agreement. As a comparative analysis, a quadrant technique was used to compile a frequency distribution of electrical faults and a nonlinear least-squares technique is applied to the distribution to estimate the parameters in the gamma and Poisson distributions. These results are compared to the cluster parameters from the summation technique and the technique using moment estimates. All three estimates are in very good agreement. The application of this model to actual chip yields is shown not only to be more accurate but also to contain information about the relative number of fault generating mechanisms for the mask level of interest in the process     

Defect Characterization in Ge/(001)Si Epitaxial Films Grown by Reduced-Pressure Chemical Vapor Deposition

We studied the microstructural characteristics and electrical properties of epitaxial Ge films grown on Si(001) substrates by x-ray diffraction, atomic force microscopy, and transmission electron microscopy. The films were grown using a two-step technique by reduced-pressure chemical vapor deposition, where the first step promotes two-dimensional growth at a lower substrate temperature. We observed a decrease in defect density with increasing film thickness. Ge films with thickness of 3.5 μm exhibited threading dislocation densities of 5 × 10⁶ cm^?2, which yielded devices with dark current density of 5 mA cm^?2 (1 V reverse bias). We also noted the presence of stacking faults in the form of lines in the films and establish that this is an important defect for Ge films grown by this deposition technique.