Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs

Scaling of the standard single-gate bulk MOSFETs faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the leakage current and enhanced sensitivity to process variations. Multi-gate MOSFET technologies mitigate these limitations by providing a stronger control over a thin silicon body with multiple electrically coupled gates. Double-gate FinFET is the most attractive choice among the multi-gate transistor architectures because of the self-alignment of the two gates and the similarity of the fabrication steps to the existing standard CMOS technology. New latches and flip-flops based on independent-gate FinFETs are proposed in this paper to simultaneously reduce the power consumption and the circuit area. With the proposed independently biased double-gate FinFET sequential circuits, the active power consumption, the clock power, the leakage power, and the circuit area are reduced by up to 47%, 32%, 42%, and 20%, respectively, while maintaining similar speed and data stability as compared to the standard sequential circuits with tied-gate FinFETs in a 32-nm FinFET technology.     

Cointegration of High-Performance Tied-Gate Three-Terminal FinFETs and Variable Threshold-Voltage Independent-Gate Four-Terminal FinFETs With Asymmetric Gate-Oxide Thicknesses

Cointegration of titanium nitride (TiN)-gate high-performance tied-gate three-terminal FinFETs with symmetric gate-oxide thicknesses (t_ox1=t_ox2=1.7 nm) and variable threshold-voltage V_th independent-gate four-terminal (4T) FinFETs with asymmetric gate-oxide thicknesses (t_ox1=1.7 nm for the driving-gate-oxide, and t_ox2=3.4 or 7.0 nm for the control-gate-oxide) has been successfully developed using conventional reactive sputtering, two-step Si-fin and gate-oxide formation, and resist etch-back processes. A significantly improved subthreshold slope and an extremely low OFF-state current I_off are experimentally confirmed in the asymmetric gate-oxide thickness 4T FinFETs by increasing the control-gate-oxide thickness to twice or more the driving-gate-oxide thickness. The developed techniques are attractive for high-performance and low-power FinFET very large-scale integration circuits     

Electron Mobility and Short-Channel Device Characteristics of SOI FinFETs With Uniaxially Strained (110) Channels

We have successfully fabricated uniaxially strained SOI (SSOI) FinFETs with high electron mobility and low parasitic resistance. The high electron mobility enhancement on the (110) fin sidewall surfaces was obtained by utilizing effective subband engineering through uniaxial tensile strain along $ langlehbox{110}rangle$, while the substantial reduction of the parasitic resistance was achieved by selective Si epitaxy on the source and drain regions. It was experimentally found that the electron mobility on the (110) sidewall surfaces was significantly enhanced (2.6$times$ ) and even surpassed the (100) universal mobility (1.2$times$ ). This high mobility enhancement is mainly attributed to the electron repopulation from fourfold valleys having a heavier mass along $langlehbox{110}rangle$ to twofold valleys having a lighter one. In addition, the effective mass reduction of the twofold valleys due to conduction band warping and/or the suppressed surface roughness scattering can also be responsible for the mobility enhancement. Thanks to these high electron mobility enhancement and low parasitic resistance large performance enhancement of 35% was realized in uniaxially SSOI FinFETs with a gate length of 50 nm. This enhancement was evaluated to be as high as $sim$80% $(= hbox{35}%/hbox{45}%)$ of the intrinsic strain-induced enhancement of the short-channel device performance (45%) at the same strain level (0.8%, $sim$1.5 GPa) and gate length.      

注F短沟MOSFET的沟道热载流子效应

通过对短沟 NMOSFET的沟道热载流子效应研究 ,发现在短沟 NMOSFET栅介质中引入 F离子能明显抑制因沟道热载流子注入引起的阈电压正向漂移和跨导下降以及输出特性曲线的下移 .分析讨论了 F抑制沟道热载流子损伤的机理 . Si— F键释放了 Si/Si O2 界面应力 ,并部分替换了 Si— H弱键是抑制热载流子损伤的主要原因 .     

注F短沟MOSFET的沟道热载流子效应

通过对短沟NMOSFET的沟道热载流子效应研究,发现在短沟NMOSFET栅介质中引入F离子能明显抑制因沟道热载流子注入引起的阈电压正向漂移和跨导下降以及输出特性曲线的下移.分析讨论了F抑制沟道热载流子损伤的机理.Si—F键释放了Si/SiO2界面应力,并部分替换了Si—H弱键是抑制热载流子损伤的主要原因.     

Modeling of Short-Channel Effects in Organic Thin-Film Transistors

We propose a model for short-channel organic thin-film transistors, which accounts for Poole-Frenkel field-dependent mobility and space-charge-limited current effects. The model is developed for devices operating in the linear regime, as well as in depletion and saturation regimes. Super linear output curves for low drain voltages, as well as nonsaturating currents, can be adequately described. Experimental results for short-channel P3HT devices have been fitted, showing good agreement with the proposed model.     

短沟道SOI MOSFET总剂量辐照效应模型

报道了一个含总剂量辐照效应的 SOI MOSFET统一模型 .该模型能自动计入体耗尽条件 ,不需要分类考虑不同膜厚时的情况 .模型计算结果与实验吻合较好 .该模型物理意义明确 ,参数提取方便 ,适合于抗辐照 SOI器件与电路的模拟 .     

短沟道SOI MOSFET总剂量辐照效应模型

报道了一个含总剂量辐照效应的SOI MOSFET统一模型.该模型能自动计入体耗尽条件,不需要分类考虑不同膜厚时的情况.模型计算结果与实验吻合较好.该模型物理意义明确,参数提取方便,适合于抗辐照SOI器件与电路的模拟.     

FinFET器件总剂量效应研究进展

全面综述鳍式场效应晶体管(FinFET)的总剂量效应,包括辐照期间外加偏置、器件的工艺参数、提高器件驱动能力的特殊工艺、源/漏掺杂类型以及不同栅介质材料和新沟道材料与FinFET总剂量效应的关系。对于小尺寸器件,绝缘体上硅(SOI)FinFET比体硅FinFET具有更强的抗总剂量能力,更适合于高性能抗辐照的集成电路设计。此外,一些新的栅介质材料和一些新的沟道材料的引入,如HfO₂和Ge,可以进一步提高FinFET器件的抗总剂量能力。     

Semianalytical Modeling of Short-Channel Effects in Lightly Doped Silicon Trigate MOSFETs

A simple analytical expression of the 3-D potential distribution along the channel of lightly doped silicon trigate MOSFETs in weak inversion is derived, based on a perimeter-weighted approach of symmetric and asymmetric double-gate MOSFETs. The analytical solution is compared with the numerical solution of the 3-D Poisson's equation in the cases where the ratios of channel length/silicon thickness and channel length/channel width are ges 2. Good agreement is achieved at different positions within the channel. The perimeter-weighted approach fails at the corner regions of the silicon body; however, by using corner rounding and undoped channel to avoid corner effects in simulations, the agreement between model and simulation results is improved. By using the extra potential induced in the silicon film due to short-channel effects, the subthreshold drain current is determined in a semianalytical way, from which the subthreshold slope, the drain-induced barrier lowering, and the threshold voltage are extracted.     

Hot Carrier Effects in Wireless Communication Systems Built on Short-Channel MOSFETs

Phase noise is a critical factor that degrades the synchronization performance of a wireless communication receiver. Hot-carriers (HCs), found in the CMOS synchronization devices, are high-energy charge-carriers that can degrade the MOSFETs performance by damaging the internal device structure and lead to the phase noise increase therein. Such incremental phase noise can be related to the essential parameter, namely the MOSFET threshold voltage due to the HC effect, which is particularly evident in the short-channel MOSFET devices. In this letter, we analyze the impact of the phase noise arising from the HC effect on the wireless systems in terms of the bit-error-rate (BER) and the signal-to-interference-plus-noise ratio (SINR).     

SiGe-Channel Confinement Effects for Short-Channel PFETs With Nonbandedge Gate Workfunctions

Thin SiGe-channel confinement is found to provide significant control of the short channel effects typically associated with nonbandedge gate electrodes, in an analogous manner to ultrathin-body approaches. Gate workfunction requirements for thin-SiGe-channel p-type field effect transistors are therefore relaxed substantially more than what is expected from a simple observation of the difference between gate and channel workfunctions. In particular, thin-SiGe channels are shown to enable cost-effective high-performance bulk CMOS technologies with a single gate workfunction near the conduction bandedge. Buried channel, gate workfunction, metal gate, SiGe-channel confinement effects, SiGe-channel MOSFET, silicon germanium, ultrathin-body (UTB).     

Threshold-Voltage Modeling of Body-Tied FinFETs (Bulk FinFETs)

The threshold voltages V_th of the body-tied double/triple-gate MOSFETs (bulk FinFETs) implemented on bulk silicon (Si) wafers were modeled systematically and compared with data obtained from 3-D device simulation. The threshold-voltage behaviors of the bulk FinFETs were modeled, for the first time, based on charge sharing. For the simplified V_th model, we considered not only short-channel effect (SCE) and narrow-width effect but also 3-D charge sharing at the corner. Only one fitting parameter is introduced to reflect the SCE in the fin body. The model predicted the V_th behavior with fin body thickness, body doping concentration, gate height, gate length, and corner shape of the fin body well. Our compact model makes an accurate prediction of V_th and shows good agreement with 3-D simulation data     

Semi-Analytical Modeling of Short-Channel Effects in Si and Ge Symmetrical Double-Gate MOSFETs

A simple analytical expression of the 2-D potential distribution along the channel of silicon symmetrical double-gate (DG) MOSFETs in weak inversion is derived. The analytical solution of the potential distribution is compared with the numerical solution of the 2-D Poisson's equation in terms of the channel length L, the silicon thickness t _Si, and the gate oxide thickness t _OX. The obtained results show that the analytical solution describes, with good accuracy, the potential distribution along the channel at different positions from the gate interfaces for well-designed devices when the ratio of L/t _Si is ges 2-3. Based on the 2-D extra potential induced in the silicon film due to short-channel effects (SCEs), a semi-analytical expression for the subthreshold drain current of short-channel devices is derived. From the obtained subthreshold characteristics, the extracted device parameters of the subthreshold slope, drain-induced barrier lowering, and threshold voltage are discussed. Application of the proposed model to devices with silicon replaced by germanium demonstrates that the germanium DG MOSFETs are more prone to SCEs.     

Experimental Evaluation of Circuit-Based Modeling of the NBTI Effects in Double-Gate FinFETs

In this work, an example of practical implementation of the auxiliary sub-circuit (ASC) for modeling of the NBTI effects in DG FinFETs is described. A good agreement between the simulated and measured electrical characteristics of p-type DG FinFETs fabricated in SOI technology has been obtained using the industry-standard BSIM-CMG model with ASC. The oxide and interface trap densities are extracted in Spice simulations by tuning the ASC trapped charge parameters to fit the NBTI experimental data. The increase of oxide and interface trapped charge in p-type DG FinFET device is found to follow the logarithmic dependence with NBTI stress time.     

High-performance p-type independent-gate FinFETs

We present, to our knowledge, the first successful integration of two independent gates on a p-type FinFET. These results also represent a significant performance improvement over previously reported Independent-Gate FinFET results. The devices have gate lengths ranging from 0.5 to 5 /spl mu/m, and designed fin thicknesses ranging from 25 to 75 nm. Electrical results show near-ideal subthreshold slopes in double-gate mode (both gates modulated simultaneously). Independent-Gate operation is also examined by modulating saturated drain current with both front and back-gate voltages independently. The results are compiled to analyze performance trends versus fin thickness and gate length.     

Experimental Evaluation of Effects of Channel Doping on Characteristics of FinFETs

We investigated channel doping in fin-type double-gate (DG) MOSFETs. We demonstrated through experiments that the threshold voltage was more sensitive to the dopants in the accumulation mode than in the inversion mode. We also found that significant deviation in the threshold voltage from the expected value arose in ultrathin fin-type DG MOSFETs. We attributed this phenomenon to the unexpected dopant loss from the ultrathin channels due to segregation. This finding means that careful doping adjustments must be made in ultrathin-channel devices.     

Low-frequency noise characteristics in p-channel FinFETs

We report on the characterization of low-frequency noise in fully depleted (FD) double-gate p-channel FinFETs. While the average noise follows a 1/f dependence, considerable device-to-device variations in noise level are observed due to the statistical fluctuation of the number of oxide traps involved. We found that the low-frequency noise in poly-Si-gated p-FinFETs is mainly governed by the carrier number fluctuation with correlated mobility fluctuation. The low-frequency noise characteristics indicate that the FinFET device can be a promising candidate for analog and RF applications.     

A Novel Blocking Technology for Improving the Short-Channel Effects in Polycrystalline Silicon TFT Devices

An original blocking technology is proposed for improving the short-channel characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs). In particular, two types of modified devices called poly-Si TFT with block oxide and poly-Si on partial insulator (POPI)-TFT are designed for the first time in this field to enhance device performance. The proposed TFT structures can significantly reduce short-channel effects when compared with a thick source/drain (S/D) poly-Si TFT (i.e., the fully depleted TFT). In addition, an ultrathin (UT) S/D structure (UT-TFT) is designed to verify that the block oxide TFT devices do achieve improved performance without needing the thin active layers and ultrashallow junction depth. Also, the POPI-TFT is found to reduce the thermal instability through its natural body-tied scheme.