用改进的查表法实现高速模运算电路

阐述了一种改进的查表法来实现高速模运算电路，可以比普通的查表法节省大量的资源，同时又比阵列除法器快速。给出一个使用改进查表法实现除数为常数的快速模运算电路的设计实例，并且给出详细的数学推导过程，最后讨论改进查表法的适用范围和扩展使用，该设计已经通过FPGA验证。     

改进周期图法在倒谱法中的应用研究

文章在传统倒谱法的基础上,提出了一种基于改进周期图法的倒谱法,并分析了基于三角窗函数的改进倒谱法,通过仿真结果与性能分析表明,基于改进周期图法的倒谱法比传统倒谱法的谱线更平滑,且伪峰值相对较少,能大大减小功率谱的估计误差,在一定程度上提高了倒谱法码周期估计的性能。     

压缩改进节点法及其应用

在改进节点法的基础上,提出了针对含有受控源的线性有源网络分析的压缩改进节点法,建立了对应的压缩改进节点电压方程。该方法不但克服了改进节点法对于含有VCVS、CCVS和无伴电压源的电路处理难度较大,甚至有时无法建立网络的节点电压方程的不足,而且解决了改进节点法中由于方程数目增加以及主对角元素出现零元素时所引起的求解困难。该方法概念清晰,列写过程简单,对于小型网络的分析具有一定的实用价值。     

激光半主动制导系统的极限作用距离测量模型

激光半主动制导系统通常是光电对抗的主要对抗对象,因此,其真实的作用距离就成为了光电对抗中最为关心的指标。定义了激光半主动制导系统的极限作用距离,考虑大气湍流对激光传输的影响,推导出了激光半主动制导系统照射方程的一般形式,并参考激光测距系统测距性能的测试方法,通过改进消光比法和最大测程法的转换,得到了激光半主动制导系统的极限作用距离测量模型。最后,分别进行了改进消光比试验和最大测程试验,验证了极限作用距离测量模型。实验结果表明:依据模型只需在一定天候条件下进行改进的消光比试验即可得到任意天候条件下激光半主动制导系统的极限作用距离,且相对误差较小,不超过1%。     

改进滤波法在热管换热系统稳态检测中的应用

热管换热系统在进行数据调和和稳态优化之前，必须保证系统处于稳定状态，而检测系统是否处于稳定状态的方法多种多样。改进滤波法是一种较为普遍的稳态检验方法，可以对包含过失误差的系统数据进行有效检测，从而判断系统是否处于稳态。热管换热系统由于电网电压的波动以及外界振动，易给传感器测温数据引入过失误差，运用改进滤波法可有效检测数据含过失误差的情况。数值试验结果表明，传统的滤波法用于检测数据含过失误差时稳态检测失效，而改进滤波法能有效检测出系统处于何种状态。     

一种IGrubbs-LWLR的区域高程异常拟合方法

针对测量数据中粗差干扰及高程异常拟合方法选择较为困难的问题，结合格拉布斯(Grubbs)法判别粗差的原理，提出一种改进格拉布斯(Improved Grubbs, IGrubbs)结合局部加权线性回归(Local Weighted Linear Regression, LWLR)的拟合模型构建法。在原Grubbs法则的基础上，引入自适应迭代，在训练数据中，对粗差进行识别，并设定粗差剔除完成的指标参数，从而降低原方法中发生误判或漏判的概率，并利用局部加权线性回归法通过预处理后的训练样本数据来建立区域高程异常拟合模型。实验结果表明，相较于传统Grubbs法则，改进后的Grubbs法对于高程异常数据中的粗差剔除更为快速有效，且利用局部加权线性回归法所构建的区域高程异常拟合模型的预测精度及稳定性也得到一定程度的提高，对今后工程中的测高工作具备一定的参考意义。     

基于改进的小波-矩阵法实现雷电干扰抑制

高频地波雷达探测飞行目标时,由于所处高频段电磁环境复杂,以冲击干扰为主要形式的雷电干扰会严重影响雷达探测性能。现有的小波-矩阵联合抑制法与传统方法相比,具有定位精度高、算法复杂度低的优点,但是却具有适用范围单一的局限性。以联合法的适用条件为依据将雷电干扰分类,研究不同类型雷电干扰的最佳抑制方法,并提出了改进的小波-矩阵联合法抑制雷电干扰方案。试验仿真表明,此改进方案能很好地抑制多种类型的雷电干扰,最大程度地降低了多普勒域噪声基底,有效地提高了高频雷达抗雷电干扰性能。     

基于Matlab的p-q法与ip-ip法仿真分析

针对p-q法和ip-iq法的谐波电流检测效果的比较,由于两种检测方法都是首先检测出原电流基波分量,再与原电流做差得到原电流谐波分量,因此可以通过计算检测出的基波电流中的谐波含量或畸变率来比较两种方法的检测性能.在接有非线性负载的系统中,通过控制电压源的电压波形,在(0.8-0.9)s时间段内产生标准正弦电压,在(0.9-1.0)s时间段内产生的畸变电压,利用p-q法和ip-ip法分别对同-检测点进行谐波电流检测.通过Matlab软件仿真试验,在(0.8-0.9)s时间段内利用p-q法和ip-ip法测得的基波电流的畸变率分别为1.72％和2.04％,在(0.9-1.0)s时间段内利用p-q法和ip-iq法测得的基波电流的畸变率分别为32.73％和4.39％.从而得出结论:在检测点处电压无畸变时,两种方法的检测性能都比较好,基波电流畸变率低,误差小;当电压发生畸变时,p-q法检测性能变差,基波电流畸变率变高,而ip-ip法检测性能无明显变化,适用范围更广.     

一种改进的CFICA盲分离算法的研究

复信号快速盲分离算法(CFICA)是一种快速有效的盲信号分离方法,但它常因敏感于分离矩阵的初始值而得到较差的分离效果,首先提出一种与牛顿下降法相结合的改进CFICA,并在高斯白噪声信道中对三路复值信号进行仿真实验,结果表明,改进的算法在分离质量和效率上较原算法有明显提高.     

基于改进ADC法的侦察无人机作战效能评估

针对侦察无人机系统作战效能评估问题,提出一种改进ADC评估模型。基于侦察无人机系统的作战任务及作战过程,构建出侦察无人机作战效能指标体系;在传统ADC法的基础上综合考虑作战人员保障因素和战场环境因素,结合层次分析法和模糊综合评判法对侦察无人机系统的作战效能进行评估。最后通过算例验证了该模型的可行性和有效性,评估结果显示,改进后的ADC法使得侦察无人机作战效能评估更加贴近实战。     

一种新颖全差分光电集成接收机的标准CMOS实现

提出一种新颖的全差分光电集成接收机,它包含了全差分光电探测器和相应的差分接收电路,其中全差分光电探测器的作用是实现入射光信号到全差分光生电流信号的转换.采用特许3.3 V、0.35μm标准CMOS工艺,实现了一种相应的宽带、高灵敏度全差分光电集成接收机.测试结果表明:对于850 nm的入射光,集成全差分光电探测器的差分跨阻前置放大器(TIA)的工作速率可达到500 Mbit/s,而整个光接收机的带宽则达到了1.098 5 GHz;在10-12的误码率条件下,灵敏度可达到-12.3 dBm.     

New Fully‐Differential CMOS Second‐Generation Current Conveyer

This paper presents a new CMOS fully‐differential second‐generation current conveyor (FDCCII). The proposed FDCCII is based on a fully‐differential difference transconductor as an input stage and two class AB output stages. Besides the proposed FDCCII circuit operating at a supply voltage of ± 1.5 V, it has a total standby current of 380 µA. The applications of the FDCCII to realize a variable gain amplifier, fully‐differential integrator, and fully‐differential second‐order bandpass filter are given. The proposed FDCII and its applications are simulated using CMOS 0.35 µm technology.     

一种新的套筒式全差分跨导放大器设计

A novel fully differential telescopic operational transconductance amplifier （OTA） is proposed. An additional PMOS differential pair is introduced to improve the unit-gain bandwidth of the telescopic amplifier. At the same time, the slew rate is enhanced by the auxiliary slew rate boost circuits. The proposed OTA is designed in a 0.18 μm CMOS process. Simulation results show that there is a 49% improvement in the unit-gain bandwidth compared to that of a conventional OTA; moreover, the DC gain and the slew rate are also enhanced.     

A novel structure of the fully differential CMOS amplifier with symmetric active load

In this article, we propose a novel general structure of a linear symmetric fully differential voltage amplifier with a symmetric output. It is applicable to all sets of complementary component pairs such as BJT, JFET and MOSFET. We demonstrate the superiority of the proposed circuit in comparison with the state-of-the-art solutions. The characteristics are illustrated in both frequency and time domains, and a comparison is given between the proposed amplifier and the traditional differential amplifier with a current mirror as an active load for the same set of complementary components in CMOS equally sized W/L = 150/3 technology. The static voltage transfer characteristic of the proposed amplifier has an extremely small linearity error. The deviation from the linear characteristics is less than 0.018 mV for the amplitude of the output differential voltage of 1 Vpp. The common-mode gain by symmetric output is negligible because the proposed structure is fully symmetric. The simulation results demonstrate the efficiency of the proposed amplifier.     

Second generation fully differential current conveyor based analog circuits

In this paper, we present a new voltage-mode biquad filter that uses a six-terminal CMOS fully differential current conveyor(FDCCII). The FDCCII with only 23 transistors in its structure and operating at ± 1.5 V, is based on a class AB fully differential buffer. The proposed filter has the facility to tune gain, ωo and Q. A circuit division circuit(CDC) is employed to digitally control the FDCCII block. This digitally controlled FDCCII is used to realize a new reconfigurable fully-differential integrator and differentiator. We performed SPICE simulations to determine the performance of all circuits using CMOS 0.25 μm technology.     

Fully Differential CMOS Current Feedback Operational Amplifier

This paper presents a new CMOS fully differential current feedback operational amplifier (FDCFOA). The proposed CMOS realization of the FDCFOA is based on a novel class AB fully differential buffer circuit. Besides the proposed FDCFOA circuit is operating at supply voltages of ±1.5 V, it has a total standby current of 400 A. The applications of the FDCFOA to realize variable gain amplifier, fully differential integrator, and fourth order fully differential maximally flat low pass filter are given. The fourth order filter provides 8 dB gain and a bandwidth of 4.3 MHz to accommodate the wideband CDMA standard. The proposed FDCFOA and its applications are simulated using CMOS 0.35 m technology.Soliman A. Mahmoud was born in Cairo, Egypt, in 1971. He received the B.Sc. degree with honors, the M.Sc. degree and the Ph.D. degree from the Electronics and Communications Department, Cairo University—Egypt in 1994, 1996 and 1999 respectively. He is currently an Assistant Professor at the Electrical Engineering Department, Cairo University, Fayoum-Campus. His research interests include low voltage analog CMOS circuit design, filtering and applications suitable for VLSI.Inas Awad was born in Cairo, Egypt, in 1971. She received the Bachelor, the M.Sc. and the Ph.D. degrees in Electronics and Communications from Cairo University in 1994, 1997 and 2000, respectively. In 1995, she joined the department of Electronics and Communications, Cairo University, Fayoum-Campus as a teaching assistant and now she is an Assistant Professor at the same department. Her primary research interest is in analog circuits with particular emphasis on current-mode approach and low-voltage low-power CMOS designs.     

电流激励神经信号再生电路

介绍了一种电流激励神经信号再生电路,该电路由探测电路和激励电路组成。探测电路由全差分运算放大器和仪表放大器组成。全差分运算放大器从神经元上端探测并放大神经信号,仪表放大器对信号进一步放大。最后激励级的跨导放大器将电压线性的转化为电流。电路采用CSMC0.5μmCMOS工艺设计,芯片版图尺寸为0.93mm×0.60mm。芯片的仿真结果为：在±2.5V供电电压下,功耗为8.1mW,输出电流最高可达0.357mA,输出电阻为152kΩ,总谐波失真小于1.9%。     

全差分群时延可精确调节的四阶Bessel滤波器实现

采用全差分运算放大器、无源电阻以及用作可变电阻的MOS管设计实现了全差分R-MOSFET-C四阶Bessel有源低通滤波器,在所提出的电路中通过调节工作在线性区的MOS管有源电阻的阻值以抵消集成电路制造工艺过程中电阻阻值的一致性偏差,达到Bessel滤波器的群时延值得到精确设计的目的.该滤波器中所采用的全差分运算放大器不仅具备有电压共模负反馈,而且还具有电流共模负反馈,极有利于电路静态工作点的稳定.通过无源双端RLC原型低通滤波器导出的0.75μs群时延四阶Bessel滤波器,采用台湾联电(UMC)2层多晶硅、2层金属(2P2M)、5.0V电源电压、0.5μm CMOS工艺制造,在输入信号为100kHz、2.5Vpp时,其谐波失真(THD)值低于-65dB.     

高输出阻抗多功能电流模式双二阶滤波器

提出了一种基于多输出端差动差分电流传送器的多功能电流模式滤波器电路结构。该电路用三个多输出端差动差分电流传送器，五个或四个接地电阻和两个接地电容，同时实现了反相和，或同相带通和低通或带通和高通滤波响应特性。分析并模拟了所提出的滤波器的传递特性，PSPICE仿真结果表明，所提出的电路方案正确有效。电路具有灵敏度低，输出阻抗高，滤波器固有频率ωo和品质因数Q相互独立可调，多功能的优点，适于实现全集成连续时间滤波器。     

A new high-performance CMOS fully differential second-generation current conveyor with application example of biquad filter realisation

In this article, a new complementary metal oxide semiconductor (CMOS) high-performance fully differential second-generation current conveyor (FDCCII) implementation is proposed. The presented FDCCII provides high-output impedance at terminals Z+ and Z?, good linearity and excellent output–input current gain accuracy. Also, the proposed FDCCII circuit operates at a supply voltage of ±1.3 V. The applications of the FDCCII to realise voltage-mode multifunction filters are given. Simulations are performed using TSMC CMOS 0.35-μm technology to verify theoretical results.