利用逆向判定性缩短EFSM的测试序列的长度

在一个以扩展的有限状态机（ＥＦＳＭ）为模型描述的协议测试系统中,测试序列的可执行性是一个重要的问题。同时,还要考虑到测试序列的优化问题。文中以ＥＦＳＭ为协议的描述模型,引入了逆向判定性的概念,并利用这一概念对转换可执行性分析（ＴＥＡ）方法进行了改进,缩短了生成的测试序列的长度,并且减小了所需的ＴＥＡ树扩展空间。     

EFSM的等价转换和通信协议一致性测试

绝大多数通信协议是以ＥＦＳＭ（扩展的有限状态机）来描述的。本文首先给出ＥＦＳＭ的形式化定义，然后提出ＥＦＳＭ的一种等价转换算法及其证明。通过协议转换，可以使生成一致性测试集的方法得到简化，并且生成的测试实例具备一定的诊断数据流错误的能力     

TCS:TCP协议一致性测试系统的设计和实现

本文阐述了一个对ＴＣＰ协议进行一致性测试的测试系统的设计和实现。着重介绍了该系统的测试方法和系统结构，并分析了基于ＥＦＳＭ模型的一致性测试集的生成技术。     

利用半可控接口进行通信协议一致性测试

介绍了一种基于半可控接口的图转换算法，并应用于某通信产品的H．245协议一致性测试中，不仅增加了可测试转换的数目，还使得变换后的EFSM可以直接应用传统的测试序列生成方法产生最优的测试序列，错误覆盖率和测试效率都得到了显著的提高。     

IPv6邻居发现协议的一致性测试序列生成

自1998年互联网工程任务组(IETF)提出下一代互联网标准规范以来,IPv6已经历了十多年的发展。现今已有越来越多的IPv6产品被投入到了开发与应用中。而如何提高不同产品间的互通性和可靠性则成为了一个关键问题。进行协议一致性测试是提高IPv6实现可靠性的一种有效方式。本文就重点针对IPv6邻居发现协议进行了一致性测试分析。本文首先简要分析了IPv6邻居发现协议的主要功能及实现原理,并据此抽象出其有限状态机（FSM）模型。进而结合一种现有基于有限状态机(FSM)的一致性测试序列改进算法生成了该协议的抽象测试序列。本文在最后对得到的测试序列进行了有效性和可靠性分析,分析表明,使用该算法得到的测试序列不仅在序列长度上较传统UIO序列法有了明显的缩短,同时对测试过程中可能发生的输出错误及末状态转换错误也具备良好的检测能力。本文获得的抽象测试序列可对相关IPv6协议开发者提供有效参考。      

光纤偏振模色散常用测试方法的研究

偏振模色散（ＰＭＤ）近年来已成为光纤光缆的一个重要特性参数。本文着眼于ＰＭＤ测试的原理和方法，首先同注重ＰＭＤ的统计特性是进行ＰＭＤ测试的一个重要原则；继而按频域和时域测试ＰＭＤ的方法进行分类，并分析了目前常用的几种ＰＤＭ测试方法，例如ＪＭＥ、ＷＳＥＣ、ＩＦ和ＷＳＦＦＴ法，了它们和自的优缺点，指出了ＰＭＤ作为统计量的测试准确率极限；最后，对这些测试方法进行了有益的比较 。     

基于改进FSM的协议一致性测试方法

介绍了一种基于FSM(finite state machine)的生成一致性测试序列的改进算法,该方法混合了UIO(unique input/output)方法和T方法,UIO方法的测试能力优于T方法,但是生成的测试序列的长度较后者要长一些。实验结果表明,本改进方法的能力与UIO方法相同,并且测试序列的长度接近于T方法。     

绝缘栅双极晶体管直流电参数高温性能的测试与分析

通过对绝缘栅双极晶体管（ＩＧＢＴ）直流参数温度特性的测试分析并与ＶＤＭＯＳＦＥＴ进行比较，从中得出ＩＧＢＴ能够承受更大的电流密度，其导通压降在高温下较之ＶＤＭＯＳＦＥＴ有较大的优势。     

深亚微米PESD MOSFET特性研究及优化设计

本文对多晶抬高源漏（ＰＥＳＤ）ＭＯＳＦＥＴ的结构作了描述，并对深亚微米ＰＥＳＤＭＯＳ－ＦＥＴ的特性进行了模拟和研究，看到ＰＥＳＤＭＯＳＦＥＴ具有比较好的短沟道特性和亚阈值特性，其输出电流和跨导较大，且对热载流子效应的抑制能力较强，因此具有比较好的性能．给出了ＰＥＳＤＭＯＳＦＥＴ的优化设计方法．当ＭＯＳＦＥＴ尺寸缩小到深亚微米范围时，ＰＥＳＤＭＯＳ－ＦＥＴ将成为一种较为理想的器件结构     

深亚微米PESD MOSFET特性研究及优化设计

本文对多晶抬高源漏（ＰＥＳＤ）ＭＯＳＦＥＴ的结构作了描述，并对深亚微米ＰＥＳＤＭＯＳ－ＦＥＴ的特性进行了模拟和研究，看到ＰＥＳＤＭＯＳＦＥＴ具有比较好的短沟道特性和亚阈值特性，其输出电流和跨导较大，且对热载流子效应的抑制能力较强，因此具有比较好的性能．给出了ＰＥＳＤＭＯＳＦＥＴ的优化设计方法．当ＭＯＳＦＥＴ尺寸缩小到深亚微米范围时，ＰＥＳＤＭＯＳ－ＦＥＴ将成为一种较为理想的器件结构     

基于四阶累量的MUSIC算法对阵元误差的稳健性分析

本文分析了基于四阶累量的ＭＵＳＩＣ算法（记作ＦＯＣ－ＭＵＳＩＣ），在实际阵元存在幅相误差时，对波达方向（ＤＯＡ）的估计性能，给出了大样本情况下的估计方差公式，并与基于协方差矩阵的标准ＭＵＳＩＣ算法作了比较。计算机仿真结果表明，本文给出的方差公式与实验仿真结果十分接近。文中还给出了利用高阶累量的方法可获得阵列有效孔径扩展的新解释。     

基于数据流的软件测试序列自动生成技术研究

测试用例自动生成技术是软件测试的一个重要研究领域，而如何从待测试程序中选取适当的测试序列集合是其中的一个关键问题。文章提出一种构造结构性测试序列集合的方法，此方法首先对待测试程序进行静态分析，然后根据程序的语句间关系生成程序图，最后基于数据流测试准则，根据程序图以及变量的定义和使用信息构造结构性测试序列集合。在Linux平台上使用这种方法对若干条程序进行分析处理，得到的测试序列集合可以使待测试程序得到充分测试。本文提出的方法具有比较高的测试覆盖，同时，在计算过程中避免了无用路径的生成，节省了算法空间和执行时间。     

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. In this context, it has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. In this paper, we show that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non-robust tests are under consideration. Experimental results given in this paper are based on a software generation of RSIC test sequences that can be easily generated in this case. For a built-in self-test (BIST) purpose, hardware generated RSIC sequences have to be used. This kind of generation will be shortly discussed at the end of the paper.     

Optimal length test sequence generation using distinguishingsequences

The optimization of the length of test sequences for finite state machine based protocol conformance testing is studied. The study focuses on test generation methods, called D-methods, that utilize distinguishing sequences in the construction of test segments. The extent of the optimization of the length of a test sequence is investigated with respect to two cases. The first case establishes the lower bound for the length of test sequences generated by any D-method that overlaps test segments. The second case establishes the lower bound for the length of test sequences generated by any D-method that does not overlap test segments. It is observed that the reduction in the length of test sequences due to overlapping is significant. An efficient algorithm for the generation of test sequences is proposed. This algorithm utilizes a distinguishing sequence and overlaps test segments. Sufficiency conditions are given both for finding a minimum- length test sequence in polynomial time and for constructing the optimal length test sequences by this algorithm     

Guaranteed fault detection sequences for single transition faults in finite state machine models using concurrent fault simulation

This paper presents a new algorithm for the generation of test sequences for finite state machines. Test sequence generation is based on the transition fault model, and the generation of state-pair distinguishing sequences. We show that the use of state-pair distinguishing sequences generated from a fault-free finite state machine will remain a distinguishing sequence even in the presence of a single transition fault, thus guaranteeing complete single transition fault coverage. Analysis and experimental results show that the complexity of the test sequence generation algorithm is less than those of the previous algorithms. The utility of the transition fault model, and the generated test sequences is shown by their application to sequential logic circuits. These results show more than a factor of 10 improvement in the test generation time and some reduction in test length while maintaining 100% transition fault coverage.Now with Intel Corporation, FM5-161, 1900 Prairie City Road, Folsom, CA 95630.Now with Chrysalis Symbolic Design, 101 Billerica Ave., North Billerica, MA 01862.     

基于UIO的协议一致性测试序列生成方法改进

在协议一致性测试中关键则在于寻找一条简捷高效的测试序列。在基于UIO序列的基础上提出BUIO序列的方法,并运用中国邮递员算法和启发式算法对其进行优化。     

Synchronization and Specification Issues in Protocol Testing

Protocol testing for the purpose of certifying the implementation's adherence to the protocol specification can be done with a test architecture consisting of remote tester and local responder processes generating specific input stimuli, called test sequences, and observing the output produced by the implementation under test. It is possible to adapt test sequence generation techniques for finite state machines, such as transition tour, characterization, and checking sequence methods, to generate test sequences for protocols specified as incomplete finite state machines. For certain test sequences, the tester or responder processes are forced to consider the timing of an interaction in which they have not taken part; these test sequences are called nonsynchronizable. The three test sequence generation algorithms are modified to obtain synchronizable test sequences. The checking of a given protocol for intrinsic synchronization problems is also discussed. Complexities of synchronizable test sequence generation algorithms are given and complete testing of a protocol is shown to be infeasible. To extend the applicability of the characterization and checking sequences, different methods are proposed to enhance the protocol specifications: special test input interactions are defined and a methodology is developed to complete the protocol specifications.     

基于变周期重播种LFSR的测试生成

基于重播种的LFSR结构的伪随机测试生成中包含的冗余测试序列较多,因而其测试序列长度仍较长,耗费测试时间长,测试效率不高。针对此状况,提出基于变周期重播种的LFSR结构的测试生成方法。该方法可以有效地跳过伪随机测试生成中的大量冗余测试序列。在保证电路测试故障覆盖率不变的条件下,缩短总测试序列的长度。分析结果表明,同定长重播种方法相比,该方法能以较少的硬件开销实现测试序列的精简,加快了测试的速度,提高了电路测试诊断的效率。     

一种通信协议测试序列生成的新方法

本文讨论了一种协议测试的新方法,它使用构造类别代数述通信协议规范,然后根据规范中的公理部分生成测试序列。本文以栈规范为例介绍这种方法的应用。并通过与基于有限状态机的测试序列生成方法相比较,得出两种方法在一些方面是等效的,但在处理状态较多的协议时,这种方法有一定的优点。     

Test generation,design-for-testability and built-in self-test for arithmetic units based on graph labeling

In this article we discuss a test generation, design-for-testability and built-in self-test methodology for two-dimensional iterative logic arrays (ILAs) that perform arithmetic functions. Our approach is unique because a single graph labeling procedure is used to generate test vectors, implement design-for-testability as well as design the circuitry for built-in self-test. The graph labeling is based on mathematical properties of full-addition such as symmetry and self-duality. Circuit modifications are introduced by a systematic procedure based on the graph labeling, that enable them to be tested with a fixed number of tests irrespective of their size. The approach is novel as it also greatly simplifies the processes of on-chip test vector generation and response comparison that are necessary for built-in self-test. Each circuit module is tested in a pseudo-exhaustive manner with deterministic as opposed to random test sequences. This results in a comprehensive test of the circuit for which built-in self-test is designed.This research was supported by the General Electric Company and by the Semiconductor Research Corporation under contracts SRC RSCH 88-DP-108 at the University of Illinois and SRC RSCH 89-DP-142 at the University of Texas at Austin.