Harmonic distortion in single-channel MOS integrated circuits

Expressions assuming a simple square-law MOSFET model are presented for the low-frequency harmonic distortion of an enhancement-mode source follower. These theoretical results are compared to measurements of several integrated versions of the three circuit types. For a given fabrication process, the main factors determining the amount of distortion for all three circuits are the quiescent output voltage and the output swing; to a first order, the distortion does not depend on bias current or device geometries. The distortion of an enhancement-mode source follower has a similar behavior to that of an enhancement-load inverter with the same output quiescent voltage and output swing; both distortions are nearly proportional to the body-effect coefficient. For the same output quiescent voltage and output swing, the distortion of the depletion-load inverter is the highest among the three circuits, but is practically independent of process parameters.     

Harmonic performance of single-channel MOS integrated circuits

Using simple square-law models for both the MOSFET current-voltage characteristics and the relationship between the threshold voltage and the source-to-substrate voltage, simple expressions are presented for predicting the performance of the basic MOSFET circuits used in analog MOS technology. Using these expressions, the low-frequency gain and the second and third harmonic distortion performance of the enhancement-load inverters, enhancement-load source follower, depletion-load inverter, and depletion-load source follower can be easily predicted by hand calculations. The results obtained by using these expressions are compared with previously published measurements and calculations.     

A method to predict harmonic distortion in small-geometry MOS analog integrated circuits

A method to predict the small-signal linear gain and level of harmonic distortion in analog MOS circuits is presented. This method, based on a generalized nonlinear transfer function approach, lends itself to implementation in the AC small-signal analysis routine of the circuit simulation program SPICE. A low-frequency nonlinear distortion model based on the CSIM simulator MOSFET model is applied to three simple MOSFET circuits. Results presented emphasize the need to consider small-signal quantities in the development of MOSFET models and in the determination of device parameters. The method can be easily extended to include capacitive effects and a prediction of intermodulation distortion.     

Design considerations in single-channel MOS analog integrated circuits-a tutorial

The design of single-channel MOS analog integrated circuits is discussed. Simple models are presented and approximate design equations are given for basic analog cells. The emphasis is on first-order analysis as a starting point for computer-aided design.     

Calculator-aided design of MOS integrated circuits

A set of programs has been developed for the characterization of the d.c. and transient behavior of MOS integrated circuits. The d.c. analysis program calculates and plots the voltage transfer and power dissipation characteristic of a MOS inverter approached from a new point of view. The algorithm enables the characterization of basic MOS IC cells on desktop calculators. The program for the transient characterization calculates and plots the output waveform of three simple MOS cells most often occurring in MOS IC's.The MOS transistor is simulated in terms of a four-terminal large signal model described by device processing parameters. Complex MOS IC's can be also characterized by appropriate combining of these programs.     

Protective device for MOS integrated circuits

Two protective devices for MOS integrated circuits have been extensively tested and proved feasible. They also perform more reliably than conventional Zener diodes. One of them has been used in the fabrication of a dual 25-bit MOS and MNOS integrated shift register and performed reliably.     

Comparing MOS and bipolar integrated circuits

In terms of speed and speed/power performance, bipolar integrated circuits are superior to metal-oxide-semiconductor integrated circuits. This superiority is based on the high transconductance inherent in bipolar transistors and is technology-independent. For the MOS case, transconductance is highly technology-dependent, and hence the performance difference will probably diminish in the future. Comparisons of the two technologies in their mid-1966 forms are made; the bipolar performance advantage in most cases is between 10 and 100. MOS integrated circuits have an area-per-function advantage ratio of about 5 for equivalent-function circuits, but a ratio of between 5 and 10 when circuits exploiting the unique MOS properties are considered. In addition, MOS processing is simpler than bipolar processing by approximately 40 percent.     

Potential of MOS technologies for analog integrated circuits

Reviews the rapid progress in MOS analog circuit techniques over the past three years, and attempts to estimate the near-term attainable characteristics of MOS LSI circuits which incorporate both analog and digital functions.     

Analysis and CAD implementation techniques of total harmonic distortion in analog VLSI circuits

This paper presents a new methodlogy to accurately evaluate the total harmonic distortion (THD) behavior of modern integrated circuits. The methodology is general, technology independent and is used to determine large-signal or reactive THD of signal processing circuits operating in the voltage or the current domain. It is based on Fourier series analysis and Parseval's theorem, where numerical integration may be needed to accurately compute THD. For low-frequency THD, the numerical integration can be simplified to a small number of summation without degrading the accuracy. The new methodology is incorporated in a computer-aided environment which accurately estimates THD, and the speed of calculation for many circuit is several orders of magnitude faster than SPICE or other commercial CAD tools. In addition, optimization of transistor sizes to reduce THD can be achieved by incorporating the methodology in an object-oriented CAD tool such as APLAC.Currently on leave as a Fulbright-Hays professor at the Helsinki University of Technology, Finland.     

Technology and performance of integrated complementary MOS circuits

The desirable characteristics of complementary MOS circuits are low standby power consumption, high speed, and high noise immunity. These require close control and matching of n- and p-channel transistor characteristics. Acceptable limits for mismatch between devices were derived based on circuit considerations and were related to process variables. Predicted performances were achieved using test circuits; feasibility of the technology has been shown. The reliability of fabricated test structures was evaluated.     

An optimized output stage for MOS integrated circuits

An output device for optimizing propagation delay and minimizing chip area is described. An optimum means of tapering the output stages to minimize propagation delay is determined. The minimum delay is a function of the capacitive load to node ratio, the number of output stages, and the interstage propagation delay. The effects on area are also presented. A figure of merit which is a function of area and propagation time is defined which is of use in designing output stages. An optimum exists which can be considered the best compromise between further decreasing propagation delay and increasing chip area. Data is also presented which allows a designer to determine the minimum chip area once the capacitive load and the maximum allowable delay are known.     

Computer-aided design and characterization of digital MOS integrated circuits

A computer-aided circuit-simulation method is developed to enable the design, characterization, and optimization of MOS integrated circuits. The computation of dc and transient characteristics is done in terms of physical device parameters extracted from processing information and incorporated in an analytical device model. It is demonstrated that any MOS circuit configuration (with its associated series resistances and parasitic devices) can be analyzed in terms of an equivalent inverter. Input-output transfer characteristics are obtained by superposition of the load and transistor I-V characteristics, providing the necessary information for dc > `worst-case' design. A simple device model was used to compute circuit transient response. All the computed characteristics are in good agreement with measurements performed on integrated circuits.     

Behavior of analog MOS integrated circuits at high temperatures

Thermal effects on small-signal characteristics of MOS transistors are studied and parameters of MOS amplifiers operating at high temperatures are calculated. The predicted performance has been experimentally verified and high-temperature measurements of an operational amplifier and a switched-capacitor precision amplifier are presented.     

Topology dependence of floating gate faults in MOS integrated circuits

Models for floating gate faults in MOS integrated circuits are introduced. It is experimentally demonstrated that these models are mask-topology-dependent. The logic state of the gate can be stuck-at, undefined or influenced. In the case of an influenced gate a `pseudo-MOS transistor? is defined.     

Computer analysis of the double-diffused MOS transistor for integrated circuits

The effective length of an MOS transistor can be made narrow by using double diffusion similar to a bipolar transistor. Computations were conducted for an n-channel double-diffused transistor with different surface concentrations, channel lengths, channel gradients, surface-states densities, and substrate concentrations. A shorter channel length and a higher surface-state density, e.g.langle1, 1, 1ranglecrystal, gave a higher drain current and transconductance. The maximum transconductance in many cases occurs at low gate voltages. The computations indicate that a gain-bandwidth product in the gigahertz range can be expected when the graded channel region is less than 1 µm. The difference between an n-type substrate and a p-type substrate is not substantial. The analysis is also useful in predicting the performance of any integrated logic circuit using the diffused enhancement transistor as the active switch and a depletion-mode transistor (without a diffused channel) as the load device. The computation indicates that satisfactory performance can be obtained using a load device with the same geometry and an ON voltage of only a fraction of a volt, This revelation indicates that double-diffused channel MOS transistors not only give higher speed but also smaller chip area for integrated circuits and a lower supply voltage (hence less power dissipation).     

In-process voltage stressing to increase reliability of MOS integrated circuits

Time-dependent dielectric breakdown of gate oxides is one of the principal failure mechanisms of MOS integrated circuits. Voltage stressing of completed devices, which has been used to screen oxide defects and to thereby increase product reliability, is less effective with scaled high-density MOS integrated circuits because of limitations in the voltage which can be applied. Inprocess voltage stressing of silicon wafers, prior to completion of wafer processing, offers a feasible technique for achieving an effective voltage screen. Several possible techniques for inprocess voltage stressing are described, and the advantages and limitations of these are outlined. Data are presented showing typical fast-ramp dielectric breakdown distributions for MOS transistor arrays with an oxide thickness of 35 and 50 nm. Time-dependent dielectric breakdown distribution data on devices from the same wafers indicate that with all MOS transistors of an integrated circuit connected in parallel, as in one type of inprocess voltage stressing, defective oxide sites can be screened in periods of time ranging from a few seconds to hours. Inprocess voltage stressing, by decreasing susceptibility of completed devices to time-dependent dielectric breakdown, can substantially increase MOS integrated circuit reliability.     

Selective ion implantation to reduce power consumption in MOS integrated circuits

A method of using implantation to reducek'in selected MOS transistors on an LSI chip is described. An application of this technique is described where the power consumed in circuits such as memory cells is reduced without impairing other operating parameters.     

Analogue MOS current-mode circuits for three-dimensional integrated smart image sensor

An image processing technique using analogue MOS current-mode circuits is presented. This approach is of interest in smart image sensors based on three-dimensional (or multi-layered) VLSI structures. High-performance smart image sensors with high resolution can be realised because the number of transistors required for image processing in each pixel is greatly reduced.<>     

A new buried-oxide isolation for high-speed high-density MOS integrated circuits

The BO-MOS has an extensive oxide-isolated structure which isolates not only the sidewall but also the bottom of the source and drain diffusions, similar to SOS-MOS, and yet it retains high carrier mobility and low-leakage junction properties. A 1024-bit static NMOS RAM is successfully fabricated using photomasks of a redesigned high-density bulk NMOS RAM (Fujitsu MBM8115). The ring oscillator circuit fabricated using existing SOS-CMOS photomasks shows an equivalent speed-power performance to the original SOS device. The fabrication sequence for the BO-MOS requires the same number of photomasks as for the conventional MOS devices.