Role of positive trapped charge in stress-induced leakage current for flash EEPROM devices

The transient behavior of hot hole (HH) stress-induced leakage current (SILC) in tunnel oxides is investigated. The dominant SILC mechanism is positive oxide charge-assisted tunneling (PCAT). The transient effect of SILC is attributed to positive oxide charge detrapping and thus the reduction of PCAT current. A correlation between SILC and stress-induced substrate current is observed. Our study shows that both SILC and stress-induced substrate current have power law time-dependence t/sup -n/ with the power factor n about 0.7 and 1, respectively. Numerical analysis for PCAT current incorporating a trapped charge caused Coulombic potential in the tunneling barrier is performed to evaluate the time- and field-dependence of SILC and the substrate current. Based on our model, the evolution of threshold voltage shift with read-disturb time in a flash EEPROM cell is derived. Finally, the dependence of SILC on oxide thickness is explored. As oxide thickness reduces from 100 /spl Aring/ to 53 /spl Aring/, the dominant SILC mechanism is found to change from PCAT to neutral trap-assisted tunneling (TAT).     

Characterization of hot-hole injection induced SILC and relateddisturbs in flash memories

In this paper, we have proposed a new method for the study of disturb failure mechanisms caused by stress induced leakage current (SILC) in source-side erased flash memories. This method is able to directly separate the individual components of SILC due to either carrier charging/discharging in the oxide or the positive charge/trap assisted electron tunneling into the floating gate. In addition, the present method is very sensitive with capability of measuring ultralow current (<10^-19 A). Results show that, at low oxide field, the disturb is mainly contributed by the so-called charging/discharging of carriers into/from the oxide due to the capacitance coupling effect. While at high oxide field, the positive charge/trap assisted electron tunneling induced floating-gate charge variation is the major cause of disturb failure     

Measurement of ultralow gate tunneling currents using floating-gate integrator technique

We report for the first time that a gate tunneling current measurement sensitivity better than 3/spl times/10/sup -22/ A has been achieved by using a floating-gate integrator technique. The technique involves monitoring the charge change in the floating-gate integrated with an on-chip op-amp and an on-chip feedback capacitor. We used this technique to study the stress-induced leakage current (SILC) and its cycling dependence of 70 /spl Aring/ oxides in the direct tunneling region at oxide voltage as low as 1.9 V. The technique has been validated through correlation to direct measurement on MOSFET arrays and theoretical calculations. The measured SILC current is modeled with an Inelastic trap-assisted tunneling model.     

Modeling of SILC based on electron and hole tunneling. I. Transienteffects

A detailed investigation of the steady-state and transient leakage currents in thin oxides is proposed. The experimental data are compared with numerical results obtained from a model based on an inelastic trap-assisted tunneling process, which includes both electron and hole contributions. In order to accurately reproduce the transient discharge currents, a continuous distribution of oxide traps was adopted. The energies of these levels can be either in correspondence of the conduction or valence band edges of the adjacent silicon/polysilicon layers. Both electrons and holes contribute to the transient stress-induced leakage current (SILC), but the extracted trap densities cannot account for the steady-state SILC. A different mechanism, involving trap levels with energy aligned to the energy gap of the silicon layers is proposed and is developed in the following paper. The model can be applied to any type of device and bias conditions and may be used to correctly recognize the role of electron and hole SILC and the spatial and energy distribution of defect states     

A comprehensive study of hot carrier stress-induced drain leakagecurrent degradation in thin-oxide n-MOSFETs

The mechanisms and characteristics of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs are investigated. Both interface trap and oxide charge effects are analyzed. Various drain leakage current components at zero V_gs such as drain-to source subthreshold leakage, band-to-band tunneling current, and interface trap-induced leakage are taken into account. The trap-assisted drain leakage mechanisms include charge sequential tunneling current, thermionic-field emission current, and Shockley-Read-Hall generation current. The dependence of drain leakage current on supply voltage, temperature, and oxide thickness is characterized. Our result shows that the trap-assisted leakage may become a dominant drain leakage mechanism as supply voltage is reduced. In addition, a strong oxide thickness dependence of drain leakage degradation is observed. In ultra-thin gate oxide (30 Å) n-MOSFETs, drain leakage current degradation is attributed mostly to interface trap creation, while in thicker oxide (53 Å) devices, the drain leakage current exhibits two-stage degradation, a power law degradation rate in the initial stage due to interface trap generation, followed by an accelerated degradation rate in the second stage caused by oxide charge creation     

The impacts of SILC and hot carrier induced drain leakage current on the refresh time in DRAM

This paper reports the temperature dependence of SILC and hot carrier induced drain leakage current, and their impact on the refresh time in Giga-bit level DRAM with practical considerations. SILC has been found to increase as the monitoring and stress temperature increases. Due to the generation of interface states, hot carrier induced pn junction leakage current and band-to-band tunneling current have been found to increase as the monitoring temperature increases.From the simulation results of a refresh circuit for Giga-bit level DRAM, it has been found that the increase of SILC with stress time is a dominant factor in refresh failure below 373K, and the pn junction leakage current will be a dominant factor at the high elevated temperature. It has been also observed that the increase of hot carrier induced drain leakage current can be a cause for the refresh failure.     

Investigation of oxide charge trapping and detrapping in a MOSFETby using a GIDL current technique

We proposed a new measurement technique to investigate oxide charge trapping and detrapping in a hot carrier stressed n-MOSFET by measuring a GIDL current transient. This measurement technique is based on the concept that in a MOSFET the Si surface field and thus GIDL current vary with oxide trapped charge. By monitoring the temporal evolution of GIDL current, the oxide charge trapping/detrapping characteristics can be obtained. An analytical model accounting for the time-dependence of an oxide charge detrapping induced GIDL current transient was derived. A specially designed measurement consisting of oxide trap creation, oxide trap filling with electrons or holes and oxide charge detrapping was performed. Two hot carrier stress methods, channel hot electron injection and band-to-band tunneling induced hot hole injection, were employed in this work. Both electron detrapping and hole detrapping induced GIDL current transients mere observed in the same device. The time-dependence of the transients indicates that oxide charge detrapping is mainly achieved via field enhanced tunneling. In addition, we used this technique to characterize oxide trap growth in the two hot carrier stress conditions. The result reveals that the hot hole stress is about 10⁴ times more efficient in trap generation than the hot electron stress in terms of injected charge     

Total dose dependence of radiation-induced leakage current in ultra-thin gate oxides

Radiation-induced leakage current (RILC) has been studied on ultra-thin gate oxides (4 and 6 nm) irradiated with 8 MeV electrons. Both RILC and stress-induced leakage current (SILC) have been fitted with the same Fowler–Nordheim law, suggesting that RILC and SILC have similar conduction mechanisms. The RILC dependence from total dose during irradiation has been analysed and compared with the SILC dependence from the cumulative injected charge. Different growth laws of RILC and SILC have been found in the two cases. The intensity of positive and negative RILC also depends on the applied gate bias voltage during irradiation, probably reflecting different distributions of the oxide traps mediating the trap assisted tunnelling. Finally, we have presented the first evidence of a quasi-breakdown phenomenon due to ionizing radiation.     

Mechanism of stress-induced leakage current in MOS capacitors

Stress-induced leakage current (SILC) is examined both below and above the voltage at which the preexisting Fowler-Nordheim tunneling current dominates. Based on these results, it is argued that SILC is the result of inelastic rather than elastic trap-assisted tunneling. This clarification explains the well-known thickness dependence of the SILC at low fields that has identified it as a scaling limitation for nonvolatile memory tunnel oxide. It also explains a newly observed different thickness dependence at high fields and facilitates modeling of the electric field/voltage and trap density dependencies of the SILC     

Degradation of ultra-thin gate oxide LDD NMOSFET under GIDL stress

The degradation of device under GIDL(gate-induced drain leakage current)stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides.Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg.The characteristics of the GIDL current are used to analyze the damage generated during the stress.It is clearly found that the change of GIDL current before and after stress can be divided into two stages.The trapping of holes in the oxide is dominant in the first stage,but that of electrons in the oxide is dominant in the second stage.It is due to the common effects of edge direct tunneling and band-to-band tunneling.SILC(stress induced leakage current)in the NMOSFET decreases with increasing stress time under GIDL stress.The degradation characteristic of SILC also shows saturating time dependence.SILC is strongly dependent on the measured gate voltage.The higher the measured gate voltage,the less serious the degradation of the gate current.A likely mechanism is presented to explain the origin of SILC during GIDL stress.     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化. 实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流（SILC）的退化和Vth的退化均存在线性关系. 为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化.实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流(SILC)的退化和Vth的退化均存在线性关系.为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

Modeling of SILC based on electron and hole tunneling. II.Steady-state

For pt. I see ibid., vol. 47, no. 6 (June 2000). A numerical model for the stationary stress-induced leakage current (SILC) is presented, accounting for both electron and hole tunneling. Detailed comparisons against experimental results on both n- and p-channel devices highlight that the steady-state SILC is due to positively charged centers, with an energy level located in correspondence of the silicon bandgap. Electron-hole recombination at these sites dominates normal trap-assisted tunneling at low oxide fields, and successfully accounts for recently observed hole steady-state leakage. The contribution from neutral traps seems instead marginal. Based on this new picture, the impact of the recombination process on the leakage properties of ultrathin gate is also discussed     

Simplified quantitative stress-induced leakage current (SILC) model for MOS devices

A simplified quantitative model for the steady-state component of stress-induced leakage current (SILC) in MOS capacitors with ultrathin oxide layers has been developed by assuming a two-step inelastic trap-assisted tunneling (ITAT) process as the conduction mechanism. By using our model, we reduced the time of numerical calculations of SILC to 17% of the standard method while maintaining a high accuracy of the results. We also confirmed that the SILC component must not be neglected when calculating the gate current in modern devices, especially at low fields. Our simplified model helped us to investigate the dependence of SILC on the oxide field and the oxide thickness. We also shed some light on the reasons that cause the peak in the SILC–oxide thickness relation.     

On the correlation between SILC and hole fluence throughout the oxide

Stress-induced leakage current (SILC) has been recognized as a topic of concern in flash memory reliability. It is a reliable failure mechanism, occurring long before oxide breakdown and, hence, limiting oxide lifetime[1]. The physical origin and mechanisms of SILC have not yet been clearly understood and several points open to discussion remain. In this work the role of oxide hole fluence in producing the SILC is discussed. An universal power law of SILC generation kinetics is proposed versus the hole fluence throughout the oxide. The experimental results are theoretically validated by modeling the measured quantum-yield by the contributions of both anode hole injection and electron valence band injection mechanisms.     

Body effect induced wear-out acceleration in ultra-thin oxides

In this study, body effect influence on oxide degradation is analyzed. It is found that the negative bias polarization on the n-well of a p-channel MOS transistor may induce a significant reduction of the oxide lifetime as well as an increase of stress-induced leakage current (SILC). Such a result is demonstrated to confirm the key role of hot holes on SILC and breakdown phenomena. Moreover, even if the hot hole generated at the anode are probably at the origin of SILC and can be interpreted as a catalyst of breakdown, it is undoubtedly shown that both phenomena are not directly correlated: SILC at breakdown can not be ascribed to a critical density of defect at failure.     

Characterization of various stress-induced oxide traps in MOSFET'sby using a subthreshold transient current technique

An oxide trap characterization technique by measuring a subthreshold current transient is developed. This technique consists of two alternating phases, an oxide charge detrapping phase and a subthreshold current measurement phase. An analytical model relating a subthreshold current transient to oxide charge tunnel detrapping is derived. By taking advantage of a large difference between interface trap and oxide trap time-constants, this transient technique allows the characterization of oxide traps separately in the presence of interface traps. Oxide traps created by three different stress methods, channel Fowler-Nordheim (F-N) stress, hot electron stress and hot hole stress, are characterized. By varying the gate bias in the detrapping phase and the drain bias in the measurement phase, the field dependence of oxide charge detrapping and the spatial distribution of oxide traps in the channel direction can be obtained. Our results show that 1) the subthreshold current transient follows a power-law time-dependence at a small charge detrapping field, 2) while the hot hole stress generated oxide traps have a largest density, their spatial distribution in the channel is narrowest as compared to the other two stresses, and 3) the hot hole stress created oxide charges exhibit a shortest effective detrapping time-constant     

Defect generation statistics in thin gate oxides

We analyze data-retention experiments for flash memory arrays with thin tunnel oxide (t/sub ox/ = 5 nm). These samples show an additional conduction mechanism besides Fowler-Nordheim tunneling and stress-induced leakage current (SILC). The additional leakage contribution is analyzed with respect to the spatial distribution in the array and the shape of the current-voltage characteristics, and is interpreted as an anomalous SILC due to a two-trap leakage path. From the cycling dependence of the distribution tails related to one- and two-trap leakage, we provide evidence that the defect generation statistics is not Poissonian, but is instead correlated. Possible physical mechanisms responsible for correlated generation are also discussed.     

Shot noise partial suppression in the SILO regime

The power spectral densities of the current fluctuations through fresh and stressed thin oxide are investigated by means of a purposely designed ultra low noise measurement system. It is reported for the first time that the SILC noise spectrum exhibits partially suppressed shot noise down to about 70% with respect to the full shot noise observed for fresh oxide in Fowler-Nordheim regime. It is shown that a single trap assisted tunneling model with a uniform trap distribution in both energy and space is able to justify the observed noise behavior