Processors and FPGAs Quo Vadis?

Electronic applications continue to demand increased flexibility, configurability, and performance, along with reduced power consumption, board space, and cost. This is increasing pressure to integrate analog, memory, logic, and soft microcontroller unit (MCU) implementations into a single-system chip. As a result, analog, microcontroller, and application-specific integrated circuit (ASIC) suppliers are adding configurability to their product lines. As the race to develop programmable system chip solutions heats up, field-programmable gate array (FPGA) suppliers have a leg up on the competition because programmable logic has proved to be the most difficult of the necessary technologies to master     

Neuro-fuzzy chip to handle complex tasks with analog performance.

This paper presents a mixed-signal neuro-fuzzy controller chip which, in terms of power consumption, input-output delay, and precision, performs as a fully analog implementation. However, it has much larger complexity than its purely analog counterparts. This combination of performance and complexity is achieved through the use of a mixed-signal architecture consisting of a programmable analog core of reduced complexity, and a strategy, and the associated mixed-signal circuitry, to cover the whole input space through the dynamic programming of this core. Since errors and delays are proportional to the reduced number of fuzzy rules included in the analog core, they are much smaller than in the case where the whole rule set is implemented by analog circuitry. Also, the area and the power consumption of the new architecture are smaller than those of its purely analog counterparts simply because most rules are implemented through programming. The paper presents a set of building blocks associated to this architecture, and gives results for an exemplary prototype. This prototype, called multiplexing fuzzy controller (MFCON), has been realized in a CMOS 0.7 /spl mu/m standard technology. It has two inputs, implements 64 rules, and features 500 ns of input to output delay with 16-mW of power consumption. Results from the chip in a control application with a dc motor are also provided.     

0.8 /spl mu/m CMOS implementation of weighted-order statistic image filter based on cellular neural network architecture.

In this paper, a very large scale integration chip of an analog image weighted-order statistic (WOS) filter based on cellular neural network (CNN) architecture for real-time applications is described. The chip has been implemented in CMOS AMS 0.8 /spl mu/m technology. CNN-based filter consists of feedforward nonlinear template B operating within the window of 3 /spl times/ 3 pixels around the central pixel being filtered. The feedforward nonlinear CNN coefficients have been realized using programmable nonlinear coupler circuits. The WOS filter chip allows for processing of images with 300 pixels horizontal resolution. The resolution can be increased by cascading of the chips. Experimental results of basic circuit building blocks measurements are presented. Functional tests of the chip have been performed using a special test setup for PAL composite video signal processing. Using the setup real images have been filtered by WOS filter chip under test.     

Dynamically Reconfigurable Silicon Array of Spiking Neurons With Conductance-Based Synapses

A mixed-signal very large scale integration (VLSI) chip for large scale emulation of spiking neural networks is presented. The chip contains 2400 silicon neurons with fully programmable and reconfigurable synaptic connectivity. Each neuron implements a discrete-time model of a single-compartment cell. The model allows for analog membrane dynamics and an arbitrary number of synaptic connections, each with tunable conductance and reversal potential. The array of silicon neurons functions as an address-event (AE) transceiver, with incoming and outgoing spikes communicated over an asynchronous event-driven digital bus. Address encoding and conflict resolution of spiking events are implemented via a randomized arbitration scheme that ensures balanced servicing of event requests across the array. Routing of events is implemented externally using dynamically programmable random-access memory that stores a postsynaptic address, the conductance, and the reversal potential of each synaptic connection. Here, we describe the silicon neuron circuits, present experimental data characterizing the 3 mm times 3 mm chip fabricated in 0.5-mum complementary metal-oxide-semiconductor (CMOS) technology, and demonstrate its utility by configuring the hardware to emulate a model of attractor dynamics and waves of neural activity during sleep in rat hippocampus     

A programmable spike-timing based circuit block for reconfigurable neuromorphic computing

A generic programmable spike-timing based circuit which forms the building block of a reconfigurable neuromorphic array is implemented in analog VLSI. An array of programmable spike time event coded circuit blocks is configured to implement functional circuit blocks of a spike time based neuromorphic model. A reconfigurable neuromorphic array chip with 10 event blocks is fabricated using Austria Microsystems m CMOS technology to demonstrate the functionality of the circuits in silicon.     

嵌入式测试系统用高精度数控恒压恒流源

针对电磁阀产品性能测试的需要,开发了一种基于DSPIC33EV128单片机的数控恒压恒流电源装置.采用UCC27211半桥驱动芯片,由精密采样电阻和AD8417组成精准的输出电流的高边采样,电阻串联分压反馈输出电压,单片机内部数字运用PI闭环算法.电源工作方式可由外部电位器或者采集卡AO模拟量控制,或是PC机串口协议控制,并通过串口上传当前实时电压电流值.实验测试显示,电流、电压调节精度可达1%F.S.     

Emerging Research Architectures

Morphic architectures embrace a broad class of mixed-signal systems that focus on a particular application and draw inspiration for their structure from the application. In some cases, processing is carried out in the analog domain, offering orders-of-magnitude improvement in performance and power dissipation, albeit with reduced accuracy. The emergence of many-core (symmetric and asymmetric) architectures has become an established industry trend. With high-end microprocessor architecture moving to a multicore format, dual-core products have become available commercially and quad-core chips are entering the marketplace. Indeed, a recently announced 80-core experimental chip heralds a new milestone. Several other companies now produce multicore-like devices that some call next-generation field-programmable gate arrays (FPGAs). Specifically, these companies are implementing field- programmable object array (FPOA) technology, which consists of object arrays that are simple processors and other support objects such as memory.     

VLSI neuroprocessors for video motion detection

The system design of a locally connected competitive neural network for video motion detection is presented. The motion information from a sequence of image data can be determined through a two-dimensional multiprocessor array in which each processing element consists of an analog neuroprocessor. Massively parallel neurocomputing is done by compact and efficient neuroprocessors. Local data transfer between the neuroprocessors is performed by using an analog point-to-point interconnection scheme. To maintain strong signal strength over the whole system, global data communication between the host computer and neuroprocessors is carried out in a digital common bus. A mixed-signal very large scale integration (VLSI) neural chip that includes multiple neuroprocessors for fast video motion detection has been developed. Measured results of the programmable synapse, and winner-takes-all circuitry are presented. Based on the measurement data, system-level analysis on a sequence of real-world images was conducted.     

A comparative study of access topologies for chip-level address-event communication channels

We examine channel access algorithms and circuits for intra and inter chip communication channels. Classical access techniques such as arbitration, scanning, ALOHA, and priority encoding are compared by assessing throughput, latency, and power consumption. Our results provide guidance in the design of bio-inspired networks of processors, for efficient transmission of information with limited power consumption and reduced latency.     

Configurable analog signal processing

We present a viewpoint showing that analog signal processing approaches are becoming configurable and programmable like their digital counterparts, while retaining a huge computational efficiency, for a given power budget, compared to their digital counterparts. We present recent results in programmable and configurable analog signal processing describing the widespread potential of these approaches. We discuss issues with configurable systems, including size, power, and computational tradeoffs, as well as address the computational efficiency of these approaches. Analog circuits and systems research and education can significantly benefit from the computational flexibility provided by large-scale FPAAs. The component density of these devices is sufficient to synthesize large systems in a short period of time. However, this level of reconfigurable and programmable complexity requires a development platform and CAD tools to demonstrate the capabilities of large-scale FPAAs before they will be widely accepted. To address this need, a self-contained FPAA setup has been developed along with an integrated software design flow. With only an Ethernet connection and an AC power outlet, a researcher or student can explore the numerous analog circuit possibilities provided by large-scale FPAAs.     

一种带信号调理的24位A/D转换器AD7714的原理及应用

AD7714是美国Analog-Devices公司生产的高精度模数转换芯片。它采用∑-△转换技术实现高达24位的精度。片内还含有可编程增益放大器、可编程数字滤波器和寄存器,串行接口可进行3线操作,很适合于灵敏的基于微控制和DSP的系统。本文简明扼要的介绍了AD7714芯片的原理和应用。     

基于ZigBee无线传感网络技术节点设计与实现

利用各类传感器采集外界信息,产生模拟电压信号,通过模数转换进而得到数字信号,摒弃传统的有线串口发数模式,用CC2430芯片作为节点的核心芯片,负责数据处理和无线射频工作。根据以上要求给出了系统硬件结构及软件设计方案,并综合考虑到了节点的功耗问题。     

A Low-Power Multimedia SoC with Fully Programmable 3D Graphics for Mobile Devices

A low-power multimedia SoC integrates a fully programmable 3D graphics for mobile devices with an MPEG4/JPEG codec and H.264 decoder for mobile devices. A mobile unified shader achieves programmable vertex shading and pixel shading in a single die, reducing silicon area and power consumption by 35 percent and 28 percent, respectively. A logarithmic lighting engine and specialized lighting instruction improve the vertex fill rate, including transformations and lighting, to 9.1 million vertices per second. Implemented on a 6.4 mm times 6.4 mm chip with 0.13 mum CMOS logic, the SoC consumes less than 195 mW for 3D graphics applications at 1.2 V supply voltage and 100 MHz operating frequency and less than 152 mW for video applications.     

采用"回避精确增益法"设计高精度程控运放

针对“传统程控运放”和目前“集成数字程控运放”的局限性,提出一种新的程控运放设计方法。该方案采用普通运放、低精度“数字电位器”、模拟开关和电压基准芯片,完成了高精度“程控运放”的设计,从而回避运放的精确增益,不但增益级数可多可少,而且具体增益可通过改变外接电阻任意设定。此设计成本低、精度高、调试简单,尤其适合大批量产品的生产。     

An 0.5-μm CMOS analog random access memory chip for TeraOPSspeed multimedia video processing

Data compressing, data coding, and communications in object-oriented multimedia applications like telepresence, computer-aided medical diagnosis, or telesurgery require an enormous computing power-in the order of trillions of operations per second (TeraOPS). Compared with conventional digital technology, cellular neural/nonlinear network (CNN)-based computing is capable of realizing these TeraOPS-range image processing tasks in a cost-effective implementation. To exploit the computing power of the CNN Universal Machine (CNN-UM), the CNN chipset architecture has been developed-a mixed-signal hardware platform for CNN-based image processing. One of the nonstandard components of the chipset is the cache memory of the analog array processor, the analog random access memory (ARAM). This paper reports on an ARAM chip that has been designed and fabricated in a 0.5-μm CMOS technology. This chip consists of a fully addressable array of 32×256 analog memory registers and has a packing density of 637 analog-memory-cells/mm². Random and nondestructive access of the memory contents is available. Bottom-plate sampling techniques have been employed to eliminate harmonic distortion introduced by signal-dependent feedthrough. Signal coupling and interaction have been minimized by proper layout measures, including the use of protection rings and separate power supplies for the analog and the digital circuitry. This prototype features an equivalent resolution of up to 7 bits-measured by comparing the reconstructed waveform with the original input signal. Measured access times for writing/reading to/from the memory registers are of 200 ns. I/O rates via the l6-line-wide I/O bus exceed 10 Msamples/s. Storage time at room temperature is in the 80 to 100 ms range, without accuracy loss     

数字图像处理算法评估系统的硬件设计

为了能对不同的数字图像处理算法进行评估,采用了USB2．0总线技术传送数字图象数据到数字图像处理系统,在硬件设计上采用DSP＋FPGA来完成图像处理任务。整个系统具有处理能力强,重现性好,能完成各种图像处理算法评估。     

Neuron-synapse IC chip-set for large-scale chaotic neural networks.

We propose a neuron-synapse integrated circuit (IC) chip-set for large-scale chaotic neural networks. We use switched-capacitor (SC) circuit techniques to implement a three-internal-state transiently-chaotic neural network model. The SC chaotic neuron chip faithfully reproduces complex chaotic dynamics in real numbers through continuous state variables of the analog circuitry. We can digitally control most of the model parameters by means of programmable capacitive arrays embedded in the SC chaotic neuron chip. Since the output of the neuron is transfered into a digital pulse according to the all-or-nothing property of an axon, we design a synapse chip with digital circuits. We propose a memory-based synapse circuit architecture to achieve a rapid calculation of a vast number of weighted summations. Both of the SC neuron and the digital synapse circuits have been fabricated as IC forms. We have tested these IC chips extensively, and confirmed the functions and performance of the chip-set. The proposed neuron-synapse IC chip-set makes it possible to construct a scalable and reconfigurable large-scale chaotic neural network with 10000 neurons and 10000/sup 2/ synaptic connections.     

基于USB2.0接口的高速实时数据采集系统

分析了现有的高速数据采集系统,如基于PCI总线的数据采集系统、基于PLD的高速数据采集系统、基于DSP和USB2.0接口的高速数据采集系统以及基于USB和串行A/D转换的数据采集系统等优缺点,提出利用强大的USB2.0专用微处理器芯片CY7C68013构成性价比高的高速实时数据采集系统.通过对USB接口芯片CY7C68013A-100AXC的可编程接口控制逻辑的合理设计和芯片内部FIFO的有效运用,实现了数据的高速连续采样.最后由片内的USB引擎打包为USB数据帧传送至PC机,由用户保存可作进一步处理.该系统实时采集实时显示,易于扩展,传输距离长,能同时接受多个设备,电磁干扰小,安装方便,即插即用,性价比高.     

可编程中断控制器的仿真

Simulink可用作建模、分析和仿真各种动态系统的交互环境,通过Simulink提供的丰富模块资源和工具箱资源,用户很方便建立仿真模型。由于Simulink的模块库中,缺少各种可编程接口芯片模块,进行接口电路的仿真主要是通过确定电路的功能之后选择Simulink中的有关模块,对这些模块进行修改,重新封装,构建所需要的电路。结合Intel 8259A可编程中断控制器(PIC),介绍了利用Simulink对计算机接口电路进行仿真的过程。通过调用Simulink的模块库创建可编程芯片的仿真,删除芯片中多余的引脚,简化了各块芯片的复杂线路,突出了使用Simulink仿真的高效性和准确性。     

高速相机皮秒级可编程延迟单元电路设计

纳秒（ns）和亚纳秒高速相机各部件之间需要精密的可编程时间延迟来保证同步。本文提出一种基于EPLD和ASIC,数字和模拟时间延迟相结合的解决方案,延时长度可编程,延时分辨率可达皮秒（ps）级。该系统体积小,成本低,可实现参数设置、显示和控制等功能。