Design considerations for CMOS and GaAs OTAs: Frequency response,linearity, tuning,and common-mode feedback

High-performance operational transconductance amplifiers (OTAs) are important in the design of high-frequency analog transconductance-C (g _m -C) filters. Critical design considerations for OTAs are frequency response, linearity, tuning, output impedance, power supply rejection (PSR), and common-mode rejection (CMR). In CMOS technology, satisfactory OTA design techniques are available, except that the linear input range often is relatively small and the frequency response of the OTA is limited by the intrinsic speed of transistors. In this paper, a new approach is developed to increase the linear input range, and a trade-off between linearity and input range is discussed. A CMOS OTA with less than ±0.4% linearity error over a very large input range is given as a design example. To achieve a very high frequency response, 1m depletion-mode GaAs MESFETs with high intrinsic speed are used to replace MOSFETs. Simple ac compensation, a new technique for output impedance enhancement, and a new tuning method for OTAs with all N-channel devices are used to design a GaAs OTA with very small parasitics and f _–3dB=7 GHz. To improve PSR and CMR, fully balanced structures are used for the OTAs. Design considerations for the interaction of the operation of common-mode feedback (CMF) and tuning are discussed, and improved CMF circuits are proposed. Using the GaAs OTA and considering the frequency limitations imposed by parasitics, the design of a high order ladder filter with 300MHz cutoff frequency is presented as an application.     

Evaluation of the feasibility of satellite systems design in the 10–100 GHZ frequency range

We have presented a picture of the total attenuation to be considered in satellite communication and broadcasting systems in the 10–100 GHz frequency range. Although the findings and methodology are of general interest, the numerical results apply to the Italian (mid-latitude) sites of Fucino and Gera Lario and to slant paths of elevation angles 33° and 32° respectively. The rain attenuation probability distribution P(A), of exceeding the value A (dB) at a given carrier frequency in an average year, has been estimated by the synthetic storm technique and an associated formula, presently derived, which links A to frequency for fixed probabilities. The extra fading due to water vapour, clouds, oxygen and scintillations is estimated by applying the ITU-R formulae. After studying how the received carrier power P_R changes as a function of frequency for fixed antenna dimensions and transmitted carrier power P_T, we have carried out an exercise to show what first order values of P_T we need in an ideal QPSK modulation scheme, with a standard uncoded stream of 64 kbit/s, in a complete earth–satellite–earth connection, with regenerative or transparent transponders, for a given maximum bit error rate tolerated by users. After this analysis we have drawn the following conclusions: (a) the results depend very much on the outage probability and on the site; (b) there are two windows at high outage probabilities, e.g. 1%, the first in the 20–50 GHz frequency range and the second beyond 70 GHz; (c) in the frequency range 50–70 GHz any significant service availability level cannot be achieved because of the very large fading due to oxygen; (d) the transmitted power can show sharp minima which depend significantly on the outage probability and on the site; (e) service availability levels better than 99⋅99% of the year cannot be achieved at frequencies of 30 GHz and above, with ground station antennae of 25 cm or less aperture diameter. © 1998 John Wiley & Sons, Ltd.     

A coded 8-PSK system for 140 Mb/s information rate transmission over 80 MHz non-linear transponders

A combined 8-PSK modulation and rate 7/9 convolutional coding technique is proposed for 140 Mb/s information rate transmission over the 80 MHz INTELSAT transponders, thus achieving a bandwidth efficiency of 1.75 b/s/Hz of allocated bandwidth. The desired power efficiency is to achieve a bit error rate of 10^?6 at an E_b/N₀ of 11 dB, including modem and codec implementation losses. The proposed system employs an 8-PSK modem operating at a 60 MHz symbol rate (or 180 Mb/s bit rate), as well as a rate 7/9 convolutional encoder and a 16-state Viterbi algorithm decoder operating at 60 MHz. The rate 7/9 code is periodically time varying and is designed to maximize the Euclidean distance between the modulated codeword sequences, thereby achieving a 3 dB asymptotic coding gain relative to the conventional QPSK system over an AWGN channel. This code is also designed to reduce decoder complexity for high-speed operations. The performance of the proposed system over INTELSAT V and VI non-linear transponders was evaluated by Monte Carlo computer simulation. The 180 Mb/s 8 PSK modem, including the automatic frequency control, automatic gain control, carrier recovery and clock recovery circuits, has been implemented and tested. The complete Viterbi decoder is being implemented on five boards, and the critical add-compare-select (ACS) circuit of the high-speed Viterbi algorithm decoder is being implemented with hybrid technology employing 100-K series emitter-coupled logic dies on specially designed ceramic substrates. The ACS circuit operates at a speed exceeding 120 MHz, well over the design goal of 60 MHz. Construction of this codec is almost complete.     

Review of microwave distributed superconducting vortex-flow transistor amplifiers

The dynamics of fluxons in the vortex flow transistor (VFT) has been much studied. The fluxon transit time determines the fundamental speed limit of operation. Since fluxons can travel at the velocity of electromagnetic waves in the junction, the VFT has the potential for operating in high frequency systems ( ≈ 100 GHz). However, owing to the low input and output impedance of the VFT, use of the device in a conventional circuit would be quite limited. A distributed amplifier configuration consisting of many VFTs has been proposed to remedy the problems of low impedance levels. However, the realization of such an amplifier circuit at microwave or millimetre wave frequencies depends on obtaining a circuit model. In this paper, microwave superconducting VFT distributed amplifiers using the balanced control technique is reviewed. This kind of amplifier has the advantage that the capacitive feedthrough effect is decreased to a negligible extent. This is the major limiting factor for high frequency applications. The self-field effect which makes the current step inclined is reduced by injecting bias current only around the region of one end of the junction thus obtaining steeper I- V characteristics. With the asymmetric geometry, the slope of the current step is about one hundred times steeper than those obtained with the conventional overlap geometry. Owing to the diamagnetic behaviour of the Josephson junction, a little of the magnetic field induced by the current in the control line is allowed to penetrate the junction. Thus, the transresistance r_m of a VFT is very small. Some methods for maximizing r_m and minimizing the output impedance r₀ also appear in this review. The feasibility of fabricating VFT distributed amplifiers using low-T_c superconducting material has been demonstrated. The power gain of the amplifier can be as high as 15 dB with a flat frequency response.     

A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers

This paper presents a design for testability (DFT) technique for testing high-speed circuits with a low-speed test mode clock. With this technique, the test mode clock frequency can be reduced with virtually no lower limit. Even with the reduced speed requirement on the automatic test equipment (ATE), our method facilitates the test of the rated-speed timing and allows performance binning. A CMOS implementation of the DFT hardware with 50 ps timing accuracy is presented. To demonstrate the effectiveness of the technique we designed a 16-bit, 1.4 GHz pipelined multiplier as a test vehicle. Simulations using a test clock frequency much lower than the rated clock frequency show that delay faults of sizes as small as 50 ps are detected and that the new test technique provides correct performance binning.     

SiC衬底上栅长70 nm fT / fmax >160 GHz的InAlN/GaN HEMTs器件

在SiC衬底上制备了InAlN/GaN 高电子迁移率晶体管（HEMTs）,并进行了表征。为提高器件性能,综合采用了多种技术,包括高电子浓度,70 nm T型栅,小的欧姆接触电阻和小源漏间距。制备的InAlN/GaN器件在栅偏压为1 V时得到的最大饱和漏电流密度为1.65 A/mm,最大峰值跨导为382 mS/mm。70 nm栅长器件的电流增益截止频率fT和最大振荡频率fmax分别为162 GHz和176 GHz。     

All-N-logic high-speed true-single-phase dynamic CMOS logic

In this paper, a novel all-N-logic single-phase high speed dynamic CMOS logic is introduced and analyzed. The circuits achieve high speed by eliminating the need for the low-speed P-logic blocks. The use of all-N-logic allows the speed of the proposed circuits to be two to three times the speed of conventional CMOS dynamic circuits. An 2:1 frequency divider, using proposed ANL2 circuits, is simulated using 0.8 μm CMOS technology with the operating clock frequency reaching as high as 1.5 GHz. A pipelined 8-b carry generator of five-stacked NMOS transistors, which operates at a clock rate of over 710 MHz, has also been simulated. Experimental results show that the proposed circuits operate over 910 MHz implemented in a 1.2 μm CMOS technology     

栅长为83-nm的毫米波低噪声InP基PHEMTs的研制

本文设计并实现了一种83-nm T型栅的InP基In0.52Al0.48As/In0.65Ga0.35As赝配高电子迁移率晶体管（PHEMT）。该器件的总栅宽为2×30μm,展现了良好的DC直流、RF射频以及低噪声特性,包括最大饱和电流密度Idss和最大有效跨导gm,max分别为894mA/mm和1640mS/mm。基于1~110 GHz全频段在片测试的S参数外推获得的最大截止频率ft和最大振荡频率fmax分别为247GHz和392GHz。测得的器件拐点（稳定因子k=1）频率为102GHz,因此,基于拐点外推获得的fmax更加准确。采用冷源法完成器件的在片噪声参数的测试,测得的最小噪声系数NFmin在30GHz时为1dB,相关增益Gass为14.5dB。这些良好结果的获得是由于沟道层中InAs摩尔组分的增加,沟道层厚度的减小,栅长的缩短以及寄生效应的减小。这些优良的特性使得该器件非常适合于毫米波频段低噪声单片集成电路的应用。     

Significant Improvement of Transistor Transconductance and Speed by Using a Graded Channel

A concept for the improvement of the speed of a short-channel (L _g< 0.1–0.2 m) FET is suggested. The effect is due to alternating local regions (10–20 nm) with a high and a low electron concentration and, correspondingly, a high and a low electric field that are created in the undergate region. A periodic decrease in the electron temperature in the low-resistivity regions of the channel is thought of to improve the mobility and effective transit speed of electrons in the transistor channel. This must improve the speed response of the transistor. Transistors based on such nonuniform structures may have the cutoff frequency of 1000 GHz or even higher.     

Oscillateurs à TEC accordables par varactor dans la bande 18–40 GHz

This paper describes the design, analysis and experimental results of 18–26 GHz fundamental and 26–40 GHz doubler voltage controlled oscillator. They use field effect transistors and hyperabrupt GaAs varactor diodes. The interest of such circuits are a good integration, a high speed frequency tuning capability and a high frequency of oscillation allowing to achieve ultra wide bandVco by frequency transposition at lower frequencies.     

Fully digital fast transient phase-locked digital LDO-embedded-MDLL for DVFS applications

This paper presents a multiplying delay-locked loop (MDLL) embedded with a frequency-only reference (F_REF) based fully digital low-dropout regulator (DLDO) that outperforms conventional dynamic voltage and frequency scaling circuits when driving digital-load circuits that operate down to the near-threshold voltage level . We also propose a feed-forward acceleration (FFA) technique, which is dynamically activated only during the transient period to reduce the transient response time and voltage droop caused by the load current step. The proposed DLDO-embedded-MDLL was fabricated in a 40 nm CMOS process and occupies an active area of 0.02 mm². At the typical V_IN = 1.2 V and F_REF = 37.4 MHz, the regulated range of voltage was measured to be 0.56–1.16 V while the frequency being scaled from 0.411 to 2.35 GHz. With the proposed FFA technique, the load transient response and voltage droop were reduced by 61.5 and 35%, respectively, compared to the values during normal loop operation. In addition, the measured phase noise at 0.411 and 2.35 GHz was less than ?116 and ?104 dBc/Hz, respectively, both at 1 MHz offset.     

用于高速GaAs IC在片检测的电光取样系统

目前直接电光取样技术是在片检测砷化镓高速集成电路内部动态特性的最好方法。我们建立了半导体激光器电光取样系统，测试了梳状信号发生器输出的４３．７ｐｓ的电脉冲信号以及频率５ＧＨｚ的微波信号，并测试了频率３ＧＨｚ的微波信号的位相移动或时间延迟以及铁氧体微波移相器的静态特性曲线，这个系统将被应用于砷化镓高速集成电路内部动态特性在片检测。     

Sub-20 ps ECL circuits with high-performance super self-alignedselectively grown SiGe base (SSSB) bipolar transistors

This paper describes a high maximum frequency of oscillation f_max self-aligned SiGe-base bipolar transistor technology, based on a self-aligned selective epitaxial growth (SEG) technology including graded Ge profile in an intrinsic base and link-base engineering using a borosilicate glass (BSG) sidewall structure. The transistor is a new self-aligned transistor, which we call a Super Self-aligned Selectively grown SiGe Base (SSSB) bipolar transistor. The 1st step of the annealing (800°C, 10 min) was performed for the diffusion of boron from the BSG film, before the deposition of an emitter polysilicon film. The 2nd step of the annealing (950°C, 10 sec) of emitter drive-in was carried out, which enabled us to obtain sufficient current gain using in-situ phosphorus doped polysilicon as an emitter electrode. Sheet resistance for a link-region more than one order lower than that of the epitaxial intrinsic base was obtained after heat treatment. Base profile (boron and Ge) design, and the 2-step annealing technique have realized cut-off frequency f_T of 51 GHz and f_max of 50 GHz. ECL circuits of 19-psec gate delay have been achieved     

65nm工艺下20Gb/s无电感限幅放大器设计与分析

本文设计了一款能工作在20Gb/s速率下的无电感限幅放大器。限幅放大器包括三各部分：带直流失调消除的输入匹配级,增益级和输出驱动级。本设计采用交叉负反馈技术,使得放大器在获得高带宽的同时拥有较为平坦的频率响应。直流失调消除环路中增加了误差放大器来保证直流失调消除效果。放大器在65纳米工艺下成功流片,芯片面积为0.45 × 0.25平方毫米（不包括PAD）,测试结果显示放大器的差分增益为37dB,带宽为16.5GHz,在高达26.5GHz的频率内Sdd11和Sdd22分别小于-16dB和-9dB。除了驱动级,整个放大器在1.2V的电源电压下消耗50mA的电流。     

一种降低高速三维互连芯片层间信号反射的方法

In high speed three-dimensional integrated circuits （3D ICs）, through silicon via （TSV） insertion causes impedance discontinuities along the interconnect-TSV channel that results in signal reflection. As demonstrated for a two-plane interconnect structure connected by a TSV, we incorporate an appropriate capacitance at the junction to mitigate the signal reflection with gigascale frequencies. Based on 65 nm technology and S-parameter analysis, the decrease of signal reflection can be 189% at the tuned frequency of 5 GHz. Extending this method to the five-plane interconnect structure further, the reduction of signal reflection can achieve 400%. So we could broaden this method to any multilevel 3D interconnect structures. This method can also be applied to a circuit with tunable operating frequencies by digitally connecting the corresponding matching capacitance into the circuit through switches. There are remarkable improvements of the quality of the transmitting signals.     

Fault diagnosis under a limited-fault assumption and limited test-point availability

This paper describes a method of fault diagnosis for large interconnected circuits in which the number of faults is limited to, say,n _f where it is possible thatn _f exceeds the number of output measurements,n _o. The problem and its solution are formulated in the context of a frequency domain tableau based on the component connection model of a circuit/system. The paper describes Jacobian tests for diagnosability whenn _fn _o and states a full parameter diagnosability test as a corollary to the main theorem. An algorithm is developed for the identification of faulty parameters in this limited fault case. Finally, examples, including a 26-parameter video-amplifier circuit, illustrating the technique are given.     

Half-Rate Duobinary Transmitter Architecture for Chip-to-Chip Interconnect Applications

For a high speed duobinary transmitter clock frequency defines the transmission limit. A conventional duobinary transmitter needs a clock frequency equal to the data rate. In this work we propose a duobinary transmitter that uses a clock frequency half of the output data rate and hence achieves double the transmission rate for a given clock frequency as compared to a conventional duobinary transmitter. In the proposed transmitter the duobinary precoder is integrated into the last stage of a tree structured serializer to combine two NRZ data streams at half the transmission data rate. Two modes for the precoder have been incorporated into the design. The first mode is applicable for data transmission over copper whereas the second mode is suitable for wavelength division multiplexed optical transmission. A DLL based clock multiplier unit is employed to produce the high frequency clock with 50% duty cycle needed for the precoding operation. It incorporates a clock generation logic with integrated duty cycle control. A charge pump with dynamic current matching and a high resolution PFD are employed to reduce static phase error in locking and hence achieves improved jitter performance. A new delay cell along with automatic mode selection is proposed. To cover a wide range of data rate, the DLL is designed for a wide locking range and maintains almost 50% duty cycle. The design is implemented in 1.8-V, 0.18 μm Digital CMOS technology with an f _T of 27 GHz. Simulations shows that, the duobinary transmitter circuit works up-to 10 Gb/s and consumes 60 mW of power.     

一种宽带的InGaP/GaAs HBT 再生频率分频器

A dynamic divide-by-two regenerative GaP/GaAs heterojunction bipolar transistors （HBTs） frequency divider （RFD） is presented in a 60-GHz-fT Intechnology. To achieve high operation bandwidth, active loads instead of resistor loads are incorporated into the RFD. On-wafer measurement shows that the divider is operating from 10 GHz up to at least 40 GHz, limited by the available input frequency. The maximum operation frequency of the divider is found to be much higher than fT/2 of the transistor, and also the divider has excellent input sensitivity. The divider consumes 300.85 mW from 5 V supply and occupies an area of 0.47 × 0.22 mm^2.     

A 5.4-GHz high-<Emphasis Type="Italic">Q</Emphasis> tunable active-inductor bandpass filter in standard digital CMOS technology

A transistor-only CMOS active-inductor with an all-NMOS signal path is presented. By tuning the varactor-augmented parasitic capacitance at the only internal node the circuit losses from submicron MOSFETs can be partially or fully compensated to permit realizing unlimited values of Q, with little frequency and no power-consumption penalties. Transistor-only second-order bandpass filters using the active inductor were built in the TSMC 0.18-μm CMOS process, and high filter Q was obtained by tuning the varactor. The highest center frequency measured was f ₀ = 5.7 GHz for 0.2-μm gate lengths and the maximum repeatably measured Q was 665. Lower Qs can be obtained by reducing the capacitive compensation or by adjusting the circuit biasing. f ₀ and Q are tunable via separate varactors. IIP ₃ and input 1-dB compression point were simulated as 0.523 V_PP and 0.128 V_PP (−1.65 and −13.9 dBm from a 50-Ω source) at 5.7 GHz with Q = 100 and midband gain equal 4.7 dB. For the same conditions, the output noise and noise figure (R _S = 50 kΩ) were simulated to be 0.8 μV/Hz^1/2 and 25.6 dB, respectively. The filter core occupies an area of 26.6 μm × 30 μm and dissipates 4.4 mW at 5.4 GHz from a 1.8-V power supply. As the circuits use only MOSFETs they are fully compatible with standard digital CMOS processes. f ₀ statistics were obtained by measuring 40 chips at identical biasing condition.     

栅槽横向宽度对InAlAs/InGaAs HEMTsDC及RF特性的影响

我们制造出了栅长为88 nm的InP基InAlAs/InGaAs 高电子迁移率器件(HEMTs),该器件的频率特性为ft = 100 GHz, fmax = 185 GHz。本文对横向栅槽宽度分别为300 nm, 412 nm, 1070 nm的器件进行了实验。借助能带图的方式,定性分析了横向栅宽的增加会因为表面态和碰撞电离的作用,使得器件直流特性表现出kink效应,并得到减小横向栅槽宽度能减弱kink效应的结论,文中还讨论了横向栅槽宽度通过改变器件寄生电容及其源漏电阻,从而对频率特性产生影响。这些分析对制造出更高性能的HEMT器件有比较重要的意义。