一种具有高线性度MOS采样开关的采样保持电路

通过采样保持电路中运放的复用,提出了一种具有高线性度MOS采样开关的模数转换器前端采样保持电路结构。这种结构可以显著降低采样开关导通电阻变化引入的非线性,从而在不增加开关面积和功耗的情况下,实现了高性能的采样保持电路。基于0.13?m的标准CMOS工艺,对提出的采样保持电路进行了仿真。在采样时钟频率为100MHz,输入信号频率1MHz时,仿真结果显示,无杂散动态范围(SFDR)达到了116.6dB,总谐波失真(THD)达到了112.7dB,信号谐波噪声比（SNDR）达到103.7dB,可以满足14比特流水线ADC对采样保持电路的要求。     

用于CMOS图像传感器内置流水线ADC的采样/保持电路

设计了用于CMOS图像传感器内置流水线ADC的采样/保持电路,该电路具有10位采样精度和50 MHz采样速率,采用开关电容电荷重分布式结构,加入图像传感器的黑光校准功能。放大器采用全差分套筒式共源共栅增益增强型结构,保证了所需的增益和带宽。电路采用0.18μmCMOS工艺实现。HSPICE仿真结果表明,电路可在5 ns内达到0.05%的精度;对于24.0218 MHz、±0.5 V摆幅的正弦输入信号,SNDR和SFDR分别达到62.47 dB和63.73 dB,满足系统要求。     

一种10位80 MS/s低功耗采样保持电路的设计

给出了一种基于开关电容(SC)电路的10位80 MHz采样频率低功耗采样保持电路。它是为一个10位80 MS/s流水线结构A/D转换器的前端采样模块设计的。在TSMC 0.25μmCMOS工艺,2.5 V电源电压下,该电路的采样频率为80 MHz;在奈奎斯特频率采样时,无杂散动态范围(SFDR)为75.4 dB,SNDR为71.8 dB,ENOB为11.6,输入信号范围可达160 MHz(两倍采样频率),此时SFDR仍大于70 dB。该电路功耗为16.8 mW。     

一种用于高速高精度A/D转换器的自举采样电路

介绍了一种新型的CMOS自举采样电路。该电路适用于12位100 MHz采样频率的A/D转换器。采用P型栅压自举开关补偿技术,可以有效地克服采样管导通电阻变化引入的非线性失真,提高采样精度。仿真结果表明,采样时钟频率为100 MHz时,输入10 MHz信号,可得信噪失真比(SNDR)为102 dB,无杂散动态范围(SFDR)为103 dB。信号频率达到采样频率时,仍有超过85 dB的SNDR和87 dB的SFDR,满足高速高精度流水线A/D转换器对采样开关线性度和输入带宽的要求。电路采用SMIC 0.18μm CMOS数模混合工艺库实现,电源电压为1.8 V。     

一种14位125MHz采样/保持电路的设计

设计了一种高性能采样/保持(S/H)电路,采用全差分电容翻转型的主体结构,有效减小了噪声和功耗.在电路设计中,采用栅压自举开关,极大地减小了非线性失真,同时,有效地抑制了输入信号的直流偏移.采样/保持放大器电路采用折叠共源共栅结构,由于深亚微米工艺中器件本征增益减小,S/H电路为达到更高增益,采用增益提升技术.设计的采样/保持电路采用0.18μm1P5M工艺实现,在1.8V电源电压、125 MHz采样速率下,输出差动摆幅达到2 V(VP-P),输入信号到奈奎斯特频率时仍能达到98 dB以上的无杂散动态范围(SFDR),其性能满足14位精度、125MHz转换速率的流水线ADC要求.     

两倍增益10位100 MSPS CMOS采样/保持电路

提出了一种两倍增益高线性、高速、高精度采样/保持电路。该采样/保持电路通过对输入信号实现两倍放大,改善了高频非线性失真;一种新型的消除衬底偏置效应的采样开关,有效地提高了采样的线性度;高增益和宽带宽的折叠共源共栅运算放大器保证了采样/保持电路的精度和速度。整个电路以0.35μm AMS Si CMOS模型库验证。模拟结果显示,在输入信号为49.21875MHz正弦波,采样频率为100 MHz时,增益误差为70.9μV,SFDR可达到84.5 dB。     

用于流水线ADC的高精度SHA-Less电路

本文提出了一种适用于高速、高精度流水线ADC的无采样保持运算放大器(SHA-less)结构。使用可变电阻带宽修调电路以及MDAC与flash ADC的对称性设计,减少了两种单元电路间的采样误差,通过增加MDAC采样电容复位时钟和独立的flash ADC采样电容技术,消除了采样电容残留电荷引起的踢回噪声。本设计作为14位125-MS/s流水线ADC的前端转换级,基于ASMC 0.35- BiCMOS工艺的仿真和测试结果表明,前端转换级芯片面积1.4?2.9 mm2,使用带宽修调后,125 MHz采样,30.8 MHz输入信号下,SNR从63.8 dB提高到70.6 dB,SFDR从72.5 dB提高到81.3 dB,转换器的动态性能在150 MHz的输入信号频率下无明显下降。     

窄带Dither技术在流水线ADC中的校正研究

随着工艺和技术的不断发展,对ADC的无杂散动态范围(SFDR)的要求越来越高。提出了一种窄带Dither技术来改善流水线ADC的SFDR。介绍了Dither的原理和产生电路。基于TSMC 90 nm CMOS工艺,设计了一种12位100 MS/s ADC。在该ADC中运用了Dither技术,并对Dither技术的运用效果进行了仿真与验证。结果表明,当输入信号幅度为63.25 mV、频率为9.325 MHz、采样频率为50 MHz时,该ADC的SFDR为77.97 dB。采用Dither技术后,在保证SNR几乎不变的情况下,SFDR可达84.79 dB,较不采用Dither技术提高了6.82 dB。     

一种高性能CMOS采样/保持电路

介绍了一种高性能CMOS采样/保持电路.该电路在3 V电源电压下,60 MHz采样频率时,输入直到奈奎斯特频率仍能够达到90 dB的最大信号谐波比(SFDR)和80 dB的信噪比(SNR).电路采用全差分结构、底板采样、开关栅电压自举(bootstrap)和高性能的增益自举运算放大器.采用0.18 μm CMOS工艺库,对电路进行了Hspice仿真验证.结果表明,整个电路消耗静态电流5.8 mA.     

基于0.35 μm GeSi-BiCMOS工艺的1 GSPS采样保持电路

介绍了一种基于0.35μmGeSi-BiCMOS工艺的1GSPS采样/保持电路。该电路采用全差分开环结构,使用局部反馈提高开环缓冲放大器的线性度;采用增益、失调数字校正电路补偿高频输入信号衰减和工艺匹配误差造成的失调。在1GS/s采样率、484.375MHz输入信号频率、3.3V电源电压下进行仿真。结果显示,电路的SFDR达到75.6dB,THD为-74.9dB,功耗87mW。将该采样/保持电路用于一个8位1GSPSA/D转换器。流片测试结果表明,在1GSPS采样率,240.123MHz和5.123MHz输入信号下,8位A/D转换器的SNR为41.39dB和43.19dB。     

一种10位50MHz流水线模数转换器的设计

采用每级1.5 bit和每级2.5 bit相结合的方法设计了一种10位50 MHz流水线模数转换器。通过采用自举开关和增益自举技术的折叠式共源共栅运算放大器,保证了采样保持电路和级电路的性能。该电路采用华润上华(CSMC)0.5μm 5 V CMOS工艺进行版图设计和流片验证,芯片面积为5.5 mm2。测试结果表明:该模数转换器在采样频率为50 MHz,输入信号频率为30 kHz时,信号加谐波失真比(SNDR)为56.5 dB,无杂散动态范围(SFDR)为73.9 dB。输入频率为20 MHz时,信号加谐波失真比为52.1 dB,无杂散动态范围为65.7 dB。     

低功耗10位100MHz流水线A/D转换器设计

介绍了一个10位100 MHz,1.8 V的流水线结构模/数转换器（ADC）,该ADC运用相邻级运算放大器共享技术和逐级电容缩减技术,可以大大减小芯片的功耗和面积。电路采用级联1个高性能前置采样保持单元和4个运放共享的1.5位/级MDAC,并采用栅压自举开关和动态比较器来缩减功耗。结果显示,在输入频率达到奈奎斯特频率范围内,整个ADC的有效位数始终高于9位。电路使用TSMC 0.18μm 1P6 M CMOS工艺,在100 MHz的采样频率下,功耗仅为45 mW。     

A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback

A new capacitor and opamp sharing technique that enables a very efficient low-power pipeline ADC design is proposed. A new method to cancel the effect of signal-dependent kick-back or memory effect in capacitors in the absence of a sample and hold is also presented. Fabricated in a 0.18 $mu{rm m}$ CMOS process, the prototype 11-bit pipelined ADC occupies 2.2 ${rm mm}^{2}$ of active die area and achieves 66.7 dB SFDR and 53.2 dB SNDR when a 1 MHz input signal is digitized at 80 MS/s. The SFDR and SNDR are unchanged for a 50 MHz input signal. The prototype ADC consumes 36 mW at 1.8 V supply, of which the analog portion consumes 24 mW.      

A low power 12-b 40-MS/s pipeline ADC

This paper describes a 12-bit, 40-MS/s pipelined A/D converter (ADC) which is implemented in 0.18-μm CMOS process drawing 76-mW power from 3.3-V supply. Multi-bit architectures as well as telescopic operational transconductance amplifiers (OTAs) are adopted in all pipeline stages for good power efficiency. In the first two stages,particularly, 3-bit/stage architectures are used to improve the ADC's linearity performance. The ADC is calibration-free and achieves a DNL of less than 0.51 LSB and an INL of less than 1 LSB. The SNDR performance is above 67 dB below Nyquist. The 80-dB SFDR performance is maintained within 1 dB for input frequencies up to 49 MHz at full sampling rate.     

A 10-b 20-Msample/s low-power CMOS ADC

A single-ended input but internally differential 10 b, 20 Msample/s pipelined analog-to-digital converter (ADC) is demonstrated with 4 mW per stage using a single 5 V supply. The prototype ADC made of an input sample and hold (S/H) plus 8 identical unscaled pipelined stages consumes 50 mW including power consumed by a bias generator and two internal buffer amplifiers driving common-mode bias lines. Key circuits developed for this low-power ADC are a dynamic comparator with a capacitive reference voltage divider that consumes no static power, a source-follower buffered op amp that achieves wide bandwidth using large input devices, and a self-biased cascode biasing circuit that tracks power supply variation. The ADC implemented using a double-poly 1.2 μm CMOS technology exhibits a DNL of ±0.65 LSB and a SNDR of 54 dB while sampling at 20 MHz. The chip die area is 13 mm²     

A power-efficient 10-bit 40-MS/s sub-sampling pipelined CMOS analog-to-digital converter

This paper presents a 10-bit 40-MS/s pipelined analog-to-digital converter (ADC) in a 0.13-μm CMOS process for subsampling applications. A simplified opamp-sharing scheme between two successive pipelined stages is proposed to reduce the power consumption. For subsampling, a cost-effective fast input-tracking switch with high linearity is introduced to sample the input signal up to 75 MHz. A two-stage amplifier with hybrid frequency compensation is developed to achieve both high bandwidth and large swing with low power dissipation. The measured result shows that the ADC achieves over 77 dB spurious free dynamic range (SFDR) and 57.3 dB signal-to-noise-plus-distortion ratio (SNDR) within the first Nyquist zone and maintains over 70 dB SFDR and 55.3 dB SNDR for input signal up to 75 MHz. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.2 LSB and ±0.3 LSB, respectively. The ADC consumes 15.6 mW at the sampling rate of 40 MHz from a 1.2-V supply voltage, and achieves a figure-of-merit (FOM) value of 0.22 pJ per conversion step.     

A 12-bit 40 MS/s pipelined ADC with over 80 dB SFDR

This paper describes a 12-bit 40 MS/s calibration-free pipelined analog-to-digital converter (ADC), which is optimized for high spurious flee dynamic range (SFDR) performance and low power dissipation. With a 4.9 MHz sine wave input, the prototype ADC implemented in a 0.18-μm 1P6M CMOS process shows measured differential nonlinearity and integral nonlinearity within 0.78 and 1.32 least significant bits at the 12-bit level without any trimming or calibration. The ADC, with a total die area of 3. 1 × 2.1 mm~2, demonstrates a maximum signal-to-noise distortion ratio (SNDR) and SFDR of 66.32 and 83.38 dB, respectively, at a 4.9 MHz analog input and a power consumption of 102 mW from a 1.8 V supply.     

A 3 V Wideband CMOS Switched-Current A/D-Converter Suitable for Time-Interleaved Operation

The simulated and measured performance of an experimental 10-b wideband CMOS A/D converter design is presented. Fully-differential first-generation switched-current circuits with common-mode feedforward were used to implement a 1.5-b/stage pipelined architecture in order to evaluate the switched-current technique for digital radio applications. With f _in = 1.83, the measured spurious-free dynamic range (SFDR) is 60.3 dB and the signal-to-noise-and-distortion ratio (SNDR) = 46.5dB at 3 MS/s. Although this 3 V design was fabricated in a standard digital 5 V, 0.8 m CMOS process, a high bandwidth was achieved. Since the ADC maintains an SNDR 40 dB for input frequencies of more than 20 MHz, it has the highest input bandwidth reported for any CMOS switched-current A/D-converter implementation. Its sample rate can be increased by parallel, time-interleaved, operation. Measurement results are compared with the measured performance of other wideband switched-current A/D converters and found to be competitive also with respect to area and power efficiency.     

A High Performance Track and Hold Circuit for High-Resolution High-Speed ADC

Design of a high performance track and hold (T/H) circuit for high-resolution high-speed analog-to-digital converter (ADC) is presented,which has been implemented in 0.18 μm CMOS process.An improved bootstrapped and bulk-switching technique is introduced to greatly minimize the nonlinearity of sampling network over a wide bandwidth,and the addition of a modified pre-charge circuit helps reducing the total power consumption.The experimental results show that the proposed T/H circuit achieves over 77 dB SFDR (spurious-free dynamic range) and 70 dB THD (total harmonic distortion) at 100 MHz sampling rate and maintains the performance with input frequency up to 305 MHz while consuming 47 mW power.     

A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer

A 12-bit 30 MSPS pipeline analog-to-digital converter(ADC) implemented in 0.13-μm 1P8M CMOS technology is presented.Low power design with the front-end sample-and-hold amplifier removed is proposed.Except for the first stage,two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption.The ADC presents 65.3 dB SNR,75.8 dB SFDR and 64.6 dB SNDR at 5 MHz analog input with 30.7 MHz sampling rate.The chip dissipates 33.6 mW from 1.2 V power supply.FOM is 0.79 pJ/conv step.