Adaptive-Quantization Digital Image Sensor for Low-Power Image Compression

The recent emergence of new applications in the area of wireless video sensor network and ultra-low-power biomedical applications (such as the wireless camera pill) have created new design challenges and frontiers requiring extensive research work. In such applications, it is often required to capture a large amount of data and process them in real time while the hardware is constrained to take very little physical space and to consume very little power. This is only possible using custom single-chip solutions integrating image sensor and hardware-friendly image compression algorithms. This paper proposes an adaptive quantization scheme based on boundary adaptation procedure followed by an online quadrant tree decomposition processing enabling low power and yet robust and compact image compression processor integrated together with a digital CMOS image sensor. The image sensor chip has been implemented using 0.35-mum CMOS technology and operates at 3.3 V. Simulation and experimental results show compression figures corresponding to 0.6-0.8 bit per pixel, while maintaining reasonable peak signal-to-noise ratio levels and very low operating power consumption. In addition, the proposed compression processor is expected to benefit significantly from higher resolution and Megapixels CMOS imaging technology     

桥梁结构健康监控的无线传感网络系统设计

介绍了基于ZIGBEE技术标准的无线传感网络的桥梁结构监控系统,分别从硬件模块和软件架构两方面进行设计。无线模块采用的是Chipcon公司的CC2430芯片,它是第一颗真正的系统芯片(SoC)CMOS解决方案;数据处理模块采用具有高速计算能力低功耗TI公司的TS320C5509A。实验表明该设计具有低成本,低功耗,高可靠性,高安全性等特点,因此在桥梁等大型建筑结构健康监控方面具有突出的优势。     

A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks

A fully CMOS integrated RF transceiver for ubiquitous sensor networks in sub-gigahertz industrial, scientific, and medical (ISM)-band applications is implemented and measured. The integrated circuit is fabricated in 0.18-mum CMOS technology and packaged in leadless plastic chip carrier (LPCC) package. The fully monolithic transceiver consists of a receiver, a transmitter, and an RF synthesizer with on-chip voltage-controlled oscillator. The chip fully complies with the IEEE 802.15.4 wireless personal area network in sub-gigahertz mode. The cascaded noise figure of the overall receiver is 9.5 dB and the overall transmitter achieves less than 6.3% error vector magnitude for 40 kb/s mode. The chip uses 1.8-V power supply and the power consumption is 25 mW for reception mode and 29 mW for transmission mode     

A 90 nm All-digital Smart Temperature Sensor with Wireless Body Area Network Baseband Transceiver for Biotelemetry Applications

This work provides an all-digital smart temperature sensor with dual-mode transceiver chipset for wireless body area network (WBAN). The measurement results show that the proposed temperature sensor achieves a maximum temperature error < 0.6oC within the range from 20oC to 50oC. And a phase-frequency tunable clock generator (PFTCG) is designed with frequency and phase tuning capability on the fly. This chip is manufactured on a standard 90 nm CMOS process. The supply voltage to the chip core is globally applied at 0.5 V with 12 power-domain partitions for sleep-active and voltage-scaling management. The transceiver chipset provides maximum 7 Mbps data rate, resulting in 97.7% efficiency improvement in baseband circuit processing.     

Analog ASIC for improved temperature drift compensation of a high sensitive porous silicon pressure sensor

The paper focuses on the design of a CMOS analog ASIC for temperature-drift compensation of a high sensitivity piezoresistive micro-machined porous silicon pressure sensor to avoid analog-to-digital conversion, limit chip area and reduce power consumption. For implementing the compensation circuitry, multilayered perceptron (MLP) based artificial neural network (ANN) with inverse delayed function model of neuron has been optimized. The temperature drift compensation CMOS ASIC has been implemented to make porous silicon pressure sensor an excellent SMART porous silicon pressure sensor. Using the compensation circuit, the error in temperature-drift has been minimized from 93% to about 0.5% as compared to 3% using conventional neuron model in the temperature range of 25–80°C. The entire circuit has been designed using 0.35 μm AMS technology model and simulated using mentor graphics ELDO Simulator.     

一种基于0.18μm CMOS工艺的智能传感器网络节点设计与实现

针对当前无线监测网络节点存在无线通信距离小、数据传输周期短等问题,设计并实现了一种基于0.18 μm CMOS工艺的智能传感器网络节点.该无线传感器网络节点由无线传感器模块、CC2430处理器模块、无线通信模块以及电源模块构成.其中,CC2430处理器模块采用0.18 μm CMOS工艺控制电流损耗和模式变换时间,提高电源的运行周期,并采用0.18 μm CMOS工艺中低噪声放大器和UQ下变频对天线采集的射频信号进行操作,获取2.4 GHz的数据扩频,增强CC2420的无线通信抗干扰性能.设计了无线传感器网络节点中的SHTIO温湿度传感器、MS5534B集成压阻式压力传感器和ADXL202E双轴加速度传感器,并给出节点软件的结构和主程序流程.实验检测结果表明,设计的无线传感器网络具备较优的运行性能,丢包率较低,通信距离与运行周期明显优于传统方法.     

CMOS-based colour-change pH measurement system

A real-time pH detection and monitoring sensor system using a novel design neuromorphic CMOS optical sensor chip is presented. The system uses Bogen's universal indicator solution combined with a white light source and the CMOS optical sensor chip to measure pH as a function of colour change in a sample. Bogen's universal indicator solution causes a colour change in a sample according to the pH of the sample. The output voltage from the colour-sensitive CMOS photodetector circuit on the chip is proportional to the pH of the sample. Experimental results show that this sensor system can determine the pH of a sample from pH 1 to 9 in real-time. The sensor chip is implemented in AMI 1.5 mum CMOS technology available through MOSIS.     

A WiSN node SoC with real-time image compressor and IEEE 802.15.4 MAC accelerator

This article presents a wireless image sensor node SoC (system-on-a-chip) for low-power wireless image sensor network (WiSN), in which camera chip interface, high-quality image compression and IEEE 802.15.4 compliant acceleration modules are integrated on chip. The proposed SoC contains a hardware-implemented real-time lossless JPEG (JPEG-LS) compression engine for Bayer Color Filter Arrays (Bayer CFA), reaching a 3.5 bits/pixel with peak signal to noise ratio (PSNR) greater than 46.3 dB and achieving a maximum 5 frames/s @16 MHz for VGA (640 × 480) colour images. The proposed hardware accelerator for IEEE 802.15.4 media access control (MAC) layer covers crucial protocol defined functions and algorithms, and reduces 45% software code in the host processor. This SoC has been fabricated in UMC 0.18 µm 1P6M CMOS process. The average power of the prototype chip is 18.2 mW at 3.0 V power supply and 16 MHz clock rate.     

Silicon Carbide-Based Remote Wireless Optical Pressure Sensor

Proposed is a silicon carbide (SiC) weak-lensing-effect-based wireless optical sensor that allows safe, repeatable, and accurate pressure measurement suitable for harsh environments. This completely passive front-end sensor design uses a remoted free-space optical beam that targets a single crystal SiC chip fitted as an optical window within a pressure capsule. With increasing differential capsule pressure, the SiC chip forms a weak convex mirror with a changing focal length. By monitoring the chip reflected light beam magnification, pressure in the capsule is determined. Using a 633-nm wavelength laser beam, the proposed sensor is experimentally tested at room temperature for 0- to 600-psi (0-41atm) differential pressures and a remoting distance of 2.5 m     

A dual mode UHF EPC Gen 2 RFID tag in 0.18 μm CMOS

A dual mode UHF RFID transponder in 0.18 μm CMOS conforming to the EPC Gen 2 standard is presented. Low voltage design of the analog and digital blocks enables the chip to operate with a 1 V regulated voltage and thus to reduce the power consumption. The novel dual mode architecture enables the chip to work in passive and battery-assisted modes controlled by the reader. A custom Gen 2 based command switches the operation mode of the circuit. By using a special clock calibration method the chip operates from 1.2 to 5 MHz clock frequency. Several low power techniques are employed to reduce the power consumption of the chip which is essential in passive RFID tags. Measurement results show that the chip consumes 12 μW at 1 V supply voltage when it communicates with the reader. The chip is fabricated in 0.18 μm standard CMOS technology and occupies 0.95 mm² die area.     

基于嵌入式的ZigBee无线条码扫描仪系统的设计

通过对传统条码扫描仪的改造,设计一种ZIGBEE无线通信技术的条码扫描仪.测量系统由CMOS图像传感器和嵌入式S3C2410处理器构成.利用ZIGBEE无线节点传输的方式,代替传统的有线和无线芯片传输技术,保证了条码图像数据准确可靠的传输.并通过嵌入式操作系统LINUX在MCU上的移植,成功地构建了一个实用的无线条码扫描多任务实时系统.系统在空阔地,每个ZIGBEE节点可以实现可靠传输50m.     

一种具有高填充因数和动态数字双采样技术的CMOS图像传感器

介绍了基于0.35μm工艺设计的单片CMOS图像传感器芯片.该芯片采用有源像素结构,像素单元填充因数可达到43%,高于通常APS结构像素单元30%的指标.此外还设计了一种数字动态双采样技术,相对于传统的双采样技术(固定模式噪声约为0.5%),数字动态双采样技术具有更简洁的电路结构和更好抑制FPN噪声的效果.传感器芯片通过MPW计划采用Chartered 0.35μm数模混合工艺实现.实验结果表明芯片工作良好,图像固定模式噪声约为0.17%.     

A CMOS low-noise and low-power charge sampling integrated circuitfor capacitive detector/sensor interfaces

This paper describes the design and experimental results of a multichannel calibrationless charge sampling integrated circuit for capacitive detector/sensor interfaces. The integrated circuit incorporates multiple channels of sensitive charge preamplifiers, current/charge-mode amplifiers, pipelined analog storage cells, A/D converters, and static CMOS digital control circuitry. It is implemented in a 1.2 μm single-poly double-metal CMOS p-well technology. The power dissipation is 1 mW/channel. The input-referred equivalent noise charge (ENC) for a detector/sensor source capacitance of 30 pF and an integration time window of 128 ns is 1800 rms electrons. The input-referred channel-to-channel offset variation from chip to chip is only 292 rms electrons while the storage-cell-to-storage-cell offset variation is 142 rms electrons. The channel-to-channel gain variation from chip to chip is 1.6%     

A 5.2 mW Self-Configured Wearable Body Sensor Network Controller and a 12 $mu$ W Wirelessly Powered Sensor for a Continuous Health Monitoring System

A self-configured body sensor network controller and a high efficiency wirelessly powered sensor are presented for a wearable, continuous health monitoring system. The sensor chip harvests its power from the surrounding health monitoring band using an Adaptive Threshold Rectifier (ATR) with 54.9% efficiency, and it consumes 12 ?W to implement an electrocardiogram (ECG) analog front-end and an ADC. The ATR is implemented with a standard CMOS process for low cost. The adhesive bandage type sensor patch is composed of the sensor chip, a Planar-Fashionable Circuit Board (P-FCB) inductor, and a pair of dry P-FCB electrodes. The dry P-FCB electrodes enable long term monitoring without skin irritation. The network controller automatically locates the sensor position, configures the sensor type (self-configuration), wirelessly provides power to the configured sensors, and transacts data with only the selected sensors while dissipating 5.2 mW at a single 1.8 V supply. Both the sensor and the health monitoring band are implemented using P-FCB for enhanced wearability and for lower production cost. The sensor chip and the network controller chip occupy 4.8 mm² and 15.0 mm², respectively, including pads, in standard 0.18 ?m 1P6M CMOS technology.     

A High Dynamic Range CMOS Image Sensor With Inpixel Light-to-Frequency Conversion

A high dynamic range CMOS image sensor with inpixel light-to-frequency conversion has been designed. The prototype chip was fabricated in a standard 0.18-mum single-poly six-metal CMOS technology. The experimental results show that, operating at 1.2 V, the sensor can achieve a linear dynamic range of over 115 dB and an overall dynamic range of over 130 dB     

无源射频电子标签模拟前端的设计与分析

提出了与ISO/IEC 18000-3兼容的高频无源射频电子标签模拟前端.分析了设计中的考虑因素,尤其是射频电子标签的能量传输.基于这些分析,提出了一种新架构、高能量转换效率、低电压、低功耗、在噪声和能量波动环境下具有高性能的模拟前端.此电路在Chartered 0.35μm标准CMOS工艺下实现,测试结果表明芯片能很好地满足设计要求.     

Research on Column FPN and Black Level Calibration in Large Array CMOS Image Sensor

A technical investigation, research and im-plementation is presented to correct column fixed pattern noise and black level in large array Complementary metal oxide semiconductor (CMOS) image sensor. Through making a comparison among reported solution, and give large array CMOS image sensor design and considerations, according to our previous analysis on non-ideal factor and error source of piecewise Digital to analog converter (DAC) in multi-channels, an improving accurate piecewise DAC with adaptive switch technique is developed. The research theory has verified by a high dynamic range and low column Fixed pattern noise (FPN) CMOS image sensor prototype chip, which consisting of 8320×8320 pixel array was designed and fabricated in 55nm CMOS 1P4M standard process. The chip active area is 48mm×48mm with a pixel size of 5.7μm×5.7μm. The measured results achieved a high intrinsic dynamic range of 75dB, a low FPN and black level of 0.06％, a low photo response non-uniformity of 1.5％ respectively, and an excellent raw sample image taken by the prototype sensor.     

Detection system based on a novel large area hybrid detector

A system level implementation of a large area hybrid detector is presented. The detector used in this system consists of an array of hydrogenated amorphous silicon photodiodes directly connected to a CMOS readout chip, which is vertically integrated over the sensor array using flip-chip bonding. In particular, the proposed solution relies on a stack of interconnection layers, deposited on top of the photodiode array, to route each individual pixel output to a separate pre-amplifier channel. This avoids the need for a geometrical matching between the sensor array and the chip contact pads. As a consequence, conventional non-pixelated readout chip can be used and easy-scalable large area detectors can be produced. The CMOS chip is connected to an electronic board, providing the interfaces needed to read the signals as well as providing voltage references and power to the chip. The signals are collected and pre-processed by an FPGA chip, providing a very compact and flexible setup.     

A concurrent error detection IC in 2-μm static CMOS logic

When a comprehensive fault model is considered, static CMOS VLSI has long been prohibited from realizing concurrent error detecting (CED) circuits due to the unique analog faults (bridging and stuck-on faults). In this paper, we present the design, fabrication and testing of an experimental chip containing the integration of a totally self-checking (TSC) Berger code checker and a strongly code disjoint (SCD) built-in current sensor (BICS). This chip was fabricated by MOSIS using 2 μm p-well CMOS technology. In chip tests, all implanted faults, including analog faults, were detected as expected. We also show that the self-exercising mechanism of the SCD BICS is indeed functioning properly. This is the first demonstration of a working static CMOS CED chip     

Inverse Synthetic Aperture Secondary Radar Concept for Precise Wireless Positioning

In this paper, the novel inverse synthetic aperture secondary radar wireless positioning technique is introduced. The proposed concept allows for a precise spatial localization of a backscatter transponder even in dense multipath environments. A novel secondary radar signal evaluation concept compensates for the unknown modulation phase of the returned signal and thus leads to radar signals comparable to common primary radar. With use of this concept, inverse synthetic aperture radar algorithms can be applied to the signals of backscatter transponder systems. In simulations and first experiments, we used a broadband holographic reconstruction principle to realize the inverse synthetic aperture approach. The movement of the transponder along a short arbitrary aperture path is determined with assisting relative sensors (dead reckoning or inertia sensors). A set of signals measured along the aperture is adaptively focused to the transponder position. By this focusing technique, multipath reflections can be suppressed impressively and a precise indoor positioning becomes feasible. With our technique, completely new and powerful options for integrated navigation and sensor fusion in RF identification systems and wireless local positioning systems are now possible.