粗调和细调相结合的标准CMOS低噪声环形压控振荡器

本文提出了一种基于65nm CMOS标准工艺、采用粗调和细调相结合的低噪声环形压控振荡器。论文分析了环形振荡器中的直接频率调制机理,并采用开关电容阵列来减小环形压控振荡器的增益从而抑制直接频率调制效应。开关电容采用电容密度较高的二维叠层MOM电容使该压控振荡器与标准的CMOS工艺兼容。所设计压控振荡器的频率范围为480MHz～1100MHz,调谐范围为78%,测试得到输出频率为495MHz时的相位噪声为-120dBc/Hz@1MHz。该压控振荡器在1.2V的偏压下的功耗为3.84mW,相应的优值(FOM)为-169dBc/Hz。     

射频卫星电视天线电路中LC压控振荡器设计

本文设计了一款应用于卫星电视天线电路中低功耗、低相噪的宽带单片集成压控振荡器。该振荡器利用PMOS尾电流源和MIM电容阵列结构。在保证调谐范围的前提下,有效的降低了相位噪声。使得该压控振荡器实现了3.384GHz~4.022GHz频段的覆盖,在中心频率为3.7GHz时,100Hz和1MHz频偏处的相位噪声分别为-90.4dBc/Hz和-119.1dBc/Hz,工作电压下为1.8V,功耗仅为2.5mW。     

A 1-V 9.7-mW CMOS Frequency Synthesizer for IEEE 802.11a Transceivers

A 1-V CMOS frequency synthesizer is proposed for wireless local area network 802.11a transceivers using a novel transformer-feedback voltage-controlled oscillator (VCO) for low voltage and a stacked frequency divider for low power. Implemented in a 0.18-mum CMOS process and operated at 1-V supply, the VCO measures a phase noise of -140.5 dBc at an offset of 20 MHz with a center frequency of 4.26 GHz and a power consumption of 5.17 mW. Its tuning range is as wide as 920 MHz (23%). By integrating the VCO into a frequency synthesizer, a phase noise of -140.1 dBc/Hz at an offset of 20 MHz is measured at a center frequency of 4.26 GHz. Its output frequency can be changed from 4.112 to 4.352 GHz by switching the 3-bit modulus of the programmable divider. The synthesizer consumes only 9.7 mW and occupies a chip area of 1.28 mm².     

一个8GHz高功率AlGaN/GaN HEMT VCO

基于中科院微电子所的AlGaN/GaN HEMT工艺研制了一个X波段高功率混合集成压控振荡器（VCO）。电路采用源端调谐的负阻型结构,主谐振腔由开路微带和短路微带并联构成,实现高Q值设计。在偏置条件为VD=20V, VG=-1.9V, ID=150mA时,VCO在中心频率8.15 GHz处输出功率达到28 dBm,效率21%,相位噪声-85 dBc/Hz@100 KHz,-128 dBc/Hz@1 MHz。调谐电压0~5V时,调谐范围50 MHz。分析了器件闪烁噪声对GaN HEMT基振荡器相位噪声性能的主导作用。测试结果显示了AlGaN/GaN HEMT工艺在高功率低噪声微波频率源中的应用前景。     

SiGe Bipolar VCO With Ultra-Wide Tuning Range at 80 GHz Center Frequency

A SiGe millimeter-wave VCO with a center frequency around 80 GHz and an extremely wide (continuous) tuning range of 24.5 GHz ( ap 30%) is presented. The phase noise at 1 MHz offset is -97 dBc/Hz at the center frequency (and less than -94 dBc/Hz in a frequency range of 21 GHz). The maximum total output power is about 12 dBm. A cascode buffer improves decoupling from the output load at reasonable VCO power consumption (240 mW at 5 V supply voltage). A low-power frequency divider (operating up to 100 GHz) provides, in addition, a divided-by-four signal. As a further intention of this paper, the basic reasons for the limitation of the tuning range in millimeter-wave VCOs are shown and the improvement by using two (instead of one) varactor pairs is demonstrated.     

Low noise 5 GHz differential VCO using InGaP/GaAs HBT technology

The authors present the first InGaP/GaAs HBT differential VCOs with low phase noise performance. One is a cross coupled differential VCO, and the other is a Colpitts differential VCO. To achieve a fully integrated VCO, collector-base junction capacitance of HBT transistor is used for the frequency tuning varactor. The measured output frequency ranges of VCOs are 290 MHz and 190 MHz, and the phase noises at an offset frequency of 1 MHz are -118 dBc/Hz and -117 dBc/Hz respectively. The each VCO core dissipates 13.2 mW from a 3.5 V supply, and the output power is about -0.2 dBm. Concerned with cross coupled VCO, it shows the figure of merit of -179 dBc/Hz, which is the best result among the reported compound semiconductor FET and HBT VCOs.     

A low-noise, 900-MHz VCO in 0.6-μm CMOS

This paper describes a low-noise, 900-MHz, voltage-controlled oscillator (VCO) fabricated in a 0.6-μm CMOS technology. The VCO consists of four-stage fully differential delay cells performing full switching. It utilizes dual-delay path techniques to achieve high oscillation frequency and obtain a wide tuning range. The VCO operates at 750 MHz to 1.2 GHz, and the tuning range is as large as 50%. The measured results of the phase noise are -101 dBc/Hz at 100-kHz offset and -117 dBc/Hz at 600-kHz offset from the carrier frequency. This value is comparable to that of LC-based integrated oscillators. The oscillator consumes 10 mA from a 3.0-V power supply. A prototype frequency synthesizer with the VCO is also implemented in the same technology, and the measured phase noise of the synthesizer is -113 dSc/Hz at 100-kHz offset     

一种简易微波VCO的设计*

描述了一种高性能简易微波VCO器件的设计和实验。该器件基于负阻原理设计,利用微波FET和变容二极管等分立元件制作,具有高性价比的特点。设计过程中利用ADS软件进行电路的匹配和优化,通过合适的外电路设计对变容二极管VCO的调频线性度进行改善,同时,降低了VCO的相位噪声。实际电路的测试结果表明,当该VCO的中心频率为4.3GHz时,其调谐范围大于200MHz,输出功率大于5.2dBm,相位噪声优于-112dBc/Hz@1MHz和-83dBc/Hz@100kHz。     

A /spl Sigma/-/spl Delta/ fractional-N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications

A fractional-N frequency synthesizer (FNFS) in a 0.5-/spl mu/m SiGe BiCMOS technology is implemented. In order to operate in a wide-band frequency range, a switched-capacitors bank LC tank voltage-controlled oscillator (VCO) and an adaptive frequency calibration (AFC) technique are used. The measured VCO tuning range is as wide as 600 MHz (40%) from 1.15 to 1.75 GHz with a tuning sensitivity from 5.2 to 17.5 MHz/V. A 3-bit fourth-order /spl Sigma/-/spl Delta/ modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3 Hz as well as agile switching time. The experimental results show -80 dBc/Hz in-band phase noise within the loop bandwidth of 25 kHz and -129 dBc/Hz out-of-band phase noise at 400-kHz offset frequency. The fractional spurious is less than -70 dBc/Hz at 300-kHz offset frequency and the reference spur is -75 dBc/Hz. The lock time is less than 150 /spl mu/s. The proposed synthesizer consumes 19.5 mA from a single 2.8-V supply voltage and meets the requirements of GSM/GPRS/WCDMA applications.     

一种LC全集成、具有对称噪声滤波及宽调节范围的4.8GHz CMOS平衡振荡器

将对称噪声滤波技术应用到4.8GHz LC全集成VCO设计中.该VCO具有很低的相位噪声以及716MHz的调节范围,在SMIC 0.25μm单层多晶、五层金属、n阱 RF CMOS工艺上实现,在2.5V电源电压下工作电流仅为6mA,与常规VCO比较,在相同条件下,噪声性能改善了6dBc/Hz.芯片测试结果表明,在偏离4.8GHz载波1MHz的地方相位噪声为-123.66dBc/Hz,该设计在锁相环及其他消费类电子产品中有广泛应用.     

A fully integrated 5.8 GHz U-NII band 0.18-/spl mu/m CMOS VCO

A fully integrated 5.8 GHz CMOS L-C tank voltage-controlled oscillator (VCO) using a 0.18-/spl mu/m 1P6M standard CMOS process for 5 GHz U-NII band WLAN application is presented. The VCO core circuit uses only PMOS to pursue a better phase noise performance since it has less 1/f noise than NMOS. The measurement is performed by using a FR-4 PCB test fixture. The output frequency of the VCO is from 5860 to 6026 MHz with a 166 MHz tuning range and the phase noise is -96.9 dBc/Hz at 300 kHz (or -110 dBc/Hz at 1 MHz) with V ctrl = 0 V. The power consumption of the VCO excluding buffer amplifiers is 8.1 mW at V/sub DD/ = 1.8 V and the output power is -4 dBm.     

A 6 GHz high power and low phase noise VCO using an InGaP/GaAs HBT

A 6 GHz voltage controlled oscillator (VCO) optimized for power and noise performance was designed and characterized. This VCO was designed with the negative-resistance (Neg-R) method, utilizing an InGaP/GaAs hetero-junction bipolar transistor in the negative-resistance block. A proper output matching network and a high Q stripe line resonator were used to enhance output power and depress phase noise. Measured central frequency of the VCO was 6.008 GHz. The tuning range was more than 200 MHz. At the central frequency, an output power of 9.8 dBm and phase noise of -122.33 dBc/Hz at 1 MHz offset were achieved, the calculated RF to DC efficiency was about 14%, and the figure of merit was -179.2 dBc/Hz.     

Fully Differential 5‐GHz LC‐Tank VCOs with Improved Phase Noise and Wide Tuning Range

In this paper, we propose two LC voltage‐controlled oscillators (VCOs) that improve both phase noise and tuning range. With both 1/f induced low‐frequency noise and low‐frequency thermal noise around DC or around harmonics suppressed significantly by the employment of a current‐current negative feedback (CCNF) loop, the phase noise in the CCNF LC VCO has been improved by about 10 dB at 6 MHz offset compared to the conventional LC VCO. The phase noise of the CCNF VCO was measured as ?112 dBc/Hz at 6 MHz offset from 5.5 GHz carrier frequency. Also, we present a bandwidth‐enhanced LC VCO whose tuning range has been increased about 250 % by connecting the varactor to the bases of the cross‐coupled pair. The phase noise of the bandwidth‐enhanced LC‐tank VCO has been improved by about 6 dB at 6 MHz offset compared to the conventional LC VCO. The phase noise reduction has been achieved because the DC‐decoupling capacitor Cc prevents the output common‐mode level from modulating the varactor bias point, and the signal power increases in the LC‐tank resonator. The bandwidth‐enhanced LC VCO represents a 12 % bandwidth and phase noise of ?108 dBc/Hz at 6 MHz offset.     

900 MHz压控振荡器设计

采用集总元件变容二极管和超高频三极管设计900 MHz压控振荡器,根据ADS2006A软件仿真确定了压控振荡器的电路参数,并对相关指标如相位噪声、调谐带宽、稳定系数、输出功率和谐波电平等进行了仿真,通过调整电路参数,优化电路结构,实现了工作频率为1 GHz、调谐带宽为90 MHz的压控振荡器,其相位噪声在偏移中心频率10 kHz处为-105 dBc/Hz,在100 kHz处为-120 dBc/Hz,该设计大大降低了系统成本.     

A Differentially-Tuned Voltage ControlledOscillator Using Symmetric Transformer

This letter proposes a new voltage controlled oscillator (VCO) topology that cancels common-mode noise by adoption of differential tuning varactor. To suppress common mode noise effectively, a symmetric three-coil transformer is proposed as a differential tuning resonator. The measured phase noise shows -128.7 dBc/Hz at 1 MHz offset frequency from the 1.2 GHz oscillation frequency. Over the whole frequency range, common-mode noise rejection is larger than 36 dB. Measured tuning range of the proposed VCO is about 204 MHz from the 1.18 GHz to 1.38 GHz while dissipating 1.2 mA at 1.8 V power supply.     

An 8 GHz high power AlGaN/GaN HEMT VCO

A high power X-band hybrid microwave integrated voltage controlled oscillator(VCO) based on Al-GaN /GaN HEMT is presented.The oscillator design utilizes a common-gate negative resistance structure with open and short-circuit stub microstrip lines as the main resonator for a high Q factor.The VCO operating at 20 V drain bias and-1.9 V gate bias exhibits an output power of 28 dBm at the center frequency of 8.15 GHz with an efficiency of 21%.Phase noise is estimated to be -85 dBc/Hz at 100 kHz offset and -1...     

CMOS低相位噪声压控振荡器的设计

基于65 nm CMOS标准工艺库,设计了一个工作频率在10 GHz的具有低相位噪声的CMOS电感电容型压控振荡器。该压控振荡器选用CMOS互补交叉耦合型电路结构,采用威尔逊型尾电流源负反馈技术来降低相位噪声。仿真结果表明,此压控振荡器工作频率覆盖范围为9.9~11.2 GHz,调谐范围为12.3%,中心频率为10.5 GHz,在频率偏移中心频率1 MHz下的相位噪声为-113.3 dBc/Hz,核心功耗为2.25 mW。     

Design and Analysis of Varactorless 65 nm MMW Voltage Controlled Oscillator

In this work a novel inductive tuning technique for millimeter wave (mmw) applications is presented. Fine frequency tuning is performed using a transformer. For the LC tanks inductive element, transformer is used. To tune the VCO MOS switch is placed at center tapping of the secondary coil of the transformer. The simulation shows that by changing the operating condition of MOS switch frequency band from 59.1 GHz to 64.6 GHz is obtained. The proposed 60 GHz VCO is designed using UMC 65 nm CMOS single Poly eight Metal (1P8M) Technology. Obtained Frequency Tuning Range (FTR) is 8.89% and the corresponding phase noise variation is from ???112.4 dBc/Hz to ???115.9 dBc/Hz at 10 MHz offset from the carrier. The worst phase noise value is ???112.4 dBc/Hz which is obtained at 0.3 V tuning voltage. For 0.8 V supply voltage 7.44 mW of power is dissipated. And the calculated Figure of Merit (FOM) for whole FTR, ranges from ???179.89 dBc/Hz to ???182.62 dBc/Hz.

     

使用三位三阶Δ∑调制器的集成1GHz小数频率合成器

本文实现了一个采用三位三阶Δ∑调制器的高频谱纯度集成小数频率合成器.该频率合成器采用了模拟调谐和数字调谐组合技术来提高相位噪声性能,优化的电源组合可以避免各个模块之间的相互干扰,并且提高鉴频鉴相器的线性度和提高振荡器的调谐范围.通过采用尾电流源滤波技术和减小振荡器的调谐系数,在片压控振荡器具有很低的相位噪声,而通过采用开关电容阵列,该压控振荡器达到了大约100MHz的调谐范围,该开关电容阵列由在片数字调谐系统进行控制.该频率合成器已经采用0.18μm CMOS工艺实现,仿真结果表明,该频率频率合成器的环路带宽约为14kHz,最大带内相位噪声约为-106dBc/Hz;在偏离载波频率100kHz处的相位噪声小于-120dBc/Hz,具有很高的频谱纯度.该频率合成器还具有很快的反应速度,其锁定时间约为160μs.     

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a standard 0.5 /spl mu/m digital CMOS process for wireless communication. The voltage-controlled oscillator (VCO) required for the low-frequency loop is designed using a ring-type VCO and achieves a tuning range of 89% from 356 to 931 MHz and a phase noise of -109.2 dBc/Hz at 600 kHz offset from 856 MHz. With an active chip area of 2000/spl times/1000 /spl mu/m/sup 2/ and at a 2 V supply voltage, the whole synthesizer achieves a tuning range from 1.8492 to 1.8698 GHz in 200 kHz steps with a measured phase noise of -112 dBc/Hz at 600 kHz offset from 1.86 GHz. The measured settling time is 128 /spl mu/s and the total power consumption is 95 mW.