具有自校准压控振荡器和精确自动频率校准算法的低噪声频率合成器

A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.     

Investigation of a high frequency CMOS unsaturated ring oscillator

Investigation of a high frequency unsaturated ring oscillator with cross coupled load is presented, and oscillation frequency compared with multi-path high frequency ring oscillators. Stability of oscillation is shown heuristically, via geometric argument on a phase plane, where the presence of negative impedance in the cross coupled pair of the delay cell is deemed important. Oscillation frequency formula is presented, and design insight given. In addition, a novel design methodology on lowering its phase noise is developed. Simulations on example circuit designs using 0.18???m CMOS technology demonstrate the higher frequency obtained, oscillation stability, frequency formula and design insight, as well as phase noise methodology.     

Estimating the frequency of a noisy sinusoid by linear regression (Corresp.)

The estimation of the parameters of a sinusoid from observations of signal samples corrupted by additive noise is investigated. At high signal-to-noise ratios the additive noise is viewed as an equivalent phase noise, suggesting frequency and phase estimation by linear regression on the signal phase. The variances of the regression estimates are shown to achieve the Cramer-Rao bounds. A formula for the variance of the regression frequency estimator is derived in terms of the noise power spectrum. A simple formula for the variance with1/f^{2}phase noise is presented.     

基于相位调制等效展宽激光线宽的极低相噪光电振荡器

光电振荡器是一种采用光电结合方式的新型微波频率源,其利用光学长时储能,可以实现极低相位噪声的信号输出。文章研究了光纤中散射噪声对光电振荡器相位噪声的影响,重点介绍了基于相位调制等效展宽激光线宽,抑制布里渊散射噪声架构,通过理论公式推导以及实验验证,表明了上述架构可极大改善光电振荡器的相位噪声。实验中采用调制频率为50 MHz、调制幅度为3.1的相位调制信号对激光线宽进行等效展宽,得到在10 GHz频率下为-157.3 dBc/Hz@10 kHz的极低相位噪声信号输出。     

Theoretical analysis of low phase noise design of CMOS VCO

A theoretical analysis on low phase noise of voltage-controlled oscillators (VCOs) based on complementary cross-coupled LC VCO by 0.35-/spl mu/m complementary metal oxide semiconductor technology is demonstrated. From the procedure of optimization steps, the excess noise factor of the amplifier coming from the active device has been determined. The proposed VCO operates at 2 GHz with phase noise of -116 dBc/Hz at offset frequency 600 kHz. The power consumption is 22.62 mW under 3 V bias with 9.1% frequency tuning. The achievement of low phase noise is also matched with prediction by formula in the frequency domain.     

A 3 to 5 GHz low-phase-noise fractional-N frequency synthesizer with adaptive frequency calibration for GSM/PCS/DCS/WCDMA transceivers

正A low-phase-noise S-A fractional-TV frequency synthesizer for GSM/PCS/DCS/WCDMA transceivers is presented.The voltage controlled oscillator is designed with a modified digital controlled capacitor array to extend the tuning range and minimize phase noise.A high-resolution adaptive frequency calibration technique is introduced to automatically choose frequency bands and increase phase-noise immunity.A prototype is implemented in 0.13μm CMOS technology.The experimental results show that the designed 1.2 V wideband frequency synthesizer is locked from 3.05 to 5.17 GHz within 30μs,which covers all five required frequency bands.The measured in-band phase noise are -89,-95.5 and -101 dBc/Hz for 3.8 GHz,2 GHz and 948 MHz carriers,respectively, and accordingly the out-of-band phase noise are -121,-123 and -132 dBc/Hz at 1 MHz offset,which meet the phase-noise-mask requirements of the above-mentioned standards.     

Simulation of phase noise generated by white noise in 1.7 GHz CMOSLC oscillator

The phase noise resulting from upconversion of white noise in a CMOS LC oscillator is investigated. HSPICE simulations of phase noise resulting from the random-phase white noise in a 1.7 GHz CMOS LC oscillator have been performed and demonstrate that the phase noise resulting from the upconversion of white noise has a 1/f-dependence on the offset frequency and becomes larger as the white noise increases. The results provide a confirmation by circuit simulations of Leeson's empirical formula, and provide a technique for the design of low noise oscillators     

用于太赫兹通信的双向全并行相位估计算法

在太赫兹通信的超宽带应用场景下,太赫兹载波是通过多次倍频实现,因而导致相噪严重恶化。基于太赫兹频率下的多极/零相位噪声模型,在传统的盲相位估计算法的基础上,提出了一种全并行化的相位估计算法。该算法通过在每个并行数据中插入导频,将导频相噪信息作为初始相位对并行数据进行相位扩展及旋转鉴相。借鉴传统盲相位估计算法的最佳相位估计值的判决选择思路,同时利用前一时刻导频和当前时刻导频,对当前并行数据从前后两个方向进行相位估计并对前后两个估计相位基于距离前后导频的位置进行加权求和以获得最佳相位估计信息。经过仿真验证,通过该算法后残余相噪在1 MHz和10 MHz处分别降低10 dBc/Hz和25 dBc/Hz。     

正交多载波降噪差分混沌键控通信系统

为解决多载波差分混沌移位键控(MC-DCSK)系统传输速率低和误码性能差的缺点,该文提出一种正交多载波降噪差分混沌移位键控(QMC-NR-DCSK)系统.在发送端,预定义载波用于发送参考信号,剩余M-1个不同中心频率的载波及其经正交调制技术后得到的频率相同但相位正交的载波都用于传输信息信号,此外,通过进一步引入Hilb...     

低相位噪声信号的谱线宽度

提出了由相位噪声计算信号谱线宽度的计算公式,从而计算出脉冲多普勒雷达频综器输出的激励信号的谱线宽度,并且发现低相位噪声信号的谱线宽度是通用仪表所不能精确测量的.     

Measuring Transistor Large-Signal Noise Figure for Low-Power and Low Phase-Noise Oscillator Design

This paper presents an experimental method for determining additive phase noise of an unmatched transistor in a stable 50-$Omega$ environment. The measured single-sideband phase noise is used to determine the large-signal noise figure of the device. From the Leeson–Cutler formula and a known oscillator circuit with the characterized transistor, the phase noise of the oscillator can be predicted. The method is applied to characterization of several bipolar devices around 3.4 GHz, the frequency of interest for miniature rubidium-based atomic clock voltage-controlled oscillators.      

A ring oscillator with very low phase noise and wide frequency range using carbon nanotube technology for PLL applications

This paper presents a wide frequency range three-stage voltage-controlled ring oscillator in CNTFET technology. The advantages of CNTFETs are the high speed of charge carriers, high signal to noise ratio, small size and ballistic transport. Therefore in comparison with MOSFETs, they have a higher frequency, and can operate at a wide frequency range with a very low phase noise if forward bulk bias and active inductor techniques are simultaneously used in the oscillators that employ CNTFETs. In this paper, the Stanford CNTFET model is implemented in Verilog-A, and the proposed CNT ring oscillator is simulated using ADS software over the 50–500 GHz frequency range. The phase noise of the oscillator is ? 136 dBc/Hz at 1 MHz offset, which is suitable for PLL applications.

     

正交多载波降噪差分混沌键控通信系统

为解决多载波差分混沌移位键控(MC-DCSK)系统传输速率低和误码性能差的缺点,该文提出一种正交多载波降噪差分混沌移位键控(QMC-NR-DCSK)系统。在发送端,预定义载波用于发送参考信号,剩余M-1个不同中心频率的载波及其经正交调制技术后得到的频率相同但相位正交的载波都用于传输信息信号,此外,通过进一步引入Hilbert变换,将系统的频带利用率和传输速率提升为MC-DCSK系统的4倍。在接收端引入滑动平均滤波器的降噪操作降低了噪声的方差,从而改善了系统误码性能。推导了QMC-NR-DCSK系统在加性高斯白噪声(AWGN)信道和多径瑞利衰落(RFC)信道下的比特误码率公式并进行了仿真。仿真结果和理论分析表明：QMC-NR-DCSK系统能有效提升传输速率、带宽效率和误码性能,为该系统应用于多载波无线通信提供理论参考。     

光纤时频传递系统的中继技术分析

为开展长距离高精度时间频率传输系统研究,对多级光纤时间频率传递级联系统的时延抖动进行理论分析,得出级联系统总时延抖动的一般公式。在实验上实现了两级级联50km光纤时频传递系统的闭环锁定,分别通过测试单级系统和级联系统的鉴相误差电压得到其时延抖动。通过实验结果和理论计算比较,分析了主要实验误差来源;通过分析掺铒光纤放大器(EDFA)放大自发辐射(ASE)产生的噪声对信噪比(SNR)的影响,系统频率稳定度由于信噪比的下降而产生劣化。     

高性能超低功耗的4.224GHz正交LC VCO

采用Jazz0.18μm RF CMOS工艺设计并实现应用于MB-OFDM超宽带频率综合器的4.224GHz电感电容正交压控振荡器。通过解析的方法给出了电感电容正交压控振荡器的模型,并推导出简洁的公式解释了相位噪声性能与耦合因子的关系。测试结果显示,核心电路在1.5V电源电压下,消耗6mA电流,频率调谐范围为3.566~4.712GHz;在主频频偏1MHz处的相位噪声为-119.99dBc/Hz,对应的相位噪声的FoM(Figure-of-Merit)为183dB;I、Q两路信号等效的相位误差为2.13°。     

基于相位匹配的噪声调幅干扰下LFM信号检测

该文提出一种基于相位匹配原理的噪声调幅干扰下LFM信号检测方法。推导了噪声调幅干扰信号载频估计方法,利用干扰信号载频信息,实现信号的相位匹配,并基于最小二乘相位匹配方法实现LFM信号检测。仿真结果证明了文中原理和方法的正确性。     

基于锁定时间分析的锁相环频率合成器

提出了一种新的针对采用二阶无源滤波器的锁相环频率合成器锁定时间的估算公式,并通过仿真软件及实测结果对该公式进行了验证。基于该估算公式,设计了一种具有快速锁定功能的锁相环频率合成器。实验结果表明该锁相环频率合成器锁定时间小于7μs,具有快速锁定的功能。同时该锁相环还具有良好的相位噪声性能,对于32GHz输出信号相位噪声为-72dBc/Hz@1kHz以及-90dBc/Hz@1MHz。     

估算高稳时钟抖动的幂率积分下限的研究

 幂律积分法是估算亚皮秒级时钟信号抖动所采用的一种常用方法.该方法的换算结果与积分区间有关,尤其与积分下限有关.通过对幂律积分法将相位噪声转换为抖动的关系式介绍,推导了幂律积分下限与采样时钟的频率、被采样模拟信号的最高频率及A/D变换的有效位之间的关系,给出了估算幂律积分下限的算式,并提供了该算式在估算中频采样系统时钟信号抖动中的应用实例,间接证明了该算式.     

MIMO-OFDM系统中相噪公共相位误差的分析与抑制

随着无线通信频段的不断提高,非理想载波所引入的相位噪声对多输入多输出正交频分复用(MIMO-OFDM)系统性能的影响也越来越突出,不仅影响OFDM系统载波的正交性,同时导致多天线预编码性能急剧下降。相位噪声对MIMO-OFDM系统的影响可分为公共相位误差(CPE)和载波间干扰(ICI)两部分。本文对CPE影响MIMO-OFDM系统的性能进行深入分析,提出一系列基于频域正交导频设计的CPE估计算法,以实现对CPE的有效抑制;最后,在多个场景下进行链路仿真,充分验证了提出算法的有效性和可靠性。     

锁相环环路滤波器噪声特性分析与仿真

为估计环路滤波器对锁相频率合成器输出相位噪声的贡献,建立了一种常用的有源差分环路滤波器噪声模型,并推导出滤波器中各噪声源贡献的噪声的理论公式。针对一实际滤波器贡献的相位噪声进行理论计算,考虑了滤波器中运放的非理想特性后,对滤波器中各个噪声源贡献的相位噪声进行了仿真。通过理论结果和仿真结果对比,得出理论公式对实际环路滤波器噪声进行了很好的估计。最后给出环路滤波器设计时在噪声性能方面的考虑。