Power-Aware Multiband–Multistandard CMOS Receiver System-Level Budgeting

A systematic system-level design methodology for multiband-multistandard (MB-MS) wideband/reconfigurable CMOS receivers is presented. The methodology determines the specifications (noise figure (NF) and linearity) for each building block to minimize the overall power consumption. System-level simulations show that the gain variation of the LNA for various bands/standards is an important factor in minimizing the power consumption for any MB-MS receiver. Analytical expressions for the optimum gain variation of the LNA, NF, and input-referred third-order intercept point of each building block are presented. The design methodology is applied to a wideband receiver covering Global Systems for Mobile Communications (GSM) 900- and 1900-MHz bands, Global Positioning Systems (GPS), and wideband code-division multiple-access (WCDMA) standards. As an example, the estimated power consumption is reduced by 40% when compared with the approach where the gain of the LNA is constant.     

Low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications

State-of-the-art endoscopy systems require electronics allowing for real-time, bidirectional data transfer. Proposed are 2.4-GHz low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications. The prototype integrates a low-IF receiver analog front-end [low noise amplifier (LNA), double balanced down-converter, bandpass-filtered automatic gain controlled (AGC) loop and amplitude-shift keying (ASK) demodulator], and a direct up-conversion transmitter analog front-end [20-MHz IF phase-locked loop (PLL) with well-defined amplitude control circuit, ASK modulator, up-converter, and power amplifier] on a single chip together with an internal radio frequency oscillator and local oscillating (LO) buffers. Design tradeoffs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low power consumption. The circuits have been implemented in a 0.25-microm CMOS process. The measured sensitivity of the receiver analog front-end is -70 dBm with a data rate of 256 kbps, and the measured output power of the transmitter analog front-end could achieve -23 dBm with a data rate of 1 Mbps. The integrated circuit consumes a current of 6 mA in receiver mode and 5.6 mA in transmitter mode with a power supply of 2.5 V. This paper shows the feasibility of achieving the analog performance required by the wireless endoscopy capsule system in 0.25 microm CMOS.     

A 3.1 to 5 GHz CMOS Transceiver for DS‐UWB Systems

This paper presents a direct‐conversion CMOS transceiver for fully digital DS‐UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase‐locked loop (PLL), and a voltage controlled oscillator (VCO). A single‐ended‐to‐differential converter is implemented in the down‐conversion mixer and a differential‐to‐single‐ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 mm² die using standard 0.18 µm CMOS technology and a 64‐pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low‐power, and high‐speed wireless personal area network.     

A high speed sampler for sub-sampling IR-UWB receiver

A high speed sampler for a sub-sampling impulse radio UWB receiver is presented. In this design, the sampler uses a time-interleaved topology with a single track and hold circuit, full custom clock generator, and offset cancelled comparator. These three main blocks are also discussed and analyzed. The circuit was fabricated in 0.13 μm CMOS technology. Measurement results indicate that the sampler achieves a maximum 3 GS/s sampling rate. The power consumption of the sampler is 27 mW under a supply voltage of 1.2 V. The total chip area including pads is 1.4 × 0.97 mm2.     

A 2.4 GHz low power wireless transceiver analog front-end for endoscopy capsule system

This work presents the design and implementation of a 2.4 GHz low power wireless transceiver analog front-end for the endoscopy capsule system in 0.25 μm CMOS. The prototype integrates a low-IF receiver analog front-end (low noise amplifier, double-balanced down-converter, band-pass-filtered AGC loop, and ASK demodulator) and a direct-conversion transmitter analog front-end (20 MHz IF PLL with well-defined amplitude control circuit, ASK modulator, up-converter, and output buffer) on a single chip together with one integrated RF oscillator and two LO buffers. Trade-off has been made over the design boundaries of the different building blocks to optimize the overall system performance. All building blocks feature the circuit topologies that enable comfortable operation at low power consumption. As a result, the IC works at a 2.5 V power supply, while only consuming 15 mW in receiver (RX) mode and 14 mW in transmitter (TX) mode. To build a complete transceiver for the endoscopy capsule system, only an antenna, a duplexer, and a digital controller are needed besides the presented analog front-end chip.     

Low power delta-sigma Modulator for ADSL applications in a low-Voltage CMOS technology

This paper examines the design and implementation of a fourth-order low-pass delta-sigma modulator using a systematic top-down design methodology. Special effort has been made to reduce the power consumption of the modulator through careful system-level modeling and synthesis of circuit specifications. Tradeoffs between circuit building block specifications, optimization time and computing resources are derived. This system-level modeling was tested through the successful implementation of a switched-capacitor delta-sigma analog-to-digital converter integrated circuit (IC) with an output rate slightly exceeding 2 MS/s, in a 1.8-V 0.18-/spl mu/m, single-polysilicon six-metal standard CMOS process. When sampled at 50 MHz, experimental results reveal that the IC achieves 77.6-dB dynamic range. The prototype consumes 18.8 mW of power, making it one of the lowest power dissipations in switched-capacitor implementations, and for applications where output rates exceed 2 MS/s. When compared to other state-of-the-art switched-capacitor modulators using a widely adopted figure of merit, the modulator dissipates less power and offers superior overall performance.     

A dual-mode 802.11b/bluetooth radio in 0.35-/spl mu/m CMOS

A fully integrated dual-mode CMOS transceiver tuned to 2.4 GHz consumes 65 mA in receive mode and 78 mA in transmit mode from a 3-V supply. The radio includes all the receive and transmit building blocks, such as frequency synthesizer, voltage-controlled oscillator (VCO), and power amplifier, and is intended for use in 802.11b and Bluetooth applications. The Bluetooth receiver uses a low-IF architecture for higher level of integration and lower power consumption, while the 802.11b receiver is direct conversion. The receiver achieves a typical sensitivity of -88 dBm at 11 Mb/s for 802.11b, and -83 dBm for Bluetooth mode. The receiver minimum IIP3 is -8 dBm. Both transmitters use a direct-conversion architecture, and deliver a nominal output power of 0 dBm, with a power range of 20 dB in 2-dB steps.     

A low-power highly digitized receiver for 2.4-GHz-band GFSK applications

This paper describes the design and measurement results of a low-power highly digitized receiver for Gaussian frequency-shift keying modulated input signals at 2.4 GHz. The RF front-end has been based on a low-IF architecture and does not require any variable gain or filtering blocks. The full dynamic range of the low-IF signal is converted into the digital domain by a low-power high-resolution time-continuous SigmaDelta analog-to-digital converter (ADC). This leads to a linear receive chain without limiters. A fifth-order poly-phase loop filter is used in the complex SigmaDelta ADC. The digital block performs filtering and demodulation. Channel filtering is combined with matched filtering and the suppression of noise resulting from the SigmaDelta ADC. The high degree of digitization leads to design flexibility with respect to changing standards and scalability in future CMOS generations. The receiver has been realized in a standard 0.18-mum CMOS process and measures 3.5 mm². The only external components are an antenna filter and a crystal. The power consumption is only 32 mW in the continuous mode, which is at least a factor of two lower than state-of-the-art CMOS receivers     

A CMOS ultra-wideband impulse radio transceiver for 1-mb/s data communications and /spl plusmn/2.5-cm range finding

A CMOS ultra-wideband impulse radio (UWB-IR) transceiver was developed in 0.18-/spl mu/m CMOS technology. It can be used for 1-Mb/s data communications as well as for precise range finding within an error of /spl plusmn/2.5 cm. The power consumptions of the transmitter and receiver for data communication are 0.7 and 4.0 mW, respectively. When an LNA operates intermittently through bias switching, the power consumption of the transceiver is only 1 mW. The range for data communication is 1 m with BER of 10/sup -3/. For ranging applications, the transmitter can reduce the power to 0.7 /spl mu/W for 1k pulses per second, and the receiver consumes little power. The transceiver design, all-digital transmitter, and intermittent circuit operation at the receiver reduce the power consumption dramatically, which makes the transceiver well suited for applications like sensor networks. The electronic field intensity is lower than 35 /spl mu/V/m, and thus the UWB system can be operated even under the current Japan radio regulations.     

A 2 MHz Wireless CMOS Transceiver for Implantable Biosignal Sensing Systems

An implementation of an implantable sensing biosystem composes of a readout circuit, a power management block, an embedded microcontroller unit (MCU), an implantable drug delivery section and a wireless uplink transceiver system. This paper describes a bi-directional wireless transceiver system for implantable sensing systems. The transceiver system is composed of an external and implantable transceiver, communicating through an inductive link. Half duplex communication between transceivers at a 10 Kbps data rate was achieved at a maximum distance of 4 cm. Command and data will be supplied to the implantable module by radio frequency (RF) telemetry utilizing an amplitude shift keying (ASK) modulated 2 MHz carrier frequency. A capacitor-less amplitude demodulation receiver architecture was produced in the research with implantable receiver core area measuring at 113.2 μm by 171.8 μm with average power dissipation at 815.1 μW at a 3.3 V single rail power supply. An active uplink transceiver utilizing load shift keying (LSK) as backward data telemetry was designed. Implantable transmitter core area measures 251.7 μm by 139.3 μm, consuming 103.62 mW while driving an RF ferrite core antenna at maximum reading range. Integrating both circuits, implantable transceiver, measuring 355.3 μm by 171.8 μm, was designed and implemented using TSMC 0.35 μm mixed-signal 2P4M 3.3 V standard CMOS process. The integrated circuit solution addressed solutions for many of the problems associated with implanted devices and introduces circuits which improve in several ways over previously published designs, in functionality and integration level. In addition to being fully integrated in plain CMOS technology, not relying at least partly on available specialized elements and expensive technologies, these building blocks improve on previous designs in performance and/or power consumption. This work succeeded in implementing building blocks for an implantable transceiver, which depends only on the absolute minimum off-chip components. A complete implantable chip is presented, which highlight the design tradeoffs and optimizations applied to the design of CMOS implantable system chips.     

A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

A 0.1–4 GHz software-defined radio (SDR) receiver with reconfigurable 10–100 MHz signal bandwidth is presented. The complete system design methodology, taking blocker effects into account, is provided. Fully differential Op-Amp with Miller feedback and feed-forward compensations is proposed to support wideband analog circuits with low power consumption. The stability and isolation of inverter-based trans-conductance amplifier are analyzed in details. The design approach of high linearity Tow-Thomas trans-impedance amplifier is presented to reject out-of-band blockers. To compensate for PVT variations, IIP2, frequency tuning, DC offset and IQ calibration are also integrated on-chip. The SDR receiver has been implemented in 65 nm CMOS, with 1.2/2.5 V power supply and a core chip area of 2.4 mm². The receiver achieves S11 input matching below ?10 dB and a NF of 3–8 dB across the 0.1–4 GHz range, and a maximum gain of 82–92 dB with a 70 dB dynamic range. Dissipated power spans from 30 to 90 mW across this entire frequency range. For LTE application with 20 MHz signal bandwidth and a LO frequency of 2.3 GHz, the receiver consumes 21 mA current.     

An analog feed-forward neural network with on-chip learning

An analog continuous-time neural network with on-chip learning is presented. The 4-3-2 feed-forward network with a modified back-propagation learning scheme was build using micropower building blocks in a double poly, double metal 2 CMOS process. The weights are stored in non-volatile UV-light programmable analog floating gate memories. A differential signal representation is used to design simple building blocks which may be utilized to build very large neural networks. Measured results from on-chip learning are shown and an example of generalization is demonstrated. The use of micro-power building blocks allows very large networks to be implemented without significant power consumption.     

A Zero-IF 60 GHz 65 nm CMOS Transceiver With Direct BPSK Modulation Demonstrating up to 6 Gb/s Data Rates Over a 2 m Wireless Link

This paper presents a directly modulated, 60 GHz zero-IF transceiver architecture suitable for single-carrier, low-power, multi-gigabit wireless links in nanoscale CMOS technologies. This mm-wave front end architecture requires no upconversion of the baseband signals in the transmitter and no analog-to-digital conversion in the receiver, thus minimizing system complexity and power consumption. All circuit blocks are realized using sub-1.0 V topologies, that feature only a single high-frequency transistor between the supply and ground, and which are scalable to future 45 nm, 32 nm, and 22 nm CMOS nodes. The transceiver is fabricated in a 65 nm CMOS process with a digital back-end. It includes a receiver with 14.7 dB gain and 5.6 dB noise figure, a 60 GHz LO distribution tree, a 69 GHz static frequency divider, and a direct BPSK modulator operating over the 55–65 GHz band at data rates exceeding 6 Gb/s. With both the transmitter and the receiver turned on, the chip consumes 374 mW from 1.2 V which reduces to 232 mW for a 1.0 V supply. It occupies 1.28$,times,$0.81 mm$^{2}$. The transceiver and its building blocks were characterized over temperature up to 85$^{circ}$ C and for power supplies down to 1 V. A manufacturability study of 60 GHz radio circuits is presented with measurements of transistors, the low-noise amplifier, and the receiver on slow, typical, and fast process splits. The transceiver architecture and performance were validated in a 1–6 Gb/s 2-meter wireless transmit-receive link over the 55–64 GHz range.      

A Low Noise Figure 1.2-V CMOS GPS Receiver Integrated as a Part of a Multimode Receiver

This paper presents what kind of challenges are posed when a global positioning system (GPS) receiver is being added to a multiradio terminal. The GPS receiver chain is integrated as a part of a multiband and multimode receiver, designed for global system for mobile communications (GSM) and wideband code division multiple access (WCDMA). The hostile radio environment challenges in a terminal level are discussed. Especially, the modifications of the additional GPS mode to an existing receiver ASIC with minor and most necessary changes to the implementation is discussed and presented. The IC is implemented in a 0.13-mum CMOS technology without any analog options. At 1.2-V supply voltage and total power dissipation of 49 mW for the analog signal path, the proposed GPS receiver features a noise figure of 2.2 dB and an out-of-band IIP3 of +24 dBm for the worst-case test scenario, which makes it suitable to cellular handset usage in a demanding interference environment.     

一种适用于无源超高频射频识别标签的低电压低功耗射频/模拟前端电路

提出了一种适用于无源超高频射频识别标签的低电压低功耗射频/模拟前端电路.通过引入一个使用亚阈值技术的基准源,电路实现了温度补偿,从而使得系统时钟在～40～100℃的范围内保持稳定.在模块设计中,提出了一些新的电路结构来降低系统功耗,其中包括一种零静态功耗的上电复位电路和一种新的稳压电路.该射频/模拟前端电路采用不带肖特基二极管0.18μm CMOS EEP-ROM工艺流片实现,它与数字基带、EEPROM一起实现了一个完整的标签芯片.测试结果表明,该芯片的最低电源电压要求为0.75V.在该最低电压下,射频/模拟前端电路的总电流为4.6μA.     

49 mW 5 Gbit/s CMOS receiver for 60 GHz impulse radio

A 5 Gbit/s CMOS receiver for 60 GHz impulse radio is realised. It contains a fully differential envelope detector for differential inputs, a current mode offset canceller for robustness against PVT variations, and a high-speed comparator with hysteresis for noise immunity. The receiver is fabricated using a 90 nm CMOS process with a size of 950 x 750 spl mu/m. The total power consumption of the receiver is 49 mW at 5 Gbit/s.     

Two 1-V Fully Differential CMOS Switched-Capacitor Amplifiers

Two 1-V fully differential CMOS switched-capacitor amplifiers in a standard CMOS 0.35-μm technology are presented. The improved bootstrapped switches are used to allow rail-to-rail signal swing. The circuit design of the major building blocks is described. The performance of these two circuits is demonstrated by experimental results.     

Efficient current reuse for low-power transceivers

Current boosting is a method where the performance of an active circuit block is optimized by placing a constant current source in parallel with the active signal path to provide optimal biasing for different components. In this paper, a technique to replace the constant dc current source with active building blocks typically required in transceivers is proposed. By using this method the total current consumption of the transceiver can be efficiently reduced without modifying its performance. A design example where the proposed technique reduces the receiver current consumption by 45% is given.     

An ultra-wideband transceiver architecture for low power, low rate, wireless systems

This paper presents the system architecture, modeling, and design constraints for a baseband, integrated, CMOS, impulse ultra-wideband transceiver targeting very low power consumption on the order of 1 mW. Intended for a sensor network application, the radio supports low communication rates (/spl sim/100 kpbs) and ranging capabilities over short distances (/spl sim/10 m). Based on a "mostly digital" architecture, the analog complexity is reduced by moving the A/D convertor as close to the antenna as is reasonable. Pulses are generated from simple digital switches, overlaying the signal energy on the lower FCC UWB band (0-960 MHz). Reception is achieved using baseband gain blocks feeding a time-interleaved bank of low resolution A/D converters. A window of energy is captured in time and fed to the digital backend for processing. To save power and area, the digital backend implements only a pulse template correlation filter block overlaid with an additional spreading code. As a pulse template is used, no specific channel estimation or interference cancellation is assumed. The system performance is quantified for this case and implementation tradeoffs are explored with a strong focus on reducing power consumption. In particular, the issues of modulation choice, clock generation, gain and noise figure, ADC resolution, and digital signal processing requirements will be discussed.