An accurate gate length extraction method for sub-quarter micronMOSFET's

By comparing measured and simulated gate-to-source/drain capacitances, C_gds, an accurate gate length extraction method is proposed for sub-quarter micron MOSFET's applications. We show that by including the 2-D field effect on the fringing capacitance, the polysilicon depletion and the quantum-well effects in the C_gds simulation, the polysilicon gate length, L_poly, can be accurately determined for device lengths down to the 0.1 μm regime. The accuracy of this method approaches that of cross-sectional TEM on the device under test, but without destroying the device. Furthermore, we note that as a result of accurate L_poly extraction, the source/drain lateral diffusion length, L_diff , and effective channel length, L_eff, can also be determined precisely. The accuracy of L_diff is confirmed by examining their consistency with experimentally obtained 2-D source/drain profile     

Self-aligned bottom-gate submicrometer-channel-length a-Si-:Hthin-film transistors

Fully self-aligned bottom-gate thin-film transistors (TFTs) fabricated by using a back substrate exposure technique combined with a metal lift-off process are discussed. Ohmic contact to the sources and drains is accomplished by a 40-nm-thick layer of phosphorous-doped microcrystalline silicon. Devices with channel lengths ranging from 0.4 to 12 μm are processed with overlap dimensions between the gate and the source and the gate and the drain ranging from 0.0 to 1.0 μm. Analysis of the conductance data in the linear voltage regime reveals a parasitic drain-to-channel and source-to-channel resistance that is 14% of the channel resistance for a 10-μm device and 140% for a 1-μm device. Thus, increase in the device speed caused by reducing the channel length does not follow expected behavior. A similar situation exists in the nonlinear regime. The on-current of the devices starts to saturate below channel lengths of 2 μm. Current on/off ratios taken at V_d=5 V and V_G=15 V and 0 V, respectively, are approximately 1×10⁶ for the 1- and 12-μm-long devices. The on/off ratio is reduced to 1×10⁵ for the 0.4-μm device     

The effects of source/drain resistance on deep submicrometer deviceperformance

As MOSFET channel lengths approach the deep-submicrometer regime, performance degradation due to parasitic source/drain resistance (R _sd) becomes an important factor to consider in device scaling. The effects of R_sd on the device performance of deep-submicrometer non-LDD (lightly doped drain) n-channel MOSFETs are examined. Reduction in the measured saturation drain current (R_sd=600 Ω-μm) relative to the ideal saturation current (R_sd=0.0 Ω-μm) is about 4% for L_eff=0.7 μm and T_ox =15.6 nm and 10% for L_eff=0.3 μm and T _ox=8.6 nm. Reduction of current in the linear regime and reduction of the simulated ring oscillator speed are both about three times higher. The effect of salicide technologies on device performance is discussed. Projections are made of the ultimate achievable performance     

Verification of saturation velocity lowering in MOSFET's inversionlayer

With reduction of the MOSFET's channel length L, the drain saturation current of MOSFET's is determined by the saturation velocity v_sat in the inversion layer. Hence, the modeling of v_sat becomes very important. In this paper, v_sat in the inversion layer has been examined by using simulation experiment. New parameter values for v_sat model in the inversion layer are proposed. In order to verify the v_sat model, the impurity profiles of MOSFET's are calibrated to fit the threshold voltage V_th-L characteristics. Then, we validate new v_sat model by comparing the experiments of I_D-V_D characteristics of 0.35-μm CMOS with the simulations using the energy transport model (ETM)     

Enhanced corrugated QWIP performance using dielectric coverage

We report here the effect of dielectric/metal coverage on the performance of the corrugated quantum well infrared photodetectors (C-QWIP) in two wavelength regimes. We found that with proper dielectrics, both the detector dark current and the spectral responsivity can he improved upon the monitoring 45° edge coupled QWIP. In the 8 μm regime, the normalized responsivity of a Si₃ N₄ covered C-QWIP was found to be improved by 3.3 times. In the 14 μm regime, the improvement is a factor of 1.8 using Si₃N₄ coverage and a factor of 2.5 using SiO₂ coverage     

Velocity saturation in the extrinsic device: a fundamental limit inHFET's

We have carried out an experimental study revealing that velocity saturation (υ_sat) occurring in both the extrinsic source and drain sets a fundamental limit on maximum drain current and useful gate swing in HFET's. Using AlGaAs/n⁺-InGaAs HFET's as a vehicle, we find that first g_m and eventually f_T decline at high currents in two stages. Initially, the approach of υ_sat in the extrinsic device causes the small-signal source and drain resistances (r_s and r_d) to rise dramatically, primarily degrading g_m. As the current increases further, the large-signal source and drain resistances (R_s and R_d) grow significantly as well, pushing the intrinsic HFET toward the linear regime. Combined with the rapid rise of r_s and r_d, the accompanying increase in gate-drain capacitance forces f_T to decline through a strongly enhanced Miller effect. We associate this two-fold mechanism with a new regime of HFET operation, which we call the parasitic-resistance blow-up regime     

Magnetotransport phenomena in single AlGaAs/GaAs quantum wires grown on laterally patterned substrates

Single, sub-micrometer wide quantum wires have been fabricated using molecular beam epitaxy on mesa-etched GaAs substrates, where the GaAs wire is embedded in AlGaAs. By using a Hall bar pattern, potential probes were directly attached to the wires while grown. To avoid problems associated with anisotropic etching and regrowth, the wire structures were oriented along the 100 crystallographic directions. From this fabrication technique, described in detail by Shitara et al., Appl. Phys. Lett. 66, 2385 (1995), one can expect the formation of high quality “self-aligned” quantum wires with a confinement potential determined by the conduction band discontinuity of AlGaAs and GaAs. Here we study the four-point magnetoresistance of 50 μm long single quantum wires with widths between 250 and 700 nm from 1.3 to 21 K. A distinct weak localization peak and universal conductance fluctuations dominate the low magnetic field regime and are used to estimate the phase-coherence length of the electrons. Pronounced 1/B periodic quantum oscillations at magnetic fields above 1 T are consistent with the picture of wires with a square-well shaped confining potential.     

DIBL considerations of extended drain structure for 0.1 μmMOSFET's

The drain-induced-barrier-lowering (DIBL) considerations of the extended drain structure were studied using two-dimensional (2-D) device simulations in the tenth-micrometer regime. We found that the drain extension length must be kept at a minimum in order to reduce the transistor cell area and to improve the device transconductance, G_m . However, without decreasing the deep source/drain junction depth, the minimum value of which is basically limited by the ability to form a good low resistive silicide contact, charge sharing associated with a small extension length deteriorates the short channel behavior of the device, via DIBL, even if aggressive scaling of the gate oxide thickness and the junction depth of the drain extension were used. The solution to this dilemma would be elevating the source/drain area by selective epitaxy to form a shallow, low resistive silicided junction. We propose here a novel device structure using the elevated silicide-as-a-diffusion-source (E-SADS), which improves the DIBL-G_m tradeoff, eliminates the contact problem, and maintains a minimal cell areal increase     

Metamorphic InAlAs/InGaAs HEMTs on GaAs substrates with a novelcomposite channels design

We report on fabrication and performance of novel 0.13 μm T-gate metamorphic InAlAs/InGaAs HEMTs on GaAs substrates with composite InGaAs channels, combining the superior transport properties of In_0.52Ga_0.48As with low-impact ionization in the In_0.32Ga_0.68As subchannel. These devices exhibit excellent DC characteristics, high drain currents of 750 mA/mm, extrinsic transconductances of 600 mS/mm, combined with still very low output conductance values of 20 mS/mm, and high channel and gate breakdown voltages. The use of a composite InGaAs channels leads to excellent cut-off frequencies: f_max of 350 GHz and an f_T 160 GHz at V_DS=1.5 V. These are the best microwave frequency results ever reported for any FET on GaAs substrate     

Theory of the MOS transistor in weak inversion-new method to determine the number of surface states

The drain current IDversus gate voltage VGof an MOST operating in weak inversion, and the influence of surface potential fluctuations on this characteristic have been studied before [1], [2]. The purpose of this paper is to derive an expression of the drain current IDversus the drain voltage VDfor devices with a channel length not smaller than 20 µm. It is demonstrated that the surface potential fluctuations do not affect the slope of the ID-VDcurve, whereas the density Nssof surface states strongly influences the slope for small drain voltages. This yields a simple and useful technique to determine Nsson MOS transistors.     

Ga2O3(Gd2O3)/InGaAsenhancement-mode n-channel MOSFETs

We have demonstrated the first Ga₂O₃(Gd₂O₃) insulated gate n-channel enhancement-mode In_0.53Ga_0.47As MOSFET's on InP semi-insulating substrate. Ga₂O₃(Gd₂ O₃) was electron beam deposited from a high purity single crystal Ga₅Gd₃O₁₂ source. The source and drain regions of the device were selectively implanted with Si to produce low resistance ohmic contacts. A 0.75-μm gate length device exhibits an extrinsic transconductance of 190 mS/mm, which is an order of magnitude improvement over previously reported enhancement-mode InGaAs MISFETs. The current gain cutoff frequency, f_t, and the maximum frequency of oscillation, f_max, of 7 and 10 GHz were obtained, respectively, for a 0.75×100 μm² gate dimension device at a gate voltage of 3 V and drain voltage of 2 V     

Low-voltage hot-electron currents and degradation indeep-submicrometer MOSFETs

Hot-electron currents and degradation in deep submicrometer MOSFETs at 3.3 V and below are studied. Using a device with L _eff=0.15 μm and T_ox=7.5 nm, substrate current is measured at a drain bias as low as 0.7 V; gate current is measured at a drain bias as low as 1.75 V. Using the charge-pumping technique, hot-electron degradation is also observed at drain biases as low as 1.8 V. These voltages are believed to be the lowest reported values for which hot-electron currents and degradation have been directly observed. These low-voltage hot-electron phenomena exhibit similar behavior to hot-electron effects present at higher biases and longer channel lengths. No critical voltage for hot-electron effects (such as the Si-SiO₂ barrier height) is apparent. Established hot-electron degradation concepts and models are shown to be applicable in the low-voltage deep submicrometer regime. Using these established models, the maximum allowable power supply voltage to insure a 10-year device lifetime is determined as a function of channel length (down to 0.15 μm) and oxide thicknesses     

Design of Si/SiGe heterojunction complementarymetal-oxide-semiconductor transistors

An optimized Si/SiGe heterostructure for complementary metal-oxide semiconductor (CMOS) transistor operation is presented. Unlike previous proposals, the design is planar and avoids inversion of the Si layer at the oxide interface. The design consists of a relaxed Si_0.7Ge _0.3 buffer, a strained Si quantum well (the electron channel), and a strained S_1-xGe_x (0.7>x>0.5) quantum well (the hole channel). The channel charge distribution is predicted using a 1-D analytical model and quantum mechanical solutions. Transport is modeled using 2-D drift-diffusion and hydrodynamic numerical simulations. An almost symmetric performance of p- and n-transistors with good short-channel behavior is predicted. Simulated ring oscillators show a 4- to 6-fold reduction in power-delay product compared to bulk Si CMOS at the 0.2-μm channel length generation     

Bias dependence of fT and fmax in anIn0.52Al0.48As/n+-In0.53Ga0.47As MISFET

Detailed microwave characterization of a recently fabricated In _0.52Al_0.48As/n⁺-In_0.53Ga _0.47As MISFET reveals that high values of current-gain cutoff frequency (f_T) and unilateral-gain cutoff frequency (f_max) are obtained for a broad range of gate bias voltage values. A significant peak in f_T and f _max has also been observed at high gate-source bias values. The peak coincides with the onset of electron accumulation at the heterointerface and is attributed to reduced ionized impurity scattering coupled with reduced drain conductance. This result suggests an improved device structure that optimizes operation in the accumulation regime     

Demonstration of submicron depletion-mode GaAs MOSFETs withnegligible drain current drift and hysteresis

We successfully fabricated submicron depletion-mode GaAs MOSFETs with negligible hysteresis and drift in drain current using Ga₂ O₃(Gd₂O₃) as the gate oxide. The 0.8-μm gate-length device shows a maximum drain current density of 450 mA/mm and a peak extrinsic transconductance of 130 mS/mm. A short-circuit current gain cutoff frequency (f_T) of 17 GHz and a maximum oscillation frequency (f_max) of 60 GHz were obtained from the 0.8 μm×60 μm device. The absence of drain current drift and hysteresis along with excellent characteristics in the submicron devices is a significant advance toward the manufacture of commercially useful GaAs MOSFETs     

Characteristics of field-induced-drain (FID) poly-Si TFTs with highon/off current ratio

The characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) with a field-induction-drain (FID) structure using an inversion layer as a drain are investigated. The FID structure not only reduces the anomalous leakage current, but also maintains a high on current. An off current of 1.5 pA/μm and an on/off current ratio of 10⁷ (V_d=10, V_g =-20 V) are successfully obtained. These characteristics result from good junction characteristics between the p channel and n⁺ inversion layer. Reducing the threshold voltage of the FID region allows a simple circuit configuration for the FID TFTs     

Electrical characteristics of an optically controlled N-channelAlGaAs/GaAs/InGaAs pseudomorphic HEMT

Electrical characteristics of an n-channel Al_0.3Ga_0.7As/GaAs/In_0.13Ga_0.87 As pseudomorphic HEMT (PHEMT) with L_g=1 μm on GaAs are characterized under optical input (P_opt). Gate leakage and drain current have been analyzed as a function of V_GS, V _DS, and P_opt. We observed monotonically increasing gate leakage current due to the energy barrier lowering by the optically induced photovoltage, which means that gate input characteristics are significantly limited by the photovoltaic effect. However, we obtained a strong nonlinear photoresponsivity of the drain current, which is limited by the photoconductive effect. We also proposed a device model with an optically induced parasitic Al_0.3Ga_0.7As MESFET parallel to the In_0.13Ga_0.87As channel PHEMT for the physical mechanism in the drain current saturation under high optical input power     

High-transconductance insulating-gate InP/InGaAs buried p-bufferDH-MODFETs grown by MOVPE

Buried p-buffer double heterostructure modulation-doped field-effect transistors (BP DH-MODFETs) with an InGaAs quantum-well channel were fabricated with high transconductance and good breakdown voltage, by placing the metal gate directly on Fe-doped InP insulating layer. Excellent extrinsic DC transconductance of 560 mS/mm and a high gate-to-drain diode breakdown voltage (greater than 20 V) were achieved at room temperature with FETs of 1.2-μm gate length. Unity currently gain cutoff frequency f_T of 24 GHz and maximum oscillation frequency f_max of 60 GHz were demonstrated for a drain to source voltage V_DS=4 V, which corresponds to an average electron velocity of 2.2×10⁷ cm/s in the quantum well     

Optimum design and fabrication of InAlAs/InGaAs HEMT's on GaAs withboth high breakdown voltage and high maximum frequency of oscillation

A simple model to describe the dependence of the breakdown voltage between gate and drain on width of the gate recess in an InAlAs/InGaAs high electron mobility transistor (HEMT) is presented. In this model, the depletion region laterally spreads to the drain region. It enables us to express the dependence of device parameters on the width of the gate recess. The model suggests that the breakdown voltage increases with the width of the gate recess and then saturates, which is experimentally confirmed. Calculations based on the model show that the maximum frequency of oscillation (f_max) also increases with the width of the gate-recess due to the reduction in both the drain conductance and the gate-to-drain capacitance, and then slightly decreases with the width due to the increase in the source resistance. We fabricated InAlAs/InGaAs HEMT's lattice-mismatched on GaAs substrates with optimum recess-width, and these exhibited both a high breakdown voltage of 14 V and a high f_max of 127 GHz at a gate length of 0.66 μm     

Utilization of an electron beam resist process to examine theeffects of asymmetric gate recess on the device characteristics ofAlGaAs/InGaAs PHEMTs

The DC and microwave characteristics of two sets of AlGaAs/InGaAs PHEMTs having a gate length of 0.2 μm are compared. The first set is composed of devices fabricated using a trilayer electron beam resist process for T-gate recess and metallization. The second set is composed of devices fabricated using a new four-layer electron beam resist process which enables the asymmetric placement of a T-gate in a wide recess trench. Devices fabricated using the four-layer resist process showed improved breakdown voltage, lower gate-drain feedback capacitance, lower output conductance, and higher f_max with only slight reduction of drain current and transconductance. For example, the off-state drain-source breakdown voltage increased from 5.2 to 12.5 V, and the f_max, increased from 133 to 158 GHz as the drain side cap recess, L_ud, was increased from 0 to 0.55 μm