A 1.5-V direct digital synthesizer with tunable delta-sigma modulator in 0.13-/spl mu/m CMOS

In direct digital synthesizer (DDS) applications, the drawback of the conventional delta sigma (/spl Delta//spl Sigma/) modulator structure is that its signal band is fixed. In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the DDS output frequency. We use a hardware-efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with 16 equal-length piecewise second-degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with an output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter full-scale output current: 11.5 mA).     

A 200 MHz quadrature digital synthesizer/mixer in 0.8 μm CMOS

A 200 MHz quadrature direct digital frequency synthesizer/complex mixer (QDDFSM) chip is presented. The chip synthesizes 12 b sine and cosine waveforms with a spectral purity of -84.3 dBc. The frequency resolution is 0.047 Hz with a corresponding switching speed of 5 ns and a tuning latency of 14 clock cycles. The chip is also capable of frequency, phase, and quadrature amplitude modulation. These modulation capabilities operate up to the maximum clocking frequency. The chip provides the capability of parallel operation of multiple chips with throughputs up to 800 MHz. The 0.8 μm triple level metal N-well CMOS chip has a complexity of 52000 transistors with a core area of 2.6×6.1 mm². Power dissipation is 2 W at 200 MHz and 5 V     

A low-voltage folded-switching mixer in 0.18-/spl mu/m CMOS

Scaling of CMOS technologies has a great impact on analog design. The most severe consequence is the reduction of the voltage supply. In this paper, a low voltage, low power, AC-coupled folded-switching mixer with current-reuse is presented. The main advantages of the introduced mixer topology are: high voltage gain, moderate noise figure, moderate linearity, and operation at low supply voltages. Insight into the mixer operation is given by analyzing voltage gain, noise figure (NF), linearity (IIP3), and DC stability. The mixer is designed and implemented in 0.18-/spl mu/m CMOS technology with metal-insulator-metal (MIM) capacitors as an option. The active chip area is 160 /spl mu/m/spl times/200 /spl mu/m. At 2.4 GHz a single side band (SSB) noise figure of 13.9 dB, a voltage gain of 11.9 dB and an IIP3 of -3 dBm are measured at a supply voltage of 1 V and with a power consumption of only 3.2 mW. At a supply voltage of 1.8 V, an SSB noise figure of 12.9 dB, a voltage gain of 16 dB and an IIP3 of 1 dBm are measured at a power consumption of 8.1 mW.     

A low-power oscillator mixer in 0.18-/spl mu/m CMOS technology

A downconversion double-balanced oscillator mixer using 0.18-/spl mu/m CMOS technology is proposed in this paper. This oscillator mixer consists of an individual mixer stacked on a voltage-controlled oscillator (VCO). The stacked structure allows entire mixer current to be reused by the VCO cross-coupled pair to reduce the total current consumption of the individual VCO and mixer. Using individual supply voltages and eliminating the tail current source, the stacked topology requires 1.0-V low supply voltage. The oscillator mixer achieves a voltage conversion gain of 10.9 dB at 4.2-GHz RF frequency. The oscillator mixer exhibits a tuning range of 11.5% and a single-sideband noise figure of 14.5 dB. The dc power consumption is 0.2 mW for the mixer and 2.94 mW for the VCO. This oscillator mixer requires a lower supply voltage and achieves a higher operating frequency among recently reported Si-based self-oscillating mixers and mixer oscillators. The mixer in this oscillator mixer also achieves a low power consumption compared with recently reported low-power mixers.     

A 285-MHz pipelined MAP decoder in 0.18-/spl mu/m CMOS

Presented in this paper is a pipelined 285-MHz maximum a posteriori probability (MAP) decoder IC. The 8.7-mm/sup 2/ IC is implemented in a 1.8-V 0.18-/spl mu/m CMOS technology and consumes 330 mW at maximum frequency. The MAP decoder chip features a block-interleaved pipelined architecture, which enables the pipelining of the add-compare-select kernels. Measured results indicate that a turbo decoder based on the presented MAP decoder core can achieve: 1) a decoding throughput of 27.6 Mb/s with an energy-efficiency of 2.36 nJ/b/iter; 2) the highest clock frequency compared to existing 0.18-/spl mu/m designs with the smallest area; and 3) comparable throughput with an area reduction of 3-4.3/spl times/ with reference to a look-ahead based high-speed design (Radix-4 design), and a parallel architecture.     

A 17-mW transmitter and frequency synthesizer for 900-MHz GSM fully integrated in 0.35-/spl mu/m CMOS

A fractional-N phase-locked loop (PLL) serves as a Gaussian minimum-shift keying (GMSK) transmitter and a receive frequency synthesizer for GSM. The entire transmitter/synthesizer is fully integrated in 0.35-/spl mu/m CMOS and consumes 17.4 and 12 mW from 2.5 V in the transmit and receive modes, respectively, including an on-chip voltage-controlled oscillator. The circuit meets GSM specifications on modulation accuracy in transmit mode, and measured phase noise from the closed-loop PLL is -148 dBc/Hz and -162 dBc/Hz, respectively, at 3- and 20-MHz offset. Worst case spur at 13-MHz offset is -77 dBc.     

A fast switching PLL frequency synthesizer with an on-chip passive discrete-time loop filter in 0.25-/spl mu/m CMOS

A phase-locked loop (PLL) frequency synthesizer with an on-chip passive discrete-time loop filter is reported in this paper. The closed loop is robust stable, and a fast switching speed is achieved by creating a stabilization zero in the discrete-time domain. The circuit implementations and system-level analysis results of the proposed architecture are presented. Techniques and design considerations are presented to overcome several potential problems of the proposed architecture, such as finite lock-in range, translation of voltage-controlled oscillator noise into in-band phase noise, and spur degradation due to clock feedthrough of the sampling switch. A 2.4 GHz prototype frequency synthesizer for Bluetooth applications was developed in a 0.25-/spl mu/m CMOS process. The measured results agree with theoretical predictions and demonstrate its high performance.     

A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-/spl mu/m digital CMOS process

This brief describes the design of a frequency synthesizer for 2.3/4.6-GHz wireless applications in a 0.35-/spl mu/m digital CMOS process. This synthesizer provides dual-band output signals by means of frequency doubling techniques. Output frequency of the proposed synthesizer ranges from 1.87-2.3 GHz, and 3.74-4.6GHz. This chip consumes a total power of 80 mW from a single 2-V supply, including 45 mW for dual-band output buffers. Core size is 2200 /spl mu/m/spl times/1600 /spl mu/m.     

A 10.7-MHz sixth-order SC ladder filter in 0.35-/spl mu/m CMOS technology

A sixth-order 10.7-MHz bandpass switched-capacitor filter based on a double terminated ladder filter is presented. The filter uses a multipath operational transconductance amplifier (OTA) that presents both better accuracy and higher slew rate than previously reported Class-A OTA topologies. Design techniques based on charge cancellation and slower clocks are used to reduce the overall capacitance from 782 down to 219 unity capacitors. The filter's center frequency and bandwidth are 10.7 MHz and 400 kHz, respectively, and a passband ripple of 1 dB in the entire passband. The quality factor of the resonators used as filter terminations is around 32. The measured (filter + buffer) third-intermodulation (IM3) distortion is less than -40 dB for a two-tone input signal of +3-dBm power level each. The signal-to-noise ratio is roughly 58 dB while the IM3 is -45 dB; the power consumption for the standalone filter is 42 mW. The chip was fabricated in a 0.35-/spl mu/m CMOS process; filter's area is 0.84 mm/sup 2/.     

An 800-MHz quadrature digital synthesizer with ECL-compatibleoutput drivers in 0.8 μm CMOS

An 800 MHz quadrature direct digital frequency synthesizer (QDDFS4) chip is presented. The chip synthesizes 12 b sine and cosine waveforms with a spectral purity of -84.3 dBc, The frequency resolution is 0.188 Hz with a corresponding switching speed of 5 ns and a tuning latency of 47 clock cycles. The chip is also capable of frequency and phase modulation. ECL-compatible output drivers are provided to facilitate I/O compatibility with other high speed devices. A high gain amplifier at the clock input enables the QDDFS4 chip to be clocked with ac-coupled RF signal sources with peak-to-peak voltage swings as small as 0.5 V. The 0.8 μm triple level metal N well CMOS chip has a complexity of 94000 transistors with a core area of 5.9×6.7 mm². Power dissipation is 3 W at 800 MHz and 5 V     

A cellular-band CDMA 0.25-/spl mu/m CMOS LNA linearized using active post-distortion

The theory of a linearization method using active post-distortion (APD) is explained for low-frequency and high-frequency applications. The low-frequency cancellation is explained in power series format and the high-frequency cancellation is explained in Volterra series format. The method is utilized for a cellular band (869-894 MHz) CDMA low-noise amplifier (LNA), which is implemented in 0.25-/spl mu/m CMOS process. The LNA achieves 1.2 dB NF, 16.2 dB power gain, and +8 dBm IIP3 while consuming 12 mA current from 2.6 V supply voltage. It shows 13.5 dB of IM3 product reduction with 0.15 dB NF penalty in comparison with an LNA which does not use the APD method.     

A 9-50-GHz Gilbert-cell down-conversion mixer in 0.13-/spl mu/m CMOS technology

A broadband microwave/millimeter-wave (MMW) Gilbert-cellmixer using standard 1P8M 0.13-/spl mu/m complementary metal oxide semiconductor (CMOS) technology is presented in this letter. Two radio frequency (RF) transformer baluns are used in RF-and local oscillator (LO)-ports to convert single-ended signals to differential signals. Thin film microstrip line is employed for the matching networks and transformer design. This mixer has a conversion gain of better than 5dB from 9 to 50GHz. Between 5 and 50GHz,the RF- and LO-to-intermediate frequency (IF) isolations are better than 40dB. The RF-to-LO and LO-to-RF isolations are all better than 20dB. To the authors' knowledge, this is the first CMOS Gilbert-cell mixer operating to MMW frequency to date.     

A 100-MHz 8-mW ROM-less quadrature direct digital frequency synthesizer

A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values as in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications. To demonstrate the proposed technique, a quadrature DDFS has been implemented using 0.5-/spl mu/m CMOS process and occupies an active area of 1.4 mm/sup 2/. It consumes 8 mW at 100 MHz and operates from a single 2.7-V supply. The spurious-free dynamic range is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz.     

A high-voltage output driver in a 2.5-V 0.25-/spl mu/m CMOS technology

The design of a high-voltage output driver in a digital 0.25-/spl mu/m 2.5-V technology is presented. The use of stacked devices with a self-biased cascode topology allows the driver to operate at three times the nominal supply voltage. Oxide stress and hot carrier degradation is minimized since the driver operates within the voltage limits imposed by the design rules of a mainstream CMOS technology. The proposed high-voltage architecture uses a switching output stage. The realized prototype delivers an output swing of 6.46 V to a 50-/spl Omega/ load with a 7.5-V supply and an input square wave of 10 MHz. A PWM signal with a dual-tone sinusoid at 70 kHz and 250 kHz results in an IM3 of -65 dB and an IM2 of -67 dB. The on-resistance is 5.9 /spl Omega/.     

A 3-to-8-GHz fast-hopping frequency synthesizer in 0.18-/spl mu/m CMOS technology

A frequency synthesizer incorporating one single-sideband (SSB) mixer generates seven bands of clock distributed from 3 to 8GHz with 1-ns switching time. An efficient frequency synthesizing technique producing balanced bands around one center frequency is employed, and the SSB mixer uses double degeneration topology to increase the linearity. Fabricated in 0.18-/spl mu/m CMOS technology, this circuit achieves a sideband rejection of 37 dB while consuming 48 mW from a 2.2-V supply.     

A multimode 0.3-200-kb/s transceiver for the 433/868/915-MHz bands in 0.25-/spl mu/m CMOS

A fully integrated transceiver suitable for low-data-rate wireless telemetry and sensor networks operating in the license-free ISM frequency bands at 433, 868, or 915 MHz implemented in 0.25-/spl mu/m CMOS is presented. G/FSK, ASK, and OOK modulation formats are supported at data rates from 0.3 to 200 kb/s. The transceiver's analog building blocks include a low-noise amplifier, mixer, channel filter, received signal-strength indication, frequency synthesizer, voltage-controlled oscillator, and power amplifier. FSK demodulation is implemented using a novel digital complex-frequency correlator that operates over a wide modulation-index range and approximates matched filter detection performance. Automatic gain control, automatic frequency control, and symbol timing recovery loops are included on chip. Operating in the 915-MHz band in FSK mode at 9.6 kb/s, the receiver consumes 19.7 mA from a 3-V supply and achieves a sensitivity of -112.8dBm at 0.1% BER. The transmitter consumes 28.5 mA for an output power of 10 dBm and delivers up to 14 dBm.     

A 0.25-/spl mu/m CMOS OPLL transmitter IC for GSM and DCS applications

A single-chip CMOS global system for mobile communications/digital cellular system dual-band offset phase-locked loop (OPLL) transmitter is presented in this paper. This chip includes a quadrature modulator and an OPLL modulation loop. Except for the loop filter and high-power voltage-controlled oscillator (TX VCO), everything is integrated into this chip to form a dual-band transmitter. This transmitter integrated circuit is fabricated in a 0.25-mum CMOS process. The current consumption without the TX VCO is approximately 23 mA under 2.7-V power supply for both bands. The measured rms and peak phase errors for Gaussian minimum shift-keying (GMSK) modulated signals are approximately 1deg and 2.4deg, respectively. The measurements show comparable performance to its BiCMOS counterparts     

A 0.3-25-GHz ultra-wideband mixer using commercial 0.18-/spl mu/m CMOS technology

An ultra-wideband mixer using standard complementary metal oxide semiconductor (CMOS) technology was first proposed in this paper. This broadband mixer achieves measured conversion gain of 11 /spl plusmn/ 1.5 dB with a bandwidth of 0.3 to 25 GHz. The mixer was fabricated in a commercial 0.18-/spl mu/m CMOS technology and demonstrated the highest frequency and bandwidth of operation. It also presented better gain-bandwidth-product performance compared with that of GaAs-based HBT technologies. The chip area is 0.8 /spl times/ 1 mm/sup 2/.     

A K-band down-conversion mixer with 1.4-GHz bandwidth in 0.13-/spl mu/m CMOS technology

A low power and low voltage down conversion mixer working at K-band is designed and fabricated in a 0.13/spl mu/m CMOS logic process. The mixer down converts RF signals from 19GHz to 2.7GHz intermediate frequency. The mixer achieves a conversion gain of 1dB, a very low single side band noise figure of 9dB and third order intermodulation point of -2dBm, while consuming 6.9mW power from a 1.2V supply. The 3-dB conversion gain bandwidth is 1.4GHz, which is almost 50% of the IF. This mixer with small frequency re-tuning can be used for ultra-wide band radars operating in the 22-29GHz band.