Quarter-micrometer SPI (Self-aligned Pocket Implantation) MOSFET'sand its application for low supply voltage operation

A novel SPI (Self-aligned Pocket Implantation) technology has been presented, which improves short channel characteristics without increasing junction capacitance. This technology features a localized pocket implantation using gate electrode and TiSi₂ film as self-aligned masks. An epi substrate is used to decrease the surface impurity concentration in the well while maintaining high latch-up immunity. The SPI and the gate to drain overlapped structure such as LATID (Large-Angle-Tilt Implanted Drain) technology allow use of the ultra low impurity concentration in the channel region, resulting in higher saturation drain current at the same gate over-drive compared to conventional device. The carrier velocity reaches 8×10⁶ cm/sec and subthreshold slope is less than 75 mV/dec, which can be explained by low impurity concentration in the channel and in the substrate. The small gate depletion layer capacitance of SPI MOSFET was estimated by C-V measurement, and it can explain high performance such as small subthreshold slope. On the other hand, the problem and the possibility of low supply voltage operation have been discussed, and it has been proposed that small subthreshold slope is prerequisite for low power device operated at low supply voltage. In addition, the drain junction capacitance of SPI is decreased by 65% for N-MOSFET's, and 69% for P-MOSFET's both compared with conventional devices. This technology yields an unloaded CMOS inverter of 48 psec delay time at the supply voltage of 1.5 V     

P-Type Floating Gate for Retention and P/E Window Improvement of Flash Memory Devices

A flash memory with a lightly doped p-type floating gate is proposed, which improves charge retention and programming/erase (P/E) V_th window. Improvement in P/E window is enhanced for cells with smaller capacitance coupling ratio, which is important for future scaled flash memory cells. Both device simulation and experimental verification are presented.     

Temperature-adaptive voltage scaling for enhanced energy efficiency in subthreshold memory arrays

Static random access memory (SRAM) circuits optimized for minimum energy consumption typically operate in the subthreshold regime with ultra low-power-supply voltages. Both the read and the write propagation delays of a subthreshold memory circuit are significantly reduced with an increase in the die temperature. The excessive timing slack observed in the clock period of constant-frequency subthreshold memory circuits at elevated temperatures provides new opportunities to lower the active-mode energy consumption. Temperature-adaptive dynamic supply voltage tuning (TA-DVS) technique is proposed in this paper to reduce the high-temperature energy consumption of ultra low-voltage subthreshold SRAM arrays. Results indicate that the energy consumption can be lowered by up to 32.8% by dynamically scaling the supply voltage at elevated temperatures. The impact of the temperature-adaptive dynamic supply voltage scaling technique on the data stability of the subthreshold SRAM bit-cells is presented. The effectiveness of the TA-DVS technique under process parameter and supply voltage variations is evaluated. An alternative technique based on temperature-adaptive reverse body bias (TA-RBB) to exponentially reduce the subthreshold leakage currents at elevated temperatures is also investigated. The active-mode energy consumption characteristics of the two temperature-adaptive voltage tuning techniques are compared.     

Exploring Variability and Performance in a Sub-200-mV Processor

In this study, we explore the design of a subthreshold processor for use in ultra-low-energy sensor systems. We describe an 8-bit subthreshold processor that has been designed with energy efficiency as the primary constraint. The processor, which is functional below V_dd=200 mV, consumes only 3.5 pJ/inst at V_dd=350 mV and, under a reverse body bias, draws only 11 nW at V_dd=160 mV. Process and temperature variations in subthreshold circuits can cause dramatic fluctuations in performance and energy consumption and can lead to robustness problems. We investigate the use of body biasing to adapt to process and temperature variations. Test-chip measurements show that body biasing is particularly effective in subthreshold circuits and can eliminate performance variations with minimal energy penalties. Reduced performance is also problematic at low voltages, so we investigate global and local techniques for improving performance while maintaining energy efficiency.     

A Novel Nanowire Channel Poly-Si TFT Functioning as Transistor and Nonvolatile SONOS Memory

In this letter, a polycrystalline silicon thin-film transistor consisting of silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire (NW) channels was investigated for the applications of transistor and nonvolatile memory. The proposed device, which is named as NW SONOS-TFT, has superior electrical characteristics of transistor, including a higher drain current, a smaller threshold voltage (V_th) , and a steeper subthreshold slope. Moreover, the NW SONOS-TFT also can exhibit high program/erase efficiency under adequate bias operation. The duality of both transistor and memory device for the NW SONOS-TFT can be attributed to the trigate structure and channel corner effect.     

Subthreshold behavior of uniformly and nonuniformly doped long-channel MOSFET

The subthreshold turnoff behavior of the long-channel MOSFET (metal-oxide-semiconductor field-effect transistor) is characterized by the gate bias swingSneeded to reduce the subthreshold current one decade. Here a simple formula for S is derived which includes source-to-substrate reverse bias and ion-implanted doping profile effects. For uniformly doped structures it is shown that curves of givenScan be constructed on an oxide thickness versus doping level plot, making estimates ofSfor any choice of these parameters particularly simple. A separate family of curves is needed for each value of source-to-substrate bias VS. Source-to-substrate reverse bias greatly reduces S in devices with large S values, but cannot reduce S to its theoretical minimum value,S_{min} = (kT/q)ln 10, at reasonable values of VS. It is found that the effect of nonuniform doping is determined mainly by the dose and centroid of the depleted portion of the excess surface doping, provided buried channels do not occur and provided the implant is not primarily located in the inversion layer itself. Higher doses and deeper implants increaseS. The maximum value ofSfor a given implant dose and source-to-substrate reverse bias occurs for that range of implantation which places the implant near the depletion edge. Consequently, the use of implants in small MOSFET's to control threshold punchthrough and parasitic capacitances will cause turnoff degradation.     

An automatic temperature compensation of internal sense ground forsubquarter micron DRAM's

This paper describes DRAM array driving techniques and the parameter scaling techniques for low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. Temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current for a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from the leakage current problem and the influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (V _th), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the V_th of the MC-Tr simply (0.45 V at K=0.4) for the satisfaction of the small leakage current, for high speed and stable operation, and for high reliability (V_PP is below 2 V_CC). They are applicable to subquarter micron DRAM's of 256 Mb and more     

MOS transistors with a forward-biased source-substrate junction

The electrical characteristics of p-channel MOSTs (metal-oxide-semiconductor) with a source-to-substrate forward voltage are studied. A sizeable magneto-electrical effect in the channel is established, when a weak magnetic induction perpendicular to the drain current and parallel to Si---SiO₂ interface is applied. The experimental results reported at room and liquid nitrogen temperature are briefly discussed.     

Body bias dependence of 1/f noise in NMOS transistors fromdeep-subthreshold to strong inversion

Dependence of 1/f noise on the body-to-source junction bias voltages (V_BS) between -2.5 and 0.5 V for 0.25-μm NMOS transistors is reported. In subthreshold, 1/f noise is reduced by about one order of magnitude, when the body-to-source junction is forward biased by 0.5 V (V_BS) compared to that for V_BS=0 V, which is due to increased depletion layer capacitance as well as possibly due to an increased average distance between oxide traps and carriers caused by the forward bias. On the contrary, in strong inversion, 1/f noise remains almost constant for the entire V_BS range     

Multi-bias capacitance voltage characteristic of AlGaN/GaN HEMT

The method of multi-bias capacitance voltage measurement is presented. The physical meaning of gate-source and gate-drain capacitances in AlGaN/GaN HEMT and the variations in them with different bias con-ditions are discussed. A capacitance model is proposed to reflect the behaviors of the gate-source and gate-drain ca-pacitances, which shows a good agreement with the measured capacitances, and the power performance obtains good results compared with the measured data from the capacitance model.     

Modeling of $V_{rm th}$ Shift in nand Flash-Memory Cell Device Considering Crosstalk and Short-Channel Effects

A threshold-voltage (V_th) shift of sub-100-nm NAND flash-memory cell transistors was modeled systematically, and the modeling was verified by comparing with the data from measurement and 3-D device simulation. The V_th shift of the NAND flash-memory cell was investigated by changing parameters such as gate length, width, drain voltage, dielectric material between cells, space between cells, lightly doped-drain depth, and adjacent-cell bias. The proposed model covers two dominant device physics: capacitance coupling effect between adjacent cells and short-channel effect. Our model showed an accurate prediction of the V_th shift of NAND flash-memory array and a good agreement with the data from simulation and measurement.     

AlGaN/GaN HEMT多偏置下CV特性的研究

电容电压特性是分析半导体器件性能的一个有效手段,而且是GaN HEMT器件大信号模型建模的重要步骤之一。本文提出一种多偏置电容电压的测试方法,并讨论了Cgs和Cgd的物理意义及其随偏置电压Vgs和Vds的变化规律。提出一种能够反映Cgs和Cgd特性的电容模型,与测试电容数据有很好的拟合效果,并且用器件的功率特性验证了该电容模型在非线性仿真的准确性。     

A double-level-Vth select gate array architecture formultilevel NAND flash memories

In multilevel flash memories, the threshold voltages of the memory cells should be controlled precisely. This paper describes how in a conventional NAND flash memory, the threshold voltages of the memory cells fluctuate due to array noise during the bit-by-bit program verify operation, and as a result, the threshold voltage distribution becomes wider. This paper describes a new array architecture, “A double-level-V_th select gate array architecture” to eliminate the array noise, together with a reduction of the cell area. The array noise is mainly caused by interbitline capacitive coupling noise and by the high resistance of the diffused source-line. The threshold voltage fluctuation can be as much as 0.7 V in a conventional array. In the proposed array, bitlines are alternately selected, and the unselected bitlines are used as low resistance source-lines. Moreover, the unselected bitlines form a shield between the neighboring selected bitlines. As a result, the array noise is strongly suppressed. The threshold voltage fluctuation is estimated to be as small as 0.03 V in the proposed array and a reliable operation of a multilevel NAND flash memory can be realized     

Analytical nonlinear HEMT model for large signal circuit simulation

A new nonlinear high electron mobility transistor (HEMT) model based on the Curtice model is described. This model introduces terms for the leakage current for subthreshold bias, drain voltage dependencies of knee voltage, drain conductance and threshold voltage, transconductance enhancement at high frequencies caused by DX centers, and the bias dependence of capacitance. Applying this model to pseudomorphic double-recessed gate HEMT's gives an average error of 2.6% for DC current and 10% for S-parameters     

低电场应力下闪速存储器的退化特性

基于负栅源边擦除的闪速存储器存储单元,研究了形成应力诱生漏电流的三种导电机制,同时采用新的实验方法对引起瞬态和稳态电流的电压漂移量进行了测量.并利用电容耦合效应模型对闪速存储器存储单元的可靠性进行了研究,结果表明,在低电场应力下,其可靠性问题主要由载流子在氧化层里充放电引起.     

Design of a sense circuit for low-voltage flash memories

A new sense circuit directly sensing the bitline voltage is proposed for low-voltage flash memories. A simple reference voltage generation method and a dataline switching method with matching of the stray capacitance between the dataline pairs are also proposed. A design method for the bitline clamp load transistors is described, taking bitline charging speed and process margins into account. The sense circuit was implemented in a 32-Mb flash memory fabricated with a 0.25-μm flash memory process and successfully operated at a low voltage of 1.5 V     

Enhanced degradation in polycrystalline silicon thin-filmtransistors under dynamic hot-carrier stress

We address the mechanisms responsible for the enhanced degradation in the polysilicon thin-film transistors under dynamic hot-carrier stress. Unlike the monotonic decrease of maximum transconductance (G_{m max}) in static stress, G_{m max} in dynamic stress is initially increased due to the channel shortening effect by holes injected into the gate oxide near the drain region and then decreased due to tail states generation at the gate oxide/channel interface and grain boundaries. The threshold voltage variations are dominated by two degradation mechanisms: (1) breaking of weak bonds and (2) breaking of strong bonds to obey the power-time dependence law with a slope of 0.4. The degradation of the sub-threshold slope is attributed to intra-grain bulk states generation     

Modeling the subthreshold swing in MOSFET's

This letter reports on the bias-dependence of the inverse subthreshold slope or subthreshold swing in MOSFET's. It is shown by calculations and verified by experiments that the subthreshold swing varies with gate bias and exhibits a global minimum. The gate-source voltage for which minimum subthreshold swing is reached, is linearly related to the voltage at which moderate inversion starts. Influence of oxide thickness and temperature is investigated. The subthreshold swing is an important parameter in modeling the weak inversion regime, especially for high-gain analog applications, imaging circuits, and low-voltage applications. Based on calculations of the subthreshold swing, we propose a new model for the diffusion component of the drain leakage current in MOSFET's. The model accurately predicts the temperature dependence of the drain leakage current     

Low-voltage hot electrons and soft-programming lifetime predictionin nonvolatile memory cells

This paper reports experiments and Monte Carlo (MC) simulations of flash memory cells at the typical bias conditions of read operations (high V_GS and low V_DS) leading to the soft-programming phenomenon. Comparing experiments with simulations we first show that, differently from the previously reported case of homogeneous injection experiments, efficient energy gain mechanisms must be invoked to explain the order of magnitude of gate (I_G) and substrate (I_B) currents at low voltage. Second, the voltage scaling behavior of the soft-programming lifetime is analyzed and the validity of usual extrapolation techniques to evaluate this parameter is addressed     

Properties of ultra-thin wafer-bonded silicon-on-insulator MOSFET's

Strong interface coupling effects on the subthreshold and transconductance characteristics have been experimentally observed and analytically modeled. For total depletion, the subthreshold swing reaches a nearly ideal value. The front channel subthreshold slope of ultrathin MOSFETs is very sensitive to the density of states at the buried Si-SiO₂ interface so that a thicker fully depleted film is preferable when the quality of this interface is poor. The transconductance reaches a maximum for total depletion. Simple theoretical models are proposed which explain the substantial variations of the transconductance and subthreshold slope as the opposite interface is scanned from inversion to total depletion and accumulation. These MOSFETs behave very well and demonstrate that high carrier mobilities and low densities of defects can be obtained at both interfaces even in ultrathin silicon-on-insulator (SOI) structures