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本文介绍了适用于多值ECL电路设计的差动电流开关理论。在该理论中,分别用开关变量和四值信号变量来描写ECL电路中差动晶体管对的开关状态和信号,并引入此两类变量之间的联结运算,以描写电路内部开关元件与信号的相互作用过程。基于该理论,本文对两种接口电路2-4编码器和4-2译码器进行了设计。应用SPICE程序对设计电路的计算机模拟表明,两种电路均具有正确的逻辑功能、理想的DC转移特性和瞬态特性。由于该接口电路具有与二值电路兼容的集成工艺、电源设备、逻辑级差和瞬态特性,因此它可用作现有二值ECL集成电路的输入输出接口,从而达到减少芯片的引脚数和片间连接的目的。 相似文献
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Starting from the viewpoint that the switch states and signal values in a digital circuit should be described separately by two different kinds of variable, the interaction between the switching element and signal in multi-valued ECL circuits is analysed and two types of connection operations, threshold switching operation and current switching operation, are proposed. The properties and circuit realizations of these new operations are discussed and the theory of differential current switches applicable to ECL circuits is established. Examples of basic ternary ECL circuits confirm that this theory can effectively guide the logic design of ternary ECL circuits at switch level. The circuits are verified by using the SPICE II program. They have the same logic level difference and transient characteristic as binary ECL circuits. Since the multi-valued ECL circuit uses only one set of power supply and can set several threshold values by using reference levels, it can be fabricated using conventional ECL techniques and is compatible with binary ECL circuits. 相似文献
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本文从多值逻辑能提高集成电路处理信息量的观点出发对三值ECL高速集成电路进行研究.文中提出符合双极型晶体管工作原理的基本运算,并讨论了有关性质.在此基础上提出差动电流开关理论,并用于设计若干基本三值ECL电路.使用SPICE 2G5程序的计算机模拟表明,这些电路具有正确的逻辑功能及理想的静态与瞬态特性. 相似文献
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基于开关信号理论的四值ECL电路 总被引:1,自引:0,他引:1
从一个有效的多值代数系统应能反映多值电路中的物理过程的这一原则出发,本文提出了一组可以描写多值ECL电路中信号与开关元件间相互作用的运算。讨论了这些运算的物理对应及有关性质,并由此建立了适用于ECL电路的开关信号理论。本文设计了若干基本四值ECL电路,用SPICE程序模拟证明了它们均具有正确的逻辑功能与理想的DC特性。 相似文献
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Ohtomo Y. Yasuda S. Togashi M. Ino M. Tanabe Y. Inoue J.-I. Nogawa M. Hino S. 《Solid-State Circuits, IEEE Journal of》1994,29(5):557-563
This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W 相似文献
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双极型电路通用综合方法与电路三要素理论 总被引:5,自引:0,他引:5
该文在电路三要素(信号,网络和负载)理论的基础上提出双极型电路通用综合方法。文中首先引入适用于电压型和电流型电路的广义二值信号,推导出源信号和负载简化定理。由此分析各单元电路结构和推导出相应的元件级电路表达式,进一步找出一种新的电路实现方式。在此基础上设计出新的低压TTL和多射型ECL元件级电路。最后经过电路实验证明理论的正确性。 相似文献
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本文以开关信号理论为指导,对电流型CMOS电路中开关变量和信号变量的相互作用进行了分析,并引入了适用于CMOS电路的电流开关理论。基于电流传输开关理论,对几类重要的三值CMOS电路进行了设计,结果表明,应用该理论能获得简单的电路设计。从而进一步完善了开关级逻辑电路设计的研究。 相似文献
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适用于TTL数字电路元件级设计的开关—信号理论 总被引:2,自引:1,他引:1
本文分析了以布尔代数为基础的数字电路设计的不足,提出了将开关状态和信号这二类变量分别描写的观点,讨论了TTL电路中晶体管开关元件与信息之间的相互作用过程,在此基础上,建立了适用于TTL电路的限幅电压开关理论,设计实例说明,该理论能有效地指导各类TTL电路在元件级的逻辑设计。 相似文献
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指导nM0S数字电路元件级设计的开关信号理论 总被引:2,自引:0,他引:2
本文指出了布尔代数在指导数字电路设计中的不足,并在区分描写开关状态与信号的二类变量的基础上建立了能反映数字电路内开关元件与信号相互作用过程的开关信号理论。本文把该理论具体用于对nMOs数字电路的研究,结果表明该理论可很好地指导nMOS数字电路在元件级的逻辑设计。 相似文献
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低电压低功耗ECL电路设计 总被引:5,自引:0,他引:5
首先指出了 ECL电路随着集成度和速度的提高 ,存在着功耗太大的问题 ,进而提出了采用低电压电源以降低功耗 ,为此发展了将串联开关转换成并联开关的技术 ,保证了电路能在低电压下正常工作 ,并由此实现了适合于低电压工作的 ECL电路的开关级设计。从对设计的电路进行的计算机模拟结果表明 ,采用文中提出的并联开关技术设计的电路 ,在电源电压为 -2 .5 V时 ,不仅具有正确的逻辑功能和较高的工作速度 ,且比采用-5 .0 V电源的电路节约了 80 %以上的功耗 相似文献
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该文通过对电流型CMOS电路的阈值控制引入了多值电流型比较器。与2值逻辑电路相比,多值逻辑电路的单条导线允许更多的信息传输。相较于电压信号,电流信号易实现加、减等算术运算,在多值逻辑的设计上更加方便。同时提出了基于比较器的4值基本单元设计方法,实现了4值取大、取小以及反向器的设计,在此基础上设计实现了加法器和减法器。该设计方法在2值、3值以及n值逻辑上同样适用。实验结果表明所设计的电路具有正确的逻辑功能,较之相关文献电流型CMOS全加器有更低的功耗和更少的晶体管数。 相似文献
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This paper presents high-speed differential input and output (I/O) interface circuits for gigabit-per-second serial data communication. The circuits are implemented in a 3.3-V/0.35-μm CMOS process. Signal levels are compatible with industry standards for low-voltage positive emitter-coupled logic (ECL), with the possibility of ac-coupling to standard ECL systems. A differential open-drain circuit with pulsed bias and active pullups offers significantly improved speed performance for a transmitter and creates wide open eye patterns. Combining circuit techniques with the features of a submicrometer technology, the presented I/O blocks enable a full-CMOS chip to communicate with high-speed ECL-compatible systems and ease up a common I/O-related speed bottleneck. The circuits operate at 622 Mb/s (OC-12) and 1.24 Gb/s (OC-24) in a repeater and a retimer configuration. The asynchronous performance of the receiver and the transmitter was tested at rates up to 2.5 Gb/s 相似文献
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New high-speed low-power BiCMOS nonthreshold logic (BNTL) circuits are presented. These circuits offers a built-in CMOS and bipolar level conversion and are suitable for reduced power supply voltage. A 4-b carry lookahead generator (CLG) circuit is designed in BNTL, ECL, and CMOS using 0.8-μm BiCMOS technology. Circuit simulations show that this new logic provides speed comparable to or better than that provided by emitter-coupled logic (ECL) for lower power dissipation 相似文献
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Carlough S.R. Philhower R.A. Maier C.A. Steidl S.A. Campbell P.M. Garg A. Kyung-Suc Nah Ernest M.W. Loy J.R. Krawczyk T.W. Jr. Curran P.F. Kraft R.P. Greub H.J. McDonald J.F. 《Solid-State Circuits, IEEE Journal of》2000,35(6):885-894
A byte-slice datapath for exploring multi-chip RISC processor development in AlGaAs-GaAs heterojunction bipolar transistor (HBT) technology has been designed, fabricated and tested. The circuits are implemented using differential current-mode logic (CML) and emitter-coupled logic (ECL) with signal swings of 250 mV. Each datapath chip contains a single slice, including an 8-bit by 32-word single-port register file with a 230-ps read access time, and an 8-bit carry-select adder with a 140-ps select path and a 380-ps ripple-carry path. Each unpackaged die was tested using an at-speed boundary scan test scheme. The register file and adder carry chain are also implemented in a special test chip for accurate performance characterization of these critical circuits 相似文献
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本文在分析TTL可编程分频器逻辑功能的基础上,设计了模数在1~16之间任意可变的ECL可编程分频器,利用SPICE电路模拟程序对电路进行了直流和瞬态分析。同时,针对超高速ECL电路的特点,完成了电路版图及工艺设计,并进行了工艺试制。做出了工作频率可达50MHz以上的ECL可编程分频器,比原TTL可编程分频器的工作频率提高了5倍之多。 相似文献