Electromigration in WLCSP solder bumps

Electromigration in two different bumping technologies for WLCSPs has been investigated. The UBM and the structure of the pads on the PCBs were found to have a major influence on the failure mode. A Ni metallization layer serving as a diffusion barrier drastically reduces the intermetallic growth in the solder ball compared to samples assembled on Cu-OSP pads. In the former the principal failure mode is electrical open due to voiding at the Ni–solder interface. In the latter Cu diffuses into the solder at a high rate creating Cu–Sn intermetallics and eventually leading to an electrical open in the Cu track on the PCB being the principal failure mode. Additional experiments showed that the lifetime of the Cu-OSP mounted samples can be extended by using via-in-pad structures.     

Reliability investigations of hard core solder bumps using mechanical palladium bumps and SnPb solder

The choice of solder joint metallurgy is a key issue especially for the reliability of flip-chip assemblies. Besides the metallurgical systems already widely used and well understood, new materials are emerging as solderable under bump metallization (UBM). For single chip bumping Pd stud bumps form a solid core under the solder layer. These hard core solder bumps are an adequate solution if single dies are available only and the chosen assembly technology is flip chip soldering. The scope of this paper is to summarize the results from aging of lead/tin solder bumps on palladium. The growth of intermetallic and its impact on the mechanical reliability are investigated.     

Characteristics of current crowding in flip-chip solder bumps

For a flip-chip package assembly, current crowding occurs in the vicinity of the locations where traces connect the solder bumps. This feature contributes significantly to the electromigration failure of the solder bumps. In this study the finite element analysis is performed to investigate characteristics of current crowding in a flip-chip solder bump subjected to a constant applied current. It is found that under such a condition, current crowding is induced solely by the structural geometry of the system. It is independent of the magnitude of the applied current. A volumetric averaging technique is also applied to cope with the current crowding singularity.     

Void detection in solder bumps with deep learning

Wafer level chip scale packages feature large numbers of solder bumps. These bumps are prone to having voids arising for instance from outgassing during the solder reflow. These voids are considered a reliability risk for the thermo-mechanical strength of the solder connection. Screening of bumps on void percentage is therefore required for quality control. Voids are well captured with X-ray radiography. Void detection in X-ray images is the topic of this paper. The large number of solder bumps necessitates the detection to be automated. In this article we first employ conventional threshold based methods to identify voids. Then, we apply a deep learning model to void percentage detection. We will demonstrate that with a proper training data set deep learning can successfully bin solder bumps on their void percentage.     

Development of highly accelerated electromigration test

A new methodology that combines the Finite Element Modeling (FEM), statistical methodology (Rank Limit method & Expectation and Maximization algorithm) and experiments to shorten electromigration (EM) testing time without changing the physical mechanism of the EM is developed. It is found that increasing testing temperature to 250 °C is able to shorten the average testing time by more than 80%. Verification using Transmission Electron Microscope (TEM) analysis shows that the physical mechanism is indeed remained unchanged.     

Characterisation of electroplated Sn/Ag solder bumps

Environmental concerns as well as legal constraints have been pushing research on flip chip technology towards the development of lead-free solders and also to new deposition techniques [Z.S. Karim, R. Schetty, Lead-free bump interconnections for flip-chip applications, in: IEEE/CPMT 1nternational Electronics Manufacturing Technology Symposium, 2000, pp. 274-278, P. Wölflick, K. Feldmann, Lead-free low-cost flip chip process chain: layout, process, reliability, in: IEEE International Electronics Manufacturing Technology (IEMT) Symposium, 2002, pp. 27-34, M. McCormack, S. Jin, The design and properties of new, pb-free solder alloys, in: IEEE/CPMT International Electronics Manufacturing Technology Symposium, 1994, pp. 7-14, T. Laine-Ylijoki, H. Steen, A. Forsten, Development and validation of a lead-free alloy for solder paste applications. IEEE Transactions on Components, Packaging, and Manufacturing technology, 20(3) (1997) 194-198, D. Frear, J. Jang, J. Lin, C. Zhang, Pb-free solders for flip-chip interconnects, JOM, 53(6) (2001) 28-32].Binary and ternary tin alloys are promising candidates to substitute lead-content components. In this paper, we describe an electroplating technique for high density FlipChip packaging [M. Bigas, E. Cabruja, Electrodeposited Sn/Ag for flip chip connection, CDE (2003)]. An analysis using Auger Electron Spectroscopy (AES) together with additional Energy Dispersive Xray analysis (EDS) tests and Scanning Electron Microscope (SEM) analysis have been performed to optimize the reflow process of the electrodeposited bumps.     

无铅钎料电迁移可靠性研究进展

随着电子器件焊点尺寸及其间距的日趋减小,电流密度急剧增加,从而引发的电迁移可靠性问题更加显著。电迁移效应的发生,使得在阴极附近出现裂纹和孔洞,在阳极则产生小丘或堆积,从而导致电路短路或断路。介绍了近年来国内外关于无铅钎料合金包括SnAgCu、SnAg、SnZn和SnBi等电迁移研究,对实验的结果、特征及其方案进行了综述和评论。     

Local melting induced by electromigration in flip-chip solder joints

A new electromigration failure mechanism in flip-chip solder joints is reported. The solder joints failed by local melting of a PbSn eutectic solder. Local melting occurred due to a sequence of events induced by the microstructure changes in the flip-chip solder joint. The formation of a depression in the current-crowding region of a solder joint induced the local electrical resistance to increase. The rising local resistance resulted in a larger Joule heating, which, in turn, raised the local temperature. When the local temperature rose above the eutectic temperature of the PbSn solder, the solder joint melted and consequently failed. The results of this study suggest that a dynamic, coupled simulation that takes into account the microstructure evolution, current density distribution, and temperature distribution may be needed to fully solve this problem.     

Formation of Pb/63Sn solder bumps using a solder droplet jetting method

Formation processes of Pb/63Sn solder droplets using a solder droplet jetting have not been sufficiently reported. Solving problems such as satellite droplets and position errors are very important for a uniform bump size and reliable flip-chip solder bump formation process. First, this paper presents the optimization of jet conditions of Pb/63Sn solder droplets and the formation process of Pb/63Sn solder bumps using a solder droplet jetting method. Second, interfacial reactions and mechanical strength of jetted Pb/63Sn solder bumps and electroless Ni-P/Au UBM joints have been investigated. Interfacial reactions have been investigated after the second solder reflow and aging, and results were compared with those of solder bumps formed by a solder screen-printing method. Third, jetted solder bumps with variable bump sizes have been demonstrated by a multiple jetting method and the control of waveform induced to a jet nozzle. Multiple droplets jetting method can control various height and size of solder bumps. Finally, real applications of jetted Pb/63Sn solder bumps have been successfully demonstrated on conventional DRAM chips and integrated passive devices (IPDs).     

Electromigration degradation mechanism for Pb-free flip-chip micro solder bumps

The electromigration (EM) of flip chip interconnect composed of Pb-free SnAgCu micro solder bump and Ni under bump metallization (UBM) is studied by accelerated current stress test. The process of void growth at the cathode side of the bump and resistance degradation process are investigated by physical analysis using SEM and Infrared microscope. EM degradation process for SnAgCu solder bump shows drastic change over time in degree of resistance shift owing to variation of contact diameter and UBM layer structure. UBM metal diffusion and local Joule heating caused by current crowding play important roles in voiding degradation process.     

Characterization of small-sized eutectic Sn-Bi solder bumps fabricated using electroplating

We studied the effects of the cooling rate during the reflow process on the microstructure of eutectic Sn-Bi solder bumps of various sizes fabricated by electroplating. To fabricate eutectic Sn-Bi solder bumps of less than 50 μm in diameter, Sn-Bi alloys were electroplated on Cu pads and reflowed at various cooling rates using the rapid thermal annealing system. The interior microstructure of electroplated bumps showed a fine mixture of Sn-rich phases and Bi-rich phases regardless of the cooling rate. Such an interior microstructure of electroplated bumps was quite different from the reported microstructure of vacuum-evaporated bumps. Ball shear tests were performed to study the effects of the cooling rate on the shear strength of the solder bumps and showed that the shear strength of the bumps increased with increasing cooling rate probably due to the reduced grain size. Soft fractures inside the solder bump were observed during the ball shear test regardless of the cooling rate.     

Reliability of composite solder bumps produced by an in-situ process

In an attempt to develop a thermally stable solder system, an in-situ Pb-Sn solder composite reinforced with Cu₆Sn₅ dispersoids was investigated for its thermal stability. The stability was evaluated mainly by measuring the growth rate of intermetallics at in-situ composite solder/BLM interface as a function of the number of reflow soldering cycles and aging time. The rates were compared with those of the eutectic Pb-Sn and Sn-Ag solders. After the thermal treatments, the solder joints were tested for their shear strengths. The results indicated that the in-situ composite solder has a higher shear strength and better thermal stability than the eutectic Pb-Sn solder. Jointly appointed by CAAM at POSTECH     

Addressing the challenges in solder resistance measurement for electromigration test

In the continuous drive for smaller chips with more functionality, I/O counts and power requirements increase. This leads to a growing concern on the electromigration (EM) reliability of solder joints in the high-density flip-chip package. For solder EM tests, it is a great challenge to detect early EM failure since the 10% change in resistance is very small due to the small initial resistance of the solder. Furthermore, the small change in resistance can often be masked by the parasitic resistance in the interconnect connecting the solder daisy chain type structures commonly employed in EM tests. The Wheatstone bridge method has been reported to address the inaccuracy associated with the use of Four-probe measurement method in solder EM tests successfully. In this work, we describe the use of Kelvin double bridge configuration that can further increase the accuracy of the bump resistance measured.     

Interfacial microstructure and strength of lead-free Sn-Zn-RE BGA solder bumps

Rare earth (RE) elements, primarily La and Ce, were doped in Sn-Zn solder to improve its properties such as wettability. The interfacial microstructure evolution and shear strength of the Sn-9Zn and Sn-9Zn-0.5RE (in wt%) solder bumps on Au/Ni/Cu under bump metallization (UBM) in a ball grid array (BGA) were investigated after thermal aging at 150 /spl deg/C for up to 1000 h. In the as-reflowed Sn-9Zn solder bump, AuSn/sub 4/ intermetallic compounds (IMCs) and Au-Zn circular IMCs formed close to the solder/UBM interface, together with the formation of a Ni-Zn-Sn ternary IMC layer of about 1 /spl mu/m in thickness. In contrast, in the as-reflowed Sn-9Zn-0.5RE solder bump, a spalled layer of Au-Zn was formed above the Ni layer. Sn-Ce-La and Sn-Zn-Ce-La phases were found near the interface at positions near the surface of the solder ball. Upon thermal aging at 150 /spl deg/C, the concentration of Zn in the Ni-Zn-Sn ternary layer of Sn-9Zn increased with aging time. For Sn-9Zn-0.5RE, the Au-Zn layer began to dissolve after 500 h of thermal aging. The shear strength of the Sn-9Zn ball was decreased after the addition of RE elements, although it was still higher than that of the Sn-37Pb and Sn-36Pb-2Ag Pb-bearing solders. The fracture mode of the Sn-9Zn system was changed from ductile to partly brittle after adding the RE elements. This is mainly due to the presence of the brittle Au-Zn layer.     

A novel flip-chip interconnection technique using solder bumps forhigh-speed photoreceivers

A flip-chip interconnection technique using small solder bumps instead of conventional wire bonding for high-speed broadband photoreceivers is described. The technique achieves interconnection with low parasitic elements, no damage to devices, and easy assembly. A photoreceiver composed of a broadband p-i-n photodiode and a laser-speed GaAS metal-semiconductor field-effect transistor (MESFET) preamplifier connected using solder bumps that are about 26 μm in diameter, with a frequency response of over 22 GHz at 1.55 μm, is demonstrated. This confirms the effectiveness of the solder bump interconnection technique for future high-speed broadband optical modules     

A study on coining processes of solder bumps on organic substrates

Solder flip chip bumping and subsequent coining processes on printed circuit board (PCB) were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCBs has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation; region of elastic deformation; region of linearly increase of applied loads; region of rapidly increase of applied loads. In order to reduce applied loads for coining solder bumps on a PCB, the effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Lower coining loads were needed to prevent potential substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying coining loads. It was found that coining process temperature had more significant effect to reduce applied coining loads during the coining process.     

Isothermal aging characteristics of Sn–Pb micro solder bumps

The shear strength of the under bump metallurgy (UBM) structure in both the high-melting solder bump and low-melting solder bump after aging were evaluated. Scanning electron microscopy and transmission electron microscopy were examined in the intermetallic compounds (IMCs) and bump joint profiles at the interface between solder and UBM. In 900 h aging experiments, the maximum shear strength of Sn–97wt.%Pb and Sn–37wt.%Pb decreased by 25% and 20%, respectively. The growth of Cu₆Sn₅ and Cu₃Sn was ascertained by the aging treatment. The crack path changes from the interior of a solder to the IMC interface. Compare with the Cu–Sn IMC, the amount of Ni–Sn IMC was small. The Ni layer is considered as the diffusion barrier.     

Preparation of Sn-Ag-In ternary solder bumps by electroplating in sequence and reliability

This paper describes a technique that can obtain ternary Sn-Ag-In solder bumps with fine pitch and homogenous composition distribution.The main feature of this process is that tin-silver and indium are electroplated on copper under bump metallization（UBM） in sequence.After an accurate reflow process,Sn_1.8Ag_9.4In solder bumps are obtained.It is found that the intermetallic compounds（IMCs） between Sn-Ag-In solder and Cu grow with the reflow time,which results in an increase in Ag concentration in the solder area.So during solidification, more Ag₂In nucleates and strengthens the solder.     

Finite element modeling on electromigration of solder joints in wafer level packages

This work studies the electromigration of solder joints in an encapsulated copper post wafer level package (WLP) by finite element modeling. Experimental data showed that the electromigration failure occurs in solder joints on the printed circuit board (PCB) side due to the current crowding. In order to improve the electromigration performance on the PCB side with a copper post WLP, two new line-to-bump geometry designs are proposed. Coupled electro-thermal finite element modeling is performed to obtain the electrical and thermal fields simultaneously. The ionic flux from electron wind and thermal response is calculated based on finite element solutions. The divergence of the total flux, which is the sum of the divergence of electromigration and thermomigration, is extracted at the critical locations in solder joints. Results show that the new proposed design structures can reduce the maximum current density by 19%, and the divergence of the total ionic flux by 42%. Thermal gradient is very small in solder joints, therefore, the main driving force for electromigration failures comes from the electron wind. The finite element results on mesh dependency are discussed in this paper.